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Imported Upstream version 6.4.0.137

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Former-commit-id: 943baa9f16a098c33e129777827f3a9d20da00d6
This commit is contained in:
Xamarin Public Jenkins (auto-signing)
2019-07-26 19:53:28 +00:00
parent e9207cf623
commit ef583813eb
2712 changed files with 74169 additions and 40587 deletions
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645
external/llvm/test/CodeGen/Mips/const-mult.ll vendored
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13
external/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll vendored Normal file
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@ -0,0 +1,13 @@
; Negative test. The constraint 'l' represents the register 'lo'.
; Check error message in case of invalid usage.
;
; RUN: not llc -march=mips -filetype=obj < %s 2>&1 | FileCheck %s
define void @constraint_l() nounwind {
entry:
; CHECK: error: invalid operand for instruction
tail call i16 asm sideeffect "addiu $0,$1,$2", "=l,r,r,~{$1}"(i16 0, i16 0)
ret void
}

10
external/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll vendored
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@ -41,5 +41,15 @@ entry:
call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
store volatile i32 %4, i32* %bosco, align 4
; Check the 'l' constraint for 16-bit type.
; CHECK: #APP
; CHECK: mtlo ${{[0-9]+}}
; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: #NO_APP
; CHECK-NEXT: mflo ${{[0-9]+}}
%bosco16 = alloca i16, align 4
call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
store volatile i16 %5, i16* %bosco16, align 4
ret i32 0
}