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Imported Upstream version 6.4.0.137
Former-commit-id: 943baa9f16a098c33e129777827f3a9d20da00d6
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@@ -28,6 +28,28 @@ return: ; preds = %if.then172, %cond.e
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ret void
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}
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; Avoid an assert/bad codegen in LD1LANEPOST lowering by not forming
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; LD1LANEPOST ISD nodes with a non-constant lane index.
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define <4 x i32> @f2(i32 *%p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2, i32 %idx) {
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%L0 = load i32, i32* %p
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%p1 = getelementptr i32, i32* %p, i64 1
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%L1 = load i32, i32* %p1
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%v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2
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%vret = insertelement <4 x i32> %v, i32 %L0, i32 %idx
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store i32 %L1, i32 *%p
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ret <4 x i32> %vret
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}
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; Check that a cycle is avoided during isel between the LD1LANEPOST instruction and the load of %L1.
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define <4 x i32> @f3(i32 *%p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2) {
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%L0 = load i32, i32* %p
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%p1 = getelementptr i32, i32* %p, i64 1
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%L1 = load i32, i32* %p1
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%v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2
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%vret = insertelement <4 x i32> %v, i32 %L0, i32 %L1
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ret <4 x i32> %vret
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #1
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@@ -1,27 +1,31 @@
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; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefix=CYCLONE --check-prefix=ALL
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefix=KRYO --check-prefix=ALL
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=falkor < %s | FileCheck %s -check-prefix=FALKOR --check-prefix=ALL
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; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefixes=ALL,CYCLONE
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; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone -mattr=+fullfp16 < %s | FileCheck %s -check-prefixes=CYCLONE-FULLFP16
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m1 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m3 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=falkor < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; rdar://11481771
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; rdar://13713797
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declare void @bar(half, float, double, <2 x double>)
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declare void @bari(i32, i32)
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declare void @barl(i64, i64)
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declare void @barf(float, float)
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define void @t1() nounwind ssp {
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entry:
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; ALL-LABEL: t1:
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; ALL-NOT: fmov
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; CYCLONE: fmov d0, xzr
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; CYCLONE: fmov d1, xzr
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; ALL: ldr h0,{{.*}}
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; CYCLONE: fmov s1, wzr
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; CYCLONE: fmov d2, xzr
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; CYCLONE: fmov d3, xzr
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; KRYO: movi v0.2d, #0000000000000000
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; KRYO: movi v1.2d, #0000000000000000
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; KRYO: movi v2.2d, #0000000000000000
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; KRYO: movi v3.2d, #0000000000000000
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; FALKOR: movi v0.2d, #0000000000000000
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; FALKOR: movi v1.2d, #0000000000000000
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; FALKOR: movi v2.2d, #0000000000000000
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; FALKOR: movi v3.2d, #0000000000000000
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tail call void @bar(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00) nounwind
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; CYCLONE: movi.16b v3, #0
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; CYCLONE-FULLFP16: fmov h0, wzr
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; CYCLONE-FULLFP16: fmov s1, wzr
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; CYCLONE-FULLFP16: fmov d2, xzr
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; CYCLONE-FULLFP16: movi.16b v3, #0
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind
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ret void
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}
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@@ -29,8 +33,8 @@ define void @t2() nounwind ssp {
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entry:
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; ALL-LABEL: t2:
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; ALL-NOT: mov w0, wzr
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; ALL: mov w0, #0
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; ALL: mov w1, #0
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; ALL: mov w{{[0-3]+}}, #0
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; ALL: mov w{{[0-3]+}}, #0
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tail call void @bari(i32 0, i32 0) nounwind
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ret void
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}
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@@ -39,8 +43,8 @@ define void @t3() nounwind ssp {
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entry:
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; ALL-LABEL: t3:
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; ALL-NOT: mov x0, xzr
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; ALL: mov x0, #0
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; ALL: mov x1, #0
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; ALL: mov x{{[0-3]+}}, #0
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; ALL: mov x{{[0-3]+}}, #0
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tail call void @barl(i64 0, i64 0) nounwind
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ret void
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}
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@@ -48,26 +52,21 @@ entry:
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define void @t4() nounwind ssp {
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; ALL-LABEL: t4:
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; ALL-NOT: fmov
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; CYCLONE: fmov s0, wzr
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; CYCLONE: fmov s1, wzr
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; KRYO: movi v0.2d, #0000000000000000
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; KRYO: movi v1.2d, #0000000000000000
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; FALKOR: movi v0.2d, #0000000000000000
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; FALKOR: movi v1.2d, #0000000000000000
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; CYCLONE: fmov s{{[0-3]+}}, wzr
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; CYCLONE: fmov s{{[0-3]+}}, wzr
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; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
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; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
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ret void
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}
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declare void @bar(double, double, double, double)
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declare void @bari(i32, i32)
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declare void @barl(i64, i64)
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declare void @barf(float, float)
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; We used to produce spills+reloads for a Q register with zero cycle zeroing
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; enabled.
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; ALL-LABEL: foo:
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; ALL-NOT: str {{q[0-9]+}}
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; ALL-NOT: ldr {{q[0-9]+}}
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; ALL-NOT: str q{{[0-9]+}}
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; ALL-NOT: ldr q{{[0-9]+}}
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define double @foo(i32 %n) {
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entry:
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br label %for.body
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@@ -90,8 +89,7 @@ for.end:
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define <2 x i64> @t6() {
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; ALL-LABEL: t6:
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; CYCLONE: movi.16b v0, #0
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; KRYO: movi v0.2d, #0000000000000000
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; FALKOR: movi v0.2d, #0000000000000000
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; OTHERS: movi v0.2d, #0000000000000000
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ret <2 x i64> zeroinitializer
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}
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@@ -353,3 +353,28 @@ body: |
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bb.1:
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RET_ReallyLR
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...
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---
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# Check that non-base registers are considered live when finding a
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# scratch register by making sure we don't use %x2 for the scratch
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# register for the inserted ORRXrs.
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# CHECK-LABEL: name: hwpf_offreg
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# CHECK: %x3 = ORRXrs %xzr, %x1, 0
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# CHECK: %w10 = LDRWroX %x3, %x2, 0, 0
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name: hwpf_offreg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: %w0, %x1, %x2, %x17, %x18
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%w10 = LDRWroX %x1, %x2, 0, 0 :: ("aarch64-strided-access" load 4)
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%x2 = ORRXrs %xzr, %x10, 0
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%w26 = LDRWroX %x1, %x2, 0, 0
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%w0 = SUBWri %w0, 1, 0
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%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
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Bcc 9, %bb.0, implicit %nzcv
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bb.1:
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RET_ReallyLR
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...
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20
external/llvm/test/CodeGen/AArch64/inlineasm-S-constraint.ll
vendored
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20
external/llvm/test/CodeGen/AArch64/inlineasm-S-constraint.ll
vendored
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@@ -0,0 +1,20 @@
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;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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@var = global i32 0
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define void @test_inline_constraint_S() {
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; CHECK-LABEL: test_inline_constraint_S:
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call void asm sideeffect "adrp x0, $0", "S"(i32* @var)
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call void asm sideeffect "add x0, x0, :lo12:$0", "S"(i32* @var)
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; CHECK: adrp x0, var
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; CHECK: add x0, x0, :lo12:var
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ret void
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}
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define i32 @test_inline_constraint_S_label(i1 %in) {
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; CHECK-LABEL: test_inline_constraint_S_label:
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call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc))
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; CHECK: adr x0, .Ltmp{{[0-9]+}}
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br i1 %in, label %loc, label %loc2
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loc:
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ret i32 0
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loc2:
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ret i32 42
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}
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35
external/llvm/test/CodeGen/AArch64/spill-stack-realignment.mir
vendored
Normal file
35
external/llvm/test/CodeGen/AArch64/spill-stack-realignment.mir
vendored
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@@ -0,0 +1,35 @@
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# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
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# Ensure references to scavenged stack slots in the CSR area use the
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# FP as a base when the stack pointer must be aligned to something
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# larger than required by the target. This is necessary because the
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# alignment padding area is between the CSR area and the SP, so the SP
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# cannot be used to reference the CSR area.
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name: test
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 64
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# CHECK: stack:
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# CHECK: id: 0, name: '', type: default, offset: -64, size: 4, alignment: 64
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# CHECK-NEXT: stack-id: 0
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# CHECK-NEXT: local-offset: -64
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# CHECK: id: 1, name: '', type: default, offset: -20, size: 4, alignment: 4
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# CHECK-NEXT: stack-id: 0
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# CHECK-NEXT: local-offset: -68
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stack:
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- { id: 0, size: 4, alignment: 64, local-offset: -64 }
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- { id: 1, size: 4, alignment: 4, local-offset: -68 }
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# CHECK: body:
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# CHECK: %sp = ANDXri killed %{{x[0-9]+}}, 7865
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# CHECK: STRSui %s0, %sp, 0
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# CHECK: STURSi %s0, %fp, -4
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body: |
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bb.0.entry:
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liveins: %s0
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STRSui %s0, %stack.0, 0
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STRSui %s0, %stack.1, 0
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; Force preserve a CSR to create a hole in the CSR stack region.
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%x28 = IMPLICIT_DEF
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RET_ReallyLR
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