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Imported Upstream version 5.18.0.207
Former-commit-id: 3b152f462918d427ce18620a2cbe4f8b79650449
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@ -1,20 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+sse2 -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; CHECK-LABEL: mov_no_attr
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; CHECK-NOT: callq __asan_report_load8@PLT
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; CHECK-NOT: callq __asan_report_store8@PLT
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define void @mov_no_attr(i64* %dst, i64* %src) {
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tail call void asm sideeffect "movq ($1), %rax \0A\09movq %rax, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i64* %dst, i64* %src)
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ret void
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}
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; CHECK-LABEL: mov_sanitize
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; CHECK: callq __asan_report_load8@PLT
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; CHECK: callq __asan_report_store8@PLT
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define void @mov_sanitize(i64* %dst, i64* %src) sanitize_address {
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tail call void asm sideeffect "movq ($1), %rax \0A\09movq %rax, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i64* %dst, i64* %src)
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ret void
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}
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@ -1,54 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+sse2 -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; CHECK-LABEL: mov8b_rbp
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; CHECK: pushq %rbp
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; CHECK-NOT: .cfi_adjust_cfa_offset 8
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; CHECK: movq %rbp, %rbp
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; CHECK: .cfi_remember_state
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; CHECK: .cfi_def_cfa_register %rbp
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; CHECK: leaq -128(%rsp)
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; CHECK: callq __asan_report_load8@PLT
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; CHECK: leaq 128(%rsp)
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; CHECK: popq %rbp
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; CHECK: .cfi_restore_state
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; CHECK-NOT: .cfi_adjust_cfa_offset -8
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; CHECK: retq
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define void @mov8b_rbp(i64* %dst, i64* %src) #0 {
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entry:
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tail call void asm sideeffect "movq ($0), %rax \0A\09movq %rax, ($1) \0A\09", "r,r,~{rax},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %src, i64* %dst)
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ret void
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}
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; CHECK-LABEL: mov8b_rsp
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; CHECK: pushq %rbp
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; CHECK: .cfi_adjust_cfa_offset 8
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; CHECK: movq %rsp, %rbp
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; CHECK: .cfi_remember_state
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; CHECK: .cfi_def_cfa_register %rbp
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; CHECK: leaq -128(%rsp)
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; CHECK: callq __asan_report_load8@PLT
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; CHECK: leaq 128(%rsp)
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; CHECK: popq %rbp
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; CHECK: .cfi_restore_state
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; CHECK: .cfi_adjust_cfa_offset -8
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; CHECK: retq
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define void @mov8b_rsp(i64* %dst, i64* %src) #1 {
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entry:
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tail call void asm sideeffect "movq ($0), %rax \0A\09movq %rax, ($1) \0A\09", "r,r,~{rax},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %src, i64* %dst)
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ret void
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}
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; CHECK-LABEL: mov8b_rsp_no_cfi
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; CHECK-NOT: .cfi{{[a-z_]+}}
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define void @mov8b_rsp_no_cfi(i64* %dst, i64* %src) #2 {
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entry:
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tail call void asm sideeffect "movq ($0), %rax \0A\09movq %rax, ($1) \0A\09", "r,r,~{rax},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %src, i64* %dst)
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ret void
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}
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attributes #0 = { nounwind sanitize_address uwtable "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" }
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attributes #1 = { nounwind sanitize_address uwtable "no-frame-pointer-elim"="false" }
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attributes #2 = { nounwind sanitize_address "no-frame-pointer-elim"="false" }
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@ -1,52 +0,0 @@
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# The test verifies that correct DWARF directives are emitted when
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# assembly files are instrumented.
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# RUN: llvm-mc %s -triple=i386-unknown-linux-gnu -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
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# CHECK-LABEL: load4b_cfa_rbp
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# CHECK: pushl %ebx
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# CHECK-NOT: .cfi_adjust_cfa_offset 8
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# CHECK: movl %ebp, %ebx
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# CHECK: .cfi_remember_state
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# CHECK: .cfi_def_cfa_register %ebx
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# CHECK: popl %ebx
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# CHECK: .cfi_restore_state
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# CHECK-NOT: .cfi_adjust_cfa_offset -8
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# CHECK: retl
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.text
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.globl load4b_cfa_rbp
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.type load4b_cfa_rbp,@function
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swap_cfa_rbp: # @swap_cfa_rbp
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.cfi_startproc
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pushl %ebp
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.cfi_def_cfa_offset 8
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.cfi_offset %ebp, -8
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movl %esp, %ebp
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.cfi_def_cfa_register %ebp
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movl 8(%ebp), %eax
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popl %ebp
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retl
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.cfi_endproc
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# CHECK-LABEL: load4b_cfa_rsp
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# CHECK: pushl %ebx
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# CHECK: .cfi_adjust_cfa_offset 4
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# CHECK: movl %esp, %ebx
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# CHECK: .cfi_remember_state
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# CHECK: .cfi_def_cfa_register %ebx
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# CHECK: popl %ebx
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# CHECK: .cfi_restore_state
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# CHECK: retl
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.globl load4b_cfa_rsp
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.type load4b_cfa_rsp,@function
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swap_cfa_rsp: # @swap_cfa_rsp
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.cfi_startproc
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pushl %ebp
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.cfi_offset %ebp, 0
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movl %esp, %ebp
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movl 8(%ebp), %eax
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popl %ebp
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retl
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.cfi_endproc
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@ -1,53 +0,0 @@
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; RUN: opt < %s -asan -S -o %t.ll
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; RUN: FileCheck %s < %t.ll
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; RUN: llc < %t.ll | FileCheck %s --check-prefix=ASM
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target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32"
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target triple = "i386-pc-windows-msvc"
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define void @MyCPUID(i32 %fxn, i32* %out) sanitize_address {
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%fxn.ptr = alloca i32
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%a.ptr = alloca i32
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%b.ptr = alloca i32
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%c.ptr = alloca i32
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%d.ptr = alloca i32
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store i32 %fxn, i32* %fxn.ptr
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call void asm sideeffect inteldialect "xchg ebx, esi\0A\09mov eax, dword ptr $4\0A\09cpuid\0A\09mov dword ptr $0, eax\0A\09mov dword ptr $1, ebx\0A\09mov dword ptr $2, ecx\0A\09mov dword ptr $3, edx\0A\09xchg ebx, esi", "=*m,=*m,=*m,=*m,*m,~{eax},~{ebx},~{ecx},~{edx},~{esi},~{dirflag},~{fpsr},~{flags}"(i32* %a.ptr, i32* %b.ptr, i32* %c.ptr, i32* %d.ptr, i32* %fxn.ptr)
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%a = load i32, i32* %a.ptr
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%a.out = getelementptr inbounds i32, i32* %out, i32 0
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store i32 %a, i32* %a.out
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%b = load i32, i32* %b.ptr
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%b.out = getelementptr inbounds i32, i32* %out, i32 1
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store i32 %b, i32* %b.out
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%c = load i32, i32* %c.ptr
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%c.out = getelementptr inbounds i32, i32* %out, i32 2
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store i32 %c, i32* %c.out
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%d = load i32, i32* %d.ptr
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%d.out = getelementptr inbounds i32, i32* %out, i32 3
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store i32 %d, i32* %d.out
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ret void
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}
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; We used to introduce stack mallocs for UAR detection, but that makes LLVM run
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; out of registers on 32-bit platforms. Therefore, we don't do stack malloc on
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; such functions.
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; CHECK-LABEL: define void @MyCPUID(i32 %fxn, i32* %out)
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; CHECK: %MyAlloca = alloca [96 x i8], align 32
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; CHECK-NOT: call {{.*}} @__asan_stack_malloc
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; The code generator should recognize that all operands are just stack memory.
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; This is important with MS inline asm where operand lists are implicit and all
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; local variables can be referenced freely.
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; ASM-LABEL: MyCPUID:
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; ASM: cpuid
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; ASM-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; ASM-NEXT: movl %ebx, {{[0-9]+}}(%esp)
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; ASM-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; ASM-NEXT: movl %edx, {{[0-9]+}}(%esp)
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@ -1,56 +0,0 @@
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; RUN: opt < %s -asan -S -o %t.ll
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; RUN: FileCheck %s < %t.ll
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; Don't do stack malloc on functions containing inline assembly on 64-bit
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; platforms. It makes LLVM run out of registers.
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; CHECK-LABEL: define void @TestAbsenceOfStackMalloc(i8* %S, i32 %pS, i8* %D, i32 %pD, i32 %h)
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; CHECK: %MyAlloca
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; CHECK-NOT: call {{.*}} @__asan_stack_malloc
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.10.0"
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define void @TestAbsenceOfStackMalloc(i8* %S, i32 %pS, i8* %D, i32 %pD, i32 %h) #0 {
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entry:
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%S.addr = alloca i8*, align 8
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%pS.addr = alloca i32, align 4
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%D.addr = alloca i8*, align 8
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%pD.addr = alloca i32, align 4
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%h.addr = alloca i32, align 4
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%sr = alloca i32, align 4
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%pDiffD = alloca i32, align 4
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%pDiffS = alloca i32, align 4
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%flagSA = alloca i8, align 1
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%flagDA = alloca i8, align 1
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store i8* %S, i8** %S.addr, align 8
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store i32 %pS, i32* %pS.addr, align 4
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store i8* %D, i8** %D.addr, align 8
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store i32 %pD, i32* %pD.addr, align 4
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store i32 %h, i32* %h.addr, align 4
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store i32 4, i32* %sr, align 4
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%0 = load i32, i32* %pD.addr, align 4
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%sub = sub i32 %0, 5
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store i32 %sub, i32* %pDiffD, align 4
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%1 = load i32, i32* %pS.addr, align 4
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%shl = shl i32 %1, 1
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%sub1 = sub i32 %shl, 5
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store i32 %sub1, i32* %pDiffS, align 4
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%2 = load i32, i32* %pS.addr, align 4
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%and = and i32 %2, 15
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%cmp = icmp eq i32 %and, 0
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%conv = zext i1 %cmp to i32
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%conv2 = trunc i32 %conv to i8
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store i8 %conv2, i8* %flagSA, align 1
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%3 = load i32, i32* %pD.addr, align 4
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%and3 = and i32 %3, 15
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%cmp4 = icmp eq i32 %and3, 0
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%conv5 = zext i1 %cmp4 to i32
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%conv6 = trunc i32 %conv5 to i8
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store i8 %conv6, i8* %flagDA, align 1
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call void asm sideeffect "mov\09\09\09$0,\09\09\09\09\09\09\09\09\09\09%rsi\0Amov\09\09\09$2,\09\09\09\09\09\09\09\09\09\09%rcx\0Amov\09\09\09$1,\09\09\09\09\09\09\09\09\09\09%rdi\0Amov\09\09\09$8,\09\09\09\09\09\09\09\09\09\09%rax\0A", "*m,*m,*m,*m,*m,*m,*m,*m,*m,~{rsi},~{rdi},~{rax},~{rcx},~{rdx},~{memory},~{dirflag},~{fpsr},~{flags}"(i8** %S.addr, i8** %D.addr, i32* %pS.addr, i32* %pDiffS, i32* %pDiffD, i32* %sr, i8* %flagSA, i8* %flagDA, i32* %h.addr) #1
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ret void
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}
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attributes #0 = { nounwind sanitize_address }
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attributes #1 = { nounwind }
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@ -1,152 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+sse2 -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; CHECK-LABEL: mov1b
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; CHECK: leaq -128(%rsp), %rsp
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: pushq %rdi
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; CHECK-NEXT: pushq %rcx
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; CHECK-NEXT: pushfq
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; CHECK-NEXT: leaq {{.*}}, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: shrq $3, %rax
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; CHECK-NEXT: movb 2147450880(%rax), %al
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: je [[A:.*]]
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; CHECK-NEXT: movl %edi, %ecx
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; CHECK-NEXT: andl $7, %ecx
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; CHECK-NEXT: movsbl %al, %eax
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; CHECK-NEXT: cmpl %eax, %ecx
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; CHECK-NEXT: jl {{.*}}
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; CHECK-NEXT: cld
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; CHECK-NEXT: emms
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; CHECK-NEXT: andq $-16, %rsp
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; CHECK-NEXT: callq __asan_report_load1@PLT
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; CHECK-NEXT: [[A]]:
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; CHECK-NEXT: popfq
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; CHECK-NEXT: popq %rcx
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; CHECK-NEXT: popq %rdi
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: leaq 128(%rsp), %rsp
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; CHECK: leaq -128(%rsp), %rsp
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; CHECK: callq __asan_report_store1@PLT
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; CHECK: leaq 128(%rsp), %rsp
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; CHECK: movb {{.*}}, {{.*}}
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define void @mov1b(i8* %dst, i8* %src) #0 {
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entry:
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tail call void asm sideeffect "movb ($1), %al \0A\09movb %al, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i8* %dst, i8* %src) #1, !srcloc !0
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ret void
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}
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; CHECK-LABEL: mov2b
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; CHECK: leaq -128(%rsp), %rsp
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; CHECK: leal 1(%ecx), %ecx
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; CHECK: callq __asan_report_load2@PLT
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; CHECK: leaq 128(%rsp), %rsp
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; CHECK: leaq -128(%rsp), %rsp
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; CHECK: leal 1(%ecx), %ecx
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; CHECK: callq __asan_report_store2@PLT
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; CHECK: leaq 128(%rsp), %rsp
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; CHECK: movw {{.*}}, {{.*}}
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define void @mov2b(i16* %dst, i16* %src) #0 {
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entry:
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tail call void asm sideeffect "movw ($1), %ax \0A\09movw %ax, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i16* %dst, i16* %src) #1, !srcloc !1
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ret void
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}
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; CHECK-LABEL: mov4b
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; CHECK: leaq -128(%rsp), %rsp
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; CHECK: addl $3, %ecx
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; CHECK: callq __asan_report_load4@PLT
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; CHECK: leaq 128(%rsp), %rsp
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; CHECK: leaq -128(%rsp), %rsp
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; CHECK: addl $3, %ecx
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; CHECK: callq __asan_report_store4@PLT
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; CHECK: leaq 128(%rsp), %rsp
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; CHECK: movl {{.*}}, {{.*}}
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define void @mov4b(i32* %dst, i32* %src) #0 {
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entry:
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tail call void asm sideeffect "movl ($1), %eax \0A\09movl %eax, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i32* %dst, i32* %src) #1, !srcloc !2
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ret void
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}
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; CHECK-LABEL: mov8b
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; CHECK: leaq -128(%rsp), %rsp
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: pushq %rdi
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; CHECK-NEXT: pushfq
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; CHECK-NEXT: leaq {{.*}}, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: shrq $3, %rax
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; CHECK-NEXT: cmpb $0, 2147450880(%rax)
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; CHECK-NEXT: je [[A:.*]]
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; CHECK-NEXT: cld
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; CHECK-NEXT: emms
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; CHECK-NEXT: andq $-16, %rsp
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; CHECK-NEXT: callq __asan_report_load8@PLT
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; CHECK-NEXT: [[A]]:
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; CHECK-NEXT: popfq
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; CHECK-NEXT: popq %rdi
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: leaq 128(%rsp), %rsp
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; CHECK: leaq -128(%rsp), %rsp
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: pushq %rdi
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; CHECK-NEXT: pushfq
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; CHECK-NEXT: leaq {{.*}}, %rdi
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||||
; CHECK-NEXT: movq %rdi, %rax
|
||||
; CHECK-NEXT: shrq $3, %rax
|
||||
; CHECK-NEXT: cmpb $0, 2147450880(%rax)
|
||||
; CHECK-NEXT: je [[A:.*]]
|
||||
; CHECK-NEXT: cld
|
||||
; CHECK-NEXT: emms
|
||||
; CHECK-NEXT: andq $-16, %rsp
|
||||
; CHECK-NEXT: callq __asan_report_store8@PLT
|
||||
; CHECK-NEXT: [[A]]:
|
||||
; CHECK-NEXT: popfq
|
||||
; CHECK-NEXT: popq %rdi
|
||||
; CHECK-NEXT: popq %rax
|
||||
; CHECK-NEXT: leaq 128(%rsp), %rsp
|
||||
|
||||
; CHECK: movq {{.*}}, {{.*}}
|
||||
define void @mov8b(i64* %dst, i64* %src) #0 {
|
||||
entry:
|
||||
tail call void asm sideeffect "movq ($1), %rax \0A\09movq %rax, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i64* %dst, i64* %src) #1, !srcloc !3
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: mov16b
|
||||
; CHECK: leaq -128(%rsp), %rsp
|
||||
; CHECK: cmpw $0, 2147450880(%rax)
|
||||
; CHECK: callq __asan_report_load16@PLT
|
||||
; CHECK: leaq 128(%rsp), %rsp
|
||||
|
||||
; CHECK: leaq -128(%rsp), %rsp
|
||||
; CHECK: cmpw $0, 2147450880(%rax)
|
||||
; CHECK: callq __asan_report_store16@PLT
|
||||
; CHECK: leaq 128(%rsp), %rsp
|
||||
|
||||
; CHECK: movaps {{.*}}, {{.*}}
|
||||
define void @mov16b(<2 x i64>* %dst, <2 x i64>* %src) #0 {
|
||||
entry:
|
||||
tail call void asm sideeffect "movaps ($1), %xmm0 \0A\09movaps %xmm0, ($0) \0A\09", "r,r,~{memory},~{xmm0},~{dirflag},~{fpsr},~{flags}"(<2 x i64>* %dst, <2 x i64>* %src) #1, !srcloc !4
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind uwtable sanitize_address "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind }
|
||||
|
||||
!0 = !{i32 98, i32 122, i32 160}
|
||||
!1 = !{i32 305, i32 329, i32 367}
|
||||
!2 = !{i32 512, i32 537, i32 576}
|
||||
!3 = !{i32 721, i32 746, i32 785}
|
||||
!4 = !{i32 929, i32 957, i32 999}
|
||||
@ -1,64 +0,0 @@
|
||||
# RUN: llvm-mc %s -triple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+sse2 -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
|
||||
|
||||
.text
|
||||
.globl mov1b
|
||||
.align 16, 0x90
|
||||
.type mov1b,@function
|
||||
# CHECK-LABEL: mov1b:
|
||||
#
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: callq __asan_report_load1@PLT
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
#
|
||||
# CHECK: movb (%rsi), %al
|
||||
#
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: callq __asan_report_store1@PLT
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
#
|
||||
# CHECK: movb %al, (%rdi)
|
||||
mov1b: # @mov1b
|
||||
.cfi_startproc
|
||||
# %bb.0:
|
||||
#APP
|
||||
movb (%rsi), %al
|
||||
movb %al, (%rdi)
|
||||
|
||||
#NO_APP
|
||||
retq
|
||||
.Ltmp0:
|
||||
.size mov1b, .Ltmp0-mov1b
|
||||
.cfi_endproc
|
||||
|
||||
.globl mov16b
|
||||
.align 16, 0x90
|
||||
.type mov16b,@function
|
||||
# CHECK-LABEL: mov16b:
|
||||
#
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: callq __asan_report_load16@PLT
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
#
|
||||
# CHECK: movaps (%rsi), %xmm0
|
||||
#
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: callq __asan_report_store16@PLT
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
#
|
||||
# CHECK: movaps %xmm0, (%rdi)
|
||||
mov16b: # @mov16b
|
||||
.cfi_startproc
|
||||
# %bb.0:
|
||||
#APP
|
||||
movaps (%rsi), %xmm0
|
||||
movaps %xmm0, (%rdi)
|
||||
|
||||
#NO_APP
|
||||
retq
|
||||
.Ltmp1:
|
||||
.size mov16b, .Ltmp1-mov16b
|
||||
.cfi_endproc
|
||||
|
||||
|
||||
.ident "clang version 3.5 "
|
||||
.section ".note.GNU-stack","",@progbits
|
||||
@ -1,26 +0,0 @@
|
||||
# RUN: llvm-mc %s -triple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+sse2 | FileCheck %s
|
||||
|
||||
.text
|
||||
.globl mov1b
|
||||
.align 16, 0x90
|
||||
.type mov1b,@function
|
||||
# CHECK-LABEL: mov1b
|
||||
# CHECK: movb (%rsi), %al
|
||||
# CHECK: movb %al, (%rdi)
|
||||
# CHECK-NOT: callq __asan_report_load1@PLT
|
||||
# CHECK-NOT: callq __asan_report_store1@PLT
|
||||
mov1b: # @mov1b
|
||||
.cfi_startproc
|
||||
# %bb.0:
|
||||
#APP
|
||||
movb (%rsi), %al
|
||||
movb %al, (%rdi)
|
||||
|
||||
#NO_APP
|
||||
retq
|
||||
.Ltmp0:
|
||||
.size mov1b, .Ltmp0-mov1b
|
||||
.cfi_endproc
|
||||
|
||||
.ident "clang version 3.5 "
|
||||
.section ".note.GNU-stack","",@progbits
|
||||
@ -1,85 +0,0 @@
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+sse2 -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
|
||||
|
||||
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
||||
target triple = "x86_64-unknown-linux-gnu"
|
||||
|
||||
; CHECK-LABEL: rep_movs_1b
|
||||
; CHECK: pushfq
|
||||
; CHECK-NEXT: testq %rcx, %rcx
|
||||
; CHECK-NEXT: je [[B:.*]]
|
||||
|
||||
; CHECK: leaq -128(%rsp), %rsp
|
||||
; CHECK-NEXT: pushq %rax
|
||||
; CHECK-NEXT: pushq %rdx
|
||||
; CHECK-NEXT: pushq %rbx
|
||||
; CHECK-NEXT: pushfq
|
||||
|
||||
; CHECK: leaq (%rsi), %rdx
|
||||
; CHECK: movq %rdx, %rdi
|
||||
; CHECK-NEXT: callq __asan_report_load1@PLT
|
||||
|
||||
; CHECK: leaq -1(%rsi,%rcx), %rdx
|
||||
; CHECK: movq %rdx, %rdi
|
||||
; CHECK-NEXT: callq __asan_report_load1@PLT
|
||||
|
||||
; CHECK: leaq (%rdi), %rdx
|
||||
; CHECK: movq %rdx, %rdi
|
||||
; CHECK-NEXT: callq __asan_report_store1@PLT
|
||||
|
||||
; CHECK: leaq -1(%rdi,%rcx), %rdx
|
||||
; CHECK: movq %rdx, %rdi
|
||||
; CHECK-NEXT: callq __asan_report_store1@PLT
|
||||
|
||||
; CHECK: popfq
|
||||
; CHECK-NEXT: popq %rbx
|
||||
; CHECK-NEXT: popq %rdx
|
||||
; CHECK-NEXT: popq %rax
|
||||
; CHECK-NEXT: leaq 128(%rsp), %rsp
|
||||
|
||||
; CHECK: [[B]]:
|
||||
; CHECK-NEXT: popfq
|
||||
|
||||
; CHECK: rep movsb (%rsi), %es:(%rdi)
|
||||
|
||||
; Function Attrs: nounwind sanitize_address uwtable
|
||||
define void @rep_movs_1b(i8* %dst, i8* %src, i64 %n) #0 {
|
||||
entry:
|
||||
tail call void asm sideeffect "rep movsb \0A\09", "{si},{di},{cx},~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %src, i8* %dst, i64 %n) #1
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: rep_movs_8b
|
||||
; CHECK: pushfq
|
||||
; CHECK-NEXT: testq %rcx, %rcx
|
||||
; CHECK-NEXT: je [[Q:.*]]
|
||||
|
||||
; CHECK: leaq (%rsi), %rdx
|
||||
; CHECK: movq %rdx, %rdi
|
||||
; CHECK-NEXT: callq __asan_report_load8@PLT
|
||||
|
||||
; CHECK: leaq -1(%rsi,%rcx,8), %rdx
|
||||
; CHECK: movq %rdx, %rdi
|
||||
; CHECK-NEXT: callq __asan_report_load8@PLT
|
||||
|
||||
; CHECK: leaq (%rdi), %rdx
|
||||
; CHECK: movq %rdx, %rdi
|
||||
; CHECK-NEXT: callq __asan_report_store8@PLT
|
||||
|
||||
; CHECK: leaq -1(%rdi,%rcx,8), %rdx
|
||||
; CHECK: movq %rdx, %rdi
|
||||
; CHECK-NEXT: callq __asan_report_store8@PLT
|
||||
|
||||
; CHECK: [[Q]]:
|
||||
; CHECK-NEXT: popfq
|
||||
|
||||
; CHECK: rep movsq (%rsi), %es:(%rdi)
|
||||
|
||||
; Function Attrs: nounwind sanitize_address uwtable
|
||||
define void @rep_movs_8b(i64* %dst, i64* %src, i64 %n) #0 {
|
||||
entry:
|
||||
tail call void asm sideeffect "rep movsq \0A\09", "{si},{di},{cx},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %src, i64* %dst, i64 %n) #1
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind sanitize_address uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind }
|
||||
@ -1,45 +0,0 @@
|
||||
# The test verifies that memory references through %rsp are correctly
|
||||
# adjusted after instrumentation.
|
||||
|
||||
# RUN: llvm-mc %s -triple=x86_64-unknown-linux-gnu -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
|
||||
|
||||
# CHECK-LABEL: rsp_access
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: pushq %rax
|
||||
# CHECK: pushq %rdi
|
||||
# CHECK: pushfq
|
||||
# CHECK: leaq 160(%rsp), %rdi
|
||||
# CHECK: callq __asan_report_load8@PLT
|
||||
# CHECK: popfq
|
||||
# CHECK: popq %rdi
|
||||
# CHECK: popq %rax
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
# CHECK: movq 8(%rsp), %rax
|
||||
# CHECK: retq
|
||||
|
||||
.text
|
||||
.globl rsp_access
|
||||
.type rsp_access,@function
|
||||
rsp_access:
|
||||
movq 8(%rsp), %rax
|
||||
retq
|
||||
|
||||
# CHECK-LABEL: rsp_32bit_access
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: pushq %rax
|
||||
# CHECK: pushq %rdi
|
||||
# CHECK: pushfq
|
||||
# CHECK: leaq 2147483647(%rsp), %rdi
|
||||
# CHECK: leaq 145(%rdi), %rdi
|
||||
# CHECK: callq __asan_report_load8@PLT
|
||||
# CHECK: popfq
|
||||
# CHECK: popq %rdi
|
||||
# CHECK: popq %rax
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
# CHECK: movq 2147483640(%rsp), %rax
|
||||
# CHECK: retq
|
||||
.globl rsp_32bit_access
|
||||
.type rsp_32bit_access,@function
|
||||
rsp_32bit_access:
|
||||
movq 2147483640(%rsp), %rax
|
||||
retq
|
||||
@ -1,59 +0,0 @@
|
||||
# RUN: llvm-mc %s -x86-asm-syntax=intel -triple=x86_64-unknown-linux-gnu -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
|
||||
|
||||
.text
|
||||
.globl swap
|
||||
.align 16, 0x90
|
||||
.type swap,@function
|
||||
# CHECK-LABEL: swap:
|
||||
#
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: callq __asan_report_load8@PLT
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
#
|
||||
# CHECK: movq (%rcx), %rax
|
||||
#
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: callq __asan_report_load8@PLT
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
#
|
||||
# CHECK: movq (%rdx), %rbx
|
||||
#
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: callq __asan_report_store8@PLT
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
#
|
||||
# CHECK: movq %rbx, (%rcx)
|
||||
#
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: callq __asan_report_store8@PLT
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
#
|
||||
# CHECK: movq %rax, (%rdx)
|
||||
swap: # @swap
|
||||
.cfi_startproc
|
||||
# %bb.0:
|
||||
push rbx
|
||||
.Ltmp0:
|
||||
.cfi_def_cfa_offset 16
|
||||
.Ltmp1:
|
||||
.cfi_offset rbx, -16
|
||||
mov rcx, rdi
|
||||
mov rdx, rsi
|
||||
#APP
|
||||
|
||||
|
||||
mov rax, qword ptr [rcx]
|
||||
mov rbx, qword ptr [rdx]
|
||||
mov qword ptr [rcx], rbx
|
||||
mov qword ptr [rdx], rax
|
||||
|
||||
#NO_APP
|
||||
pop rbx
|
||||
ret
|
||||
.Ltmp2:
|
||||
.size swap, .Ltmp2-swap
|
||||
.cfi_endproc
|
||||
|
||||
|
||||
.ident "clang version 3.5.0 "
|
||||
.section ".note.GNU-stack","",@progbits
|
||||
File diff suppressed because one or more lines are too long
@ -1,3 +0,0 @@
|
||||
if not 'X86' in config.root.targets:
|
||||
config.unsupported = True
|
||||
|
||||
@ -1,58 +0,0 @@
|
||||
; RUN: opt < %s -asan -asan-module -S | FileCheck %s
|
||||
; RUN: opt < %s -asan -asan-module -asan-mapping-scale=5 -S | FileCheck %s
|
||||
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
|
||||
target triple = "x86_64-unknown-linux-gnu"
|
||||
|
||||
; Here we check that the global redzone sizes grow with the object size.
|
||||
|
||||
@G10 = global [10 x i8] zeroinitializer, align 1
|
||||
; CHECK: @G10 = global { [10 x i8], [54 x i8] }
|
||||
|
||||
@G31 = global [31 x i8] zeroinitializer, align 1
|
||||
@G32 = global [32 x i8] zeroinitializer, align 1
|
||||
@G33 = global [33 x i8] zeroinitializer, align 1
|
||||
; CHECK: @G31 = global { [31 x i8], [33 x i8] }
|
||||
; CHECK: @G32 = global { [32 x i8], [32 x i8] }
|
||||
; CHECK: @G33 = global { [33 x i8], [63 x i8] }
|
||||
|
||||
@G63 = global [63 x i8] zeroinitializer, align 1
|
||||
@G64 = global [64 x i8] zeroinitializer, align 1
|
||||
@G65 = global [65 x i8] zeroinitializer, align 1
|
||||
; CHECK: @G63 = global { [63 x i8], [33 x i8] }
|
||||
; CHECK: @G64 = global { [64 x i8], [32 x i8] }
|
||||
; CHECK: @G65 = global { [65 x i8], [63 x i8] }
|
||||
|
||||
@G127 = global [127 x i8] zeroinitializer, align 1
|
||||
@G128 = global [128 x i8] zeroinitializer, align 1
|
||||
@G129 = global [129 x i8] zeroinitializer, align 1
|
||||
; CHECK: @G127 = global { [127 x i8], [33 x i8] }
|
||||
; CHECK: @G128 = global { [128 x i8], [32 x i8] }
|
||||
; CHECK: @G129 = global { [129 x i8], [63 x i8] }
|
||||
|
||||
@G255 = global [255 x i8] zeroinitializer, align 1
|
||||
@G256 = global [256 x i8] zeroinitializer, align 1
|
||||
@G257 = global [257 x i8] zeroinitializer, align 1
|
||||
; CHECK: @G255 = global { [255 x i8], [33 x i8] }
|
||||
; CHECK: @G256 = global { [256 x i8], [64 x i8] }
|
||||
; CHECK: @G257 = global { [257 x i8], [95 x i8] }
|
||||
|
||||
@G511 = global [511 x i8] zeroinitializer, align 1
|
||||
@G512 = global [512 x i8] zeroinitializer, align 1
|
||||
@G513 = global [513 x i8] zeroinitializer, align 1
|
||||
; CHECK: @G511 = global { [511 x i8], [97 x i8] }
|
||||
; CHECK: @G512 = global { [512 x i8], [128 x i8] }
|
||||
; CHECK: @G513 = global { [513 x i8], [159 x i8] }
|
||||
|
||||
@G1023 = global [1023 x i8] zeroinitializer, align 1
|
||||
@G1024 = global [1024 x i8] zeroinitializer, align 1
|
||||
@G1025 = global [1025 x i8] zeroinitializer, align 1
|
||||
; CHECK: @G1023 = global { [1023 x i8], [225 x i8] }
|
||||
; CHECK: @G1024 = global { [1024 x i8], [256 x i8] }
|
||||
; CHECK: @G1025 = global { [1025 x i8], [287 x i8] }
|
||||
|
||||
@G1000000 = global [1000000 x i8] zeroinitializer, align 1
|
||||
@G10000000 = global [10000000 x i8] zeroinitializer, align 1
|
||||
@G100000000 = global [100000000 x i8] zeroinitializer, align 1
|
||||
; CHECK: @G1000000 = global { [1000000 x i8], [249984 x i8] }
|
||||
; CHECK: @G10000000 = global { [10000000 x i8], [262144 x i8] }
|
||||
; CHECK: @G100000000 = global { [100000000 x i8], [262144 x i8] }
|
||||
@ -1,274 +0,0 @@
|
||||
; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -S \
|
||||
; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=STORE -check-prefix=ALL
|
||||
; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -asan-instrument-reads=0 -S \
|
||||
; RUN: | FileCheck %s -check-prefix=NOLOAD -check-prefix=STORE -check-prefix=ALL
|
||||
; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -asan-instrument-writes=0 -S \
|
||||
; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=NOSTORE -check-prefix=ALL
|
||||
; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -asan-instrument-reads=0 -asan-instrument-writes=0 -S \
|
||||
; RUN: | FileCheck %s -check-prefix=NOLOAD -check-prefix=NOSTORE -check-prefix=ALL
|
||||
; Support ASan instrumentation for constant-mask llvm.masked.{load,store}
|
||||
|
||||
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
||||
|
||||
@v4f32 = global <4 x float>* zeroinitializer, align 8
|
||||
@v8i32 = global <8 x i32>* zeroinitializer, align 8
|
||||
@v4i64 = global <4 x i32*>* zeroinitializer, align 8
|
||||
|
||||
;;;;;;;;;;;;;;;; STORE
|
||||
declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>) argmemonly nounwind
|
||||
declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) argmemonly nounwind
|
||||
declare void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*>, <4 x i32*>*, i32, <4 x i1>) argmemonly nounwind
|
||||
|
||||
define void @store.v4f32.1110(<4 x float> %arg) sanitize_address {
|
||||
; ALL-LABEL: @store.v4f32.1110
|
||||
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
|
||||
; NOSTORE-NOT: call void @__asan_store
|
||||
; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
|
||||
; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP0]])
|
||||
; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
|
||||
; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP1]])
|
||||
; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
|
||||
; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP2]])
|
||||
; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 false>)
|
||||
tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 false>)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store.v8i32.10010110(<8 x i32> %arg) sanitize_address {
|
||||
; ALL-LABEL: @store.v8i32.10010110
|
||||
%p = load <8 x i32>*, <8 x i32>** @v8i32, align 8
|
||||
; NOSTORE-NOT: call void @__asan_store
|
||||
; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
|
||||
; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP0]])
|
||||
; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 3
|
||||
; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP3]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP3]])
|
||||
; STORE: [[GEP5:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 5
|
||||
; STORE: [[PGEP5:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP5]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP5]])
|
||||
; STORE: [[GEP6:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 6
|
||||
; STORE: [[PGEP6:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP6]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP6]])
|
||||
; STORE: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 false>)
|
||||
tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 false>)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store.v4i64.0001(<4 x i32*> %arg) sanitize_address {
|
||||
; ALL-LABEL: @store.v4i64.0001
|
||||
%p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
|
||||
; NOSTORE-NOT: call void @__asan_store
|
||||
; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3
|
||||
; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64
|
||||
; STORE: call void @__asan_store8(i64 [[PGEP3]])
|
||||
; STORE: tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>)
|
||||
tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address {
|
||||
; ALL-LABEL: @store.v4f32.variable
|
||||
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
|
||||
; STORE: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
|
||||
; STORE: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
|
||||
; STORE: <label>:[[THEN0]]:
|
||||
; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
|
||||
; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP0]])
|
||||
; STORE: br label %[[AFTER0]]
|
||||
; STORE: <label>:[[AFTER0]]
|
||||
|
||||
; STORE: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
|
||||
; STORE: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
|
||||
; STORE: <label>:[[THEN1]]:
|
||||
; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
|
||||
; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP1]])
|
||||
; STORE: br label %[[AFTER1]]
|
||||
; STORE: <label>:[[AFTER1]]
|
||||
|
||||
; STORE: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2
|
||||
; STORE: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]]
|
||||
; STORE: <label>:[[THEN2]]:
|
||||
; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
|
||||
; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP2]])
|
||||
; STORE: br label %[[AFTER2]]
|
||||
; STORE: <label>:[[AFTER2]]
|
||||
|
||||
; STORE: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3
|
||||
; STORE: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]]
|
||||
; STORE: <label>:[[THEN3]]:
|
||||
; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
|
||||
; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP3]])
|
||||
; STORE: br label %[[AFTER3]]
|
||||
; STORE: <label>:[[AFTER3]]
|
||||
|
||||
; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask)
|
||||
tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask)
|
||||
ret void
|
||||
}
|
||||
|
||||
;; Store using two masked.stores, which should instrument them both.
|
||||
define void @store.v4f32.1010.split(<4 x float> %arg) sanitize_address {
|
||||
; BOTH-LABEL: @store.v4f32.1010.split
|
||||
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
|
||||
; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
|
||||
; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP0]])
|
||||
; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)
|
||||
tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)
|
||||
; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
|
||||
; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
|
||||
; STORE: call void @__asan_store4(i64 [[PGEP1]])
|
||||
; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>)
|
||||
tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>)
|
||||
ret void
|
||||
}
|
||||
|
||||
;; Store using a masked.store after a full store. Shouldn't instrument the second one.
|
||||
define void @store.v4f32.0010.after.full.store(<4 x float> %arg) sanitize_address {
|
||||
; BOTH-LABEL: @store.v4f32.0010.after.full.store
|
||||
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
|
||||
; STORE: [[PTRTOINT:%[0-9A-Za-z]+]] = ptrtoint <4 x float>* %p to i64
|
||||
; STORE: call void @__asan_store16(i64 [[PTRTOINT]])
|
||||
; STORE: store <4 x float> %arg, <4 x float>* %p
|
||||
store <4 x float> %arg, <4 x float>* %p
|
||||
; STORE-NOT: call void @__asan_store
|
||||
; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>)
|
||||
tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>)
|
||||
ret void
|
||||
}
|
||||
|
||||
;;;;;;;;;;;;;;;; LOAD
|
||||
declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>) argmemonly nounwind
|
||||
declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) argmemonly nounwind
|
||||
declare <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>*, i32, <4 x i1>, <4 x i32*>) argmemonly nounwind
|
||||
|
||||
define <8 x i32> @load.v8i32.11100001(<8 x i32> %arg) sanitize_address {
|
||||
; ALL-LABEL: @load.v8i32.11100001
|
||||
%p = load <8 x i32>*, <8 x i32>** @v8i32, align 8
|
||||
; NOLOAD-NOT: call void @__asan_load
|
||||
; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
|
||||
; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP0]])
|
||||
; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1
|
||||
; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP1]])
|
||||
; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 2
|
||||
; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP2]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP2]])
|
||||
; LOAD: [[GEP7:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 7
|
||||
; LOAD: [[PGEP7:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP7]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP7]])
|
||||
; LOAD: tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> %arg)
|
||||
%res = tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> %arg)
|
||||
ret <8 x i32> %res
|
||||
}
|
||||
|
||||
define <4 x float> @load.v4f32.1001(<4 x float> %arg) sanitize_address {
|
||||
; ALL-LABEL: @load.v4f32.1001
|
||||
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
|
||||
; NOLOAD-NOT: call void @__asan_load
|
||||
; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
|
||||
; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP0]])
|
||||
; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
|
||||
; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP3]])
|
||||
; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x float> %arg)
|
||||
%res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x float> %arg)
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define <4 x i32*> @load.v4i64.0001(<4 x i32*> %arg) sanitize_address {
|
||||
; ALL-LABEL: @load.v4i64.0001
|
||||
%p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
|
||||
; NOLOAD-NOT: call void @__asan_load
|
||||
; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3
|
||||
; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64
|
||||
; LOAD: call void @__asan_load8(i64 [[PGEP3]])
|
||||
; LOAD: tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32*> %arg)
|
||||
%res = tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32*> %arg)
|
||||
ret <4 x i32*> %res
|
||||
}
|
||||
|
||||
define <4 x float> @load.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address {
|
||||
; ALL-LABEL: @load.v4f32.variable
|
||||
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
|
||||
; LOAD: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
|
||||
; LOAD: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
|
||||
; LOAD: <label>:[[THEN0]]:
|
||||
; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
|
||||
; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP0]])
|
||||
; LOAD: br label %[[AFTER0]]
|
||||
; LOAD: <label>:[[AFTER0]]
|
||||
|
||||
; LOAD: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
|
||||
; LOAD: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
|
||||
; LOAD: <label>:[[THEN1]]:
|
||||
; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
|
||||
; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP1]])
|
||||
; LOAD: br label %[[AFTER1]]
|
||||
; LOAD: <label>:[[AFTER1]]
|
||||
|
||||
; LOAD: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2
|
||||
; LOAD: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]]
|
||||
; LOAD: <label>:[[THEN2]]:
|
||||
; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
|
||||
; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP2]])
|
||||
; LOAD: br label %[[AFTER2]]
|
||||
; LOAD: <label>:[[AFTER2]]
|
||||
|
||||
; LOAD: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3
|
||||
; LOAD: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]]
|
||||
; LOAD: <label>:[[THEN3]]:
|
||||
; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
|
||||
; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP3]])
|
||||
; LOAD: br label %[[AFTER3]]
|
||||
; LOAD: <label>:[[AFTER3]]
|
||||
|
||||
; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg)
|
||||
%res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg)
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
;; Load using two masked.loads, which should instrument them both.
|
||||
define <4 x float> @load.v4f32.1001.split(<4 x float> %arg) sanitize_address {
|
||||
; BOTH-LABEL: @load.v4f32.1001
|
||||
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
|
||||
; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
|
||||
; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP0]])
|
||||
; LOAD: %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %arg)
|
||||
%res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %arg)
|
||||
; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
|
||||
; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
|
||||
; LOAD: call void @__asan_load4(i64 [[PGEP3]])
|
||||
; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %res)
|
||||
%res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %res)
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
;; Load using a masked.load after a full load. Shouldn't instrument the second one.
|
||||
define <4 x float> @load.v4f32.1001.after.full.load(<4 x float> %arg) sanitize_address {
|
||||
; BOTH-LABEL: @load.v4f32.1001.after.full.load
|
||||
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
|
||||
; LOAD: [[PTRTOINT:%[0-9A-Za-z]+]] = ptrtoint <4 x float>* %p to i64
|
||||
; LOAD: call void @__asan_load16(i64 [[PTRTOINT]])
|
||||
; LOAD: %res = load <4 x float>, <4 x float>* %p
|
||||
%res = load <4 x float>, <4 x float>* %p
|
||||
; LOAD-NOT: call void @__asan_load
|
||||
; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %arg)
|
||||
%res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %arg)
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
@ -1,57 +0,0 @@
|
||||
; RUN: opt < %s -basicaa -gvn -asan -asan-module -S | FileCheck %s
|
||||
; ASAN conflicts with load widening iff the widened load accesses data out of bounds
|
||||
; (while the original unwidened loads do not).
|
||||
; https://github.com/google/sanitizers/issues/20#issuecomment-136381262
|
||||
|
||||
|
||||
; 32-bit little endian target.
|
||||
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
|
||||
|
||||
%struct_of_7_bytes_4_aligned = type { i32, i8, i8, i8}
|
||||
|
||||
@f = external global %struct_of_7_bytes_4_aligned , align 4
|
||||
|
||||
; Accessing bytes 4 and 6, not ok to widen to i32 if sanitize_address is set.
|
||||
|
||||
define i32 @test_widening_bad(i8* %P) nounwind ssp noredzone sanitize_address {
|
||||
entry:
|
||||
%tmp = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 1), align 4
|
||||
%conv = zext i8 %tmp to i32
|
||||
%tmp1 = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 3), align 1
|
||||
%conv2 = zext i8 %tmp1 to i32
|
||||
%add = add nsw i32 %conv, %conv2
|
||||
ret i32 %add
|
||||
; CHECK: @test_widening_bad
|
||||
; CHECK: __asan_report_load1
|
||||
; CHECK: __asan_report_load1
|
||||
; CHECK-NOT: __asan_report
|
||||
; We can not use check for "ret" here because __asan_report_load1 calls live after ret.
|
||||
; CHECK: end_test_widening_bad
|
||||
}
|
||||
|
||||
define void @end_test_widening_bad() {
|
||||
entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
;; Accessing bytes 4 and 5. No widen to i16.
|
||||
|
||||
define i32 @test_widening_ok(i8* %P) nounwind ssp noredzone sanitize_address {
|
||||
entry:
|
||||
%tmp = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 1), align 4
|
||||
%conv = zext i8 %tmp to i32
|
||||
%tmp1 = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 2), align 1
|
||||
%conv2 = zext i8 %tmp1 to i32
|
||||
%add = add nsw i32 %conv, %conv2
|
||||
ret i32 %add
|
||||
; CHECK: @test_widening_ok
|
||||
; CHECK: __asan_report_load1
|
||||
; CHECK: __asan_report_load1
|
||||
; CHECK-NOT: __asan_report
|
||||
; CHECK: end_test_widening_ok
|
||||
}
|
||||
|
||||
define void @end_test_widening_ok() {
|
||||
entry:
|
||||
ret void
|
||||
}
|
||||
@ -1,32 +0,0 @@
|
||||
; RUN: opt < %s -asan -S | FileCheck %s
|
||||
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
|
||||
target triple = "x86_64-apple-macosx10.11.0"
|
||||
|
||||
; Checks that we do not instrument loads and stores comming from custom address space.
|
||||
; These result in invalid (false positive) reports.
|
||||
; int foo(int argc, const char * argv[]) {
|
||||
; void *__attribute__((address_space(256))) *gs_base = (((void * __attribute__((address_space(256))) *)0));
|
||||
; void *somevalue = gs_base[-1];
|
||||
; return somevalue;
|
||||
; }
|
||||
|
||||
define i32 @foo(i32 %argc, i8** %argv) sanitize_address {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%argc.addr = alloca i32, align 4
|
||||
%argv.addr = alloca i8**, align 8
|
||||
%gs_base = alloca i8* addrspace(256)*, align 8
|
||||
%somevalue = alloca i8*, align 8
|
||||
store i32 0, i32* %retval, align 4
|
||||
store i32 %argc, i32* %argc.addr, align 4
|
||||
store i8** %argv, i8*** %argv.addr, align 8
|
||||
store i8* addrspace(256)* null, i8* addrspace(256)** %gs_base, align 8
|
||||
%0 = load i8* addrspace(256)*, i8* addrspace(256)** %gs_base, align 8
|
||||
%arrayidx = getelementptr inbounds i8*, i8* addrspace(256)* %0, i64 -1
|
||||
%1 = load i8*, i8* addrspace(256)* %arrayidx, align 8
|
||||
store i8* %1, i8** %somevalue, align 8
|
||||
%2 = load i8*, i8** %somevalue, align 8
|
||||
%3 = ptrtoint i8* %2 to i32
|
||||
ret i32 %3
|
||||
}
|
||||
; CHECK-NOT: call void @__asan_report_load8
|
||||
@ -1,35 +0,0 @@
|
||||
; Test basic address sanitizer instrumentation.
|
||||
;
|
||||
; RUN: opt -asan -asan-module -S < %s | FileCheck %s
|
||||
|
||||
target triple = "x86_64-pc-windows-msvc"
|
||||
; CHECK: @llvm.global_ctors = {{.*}}@asan.module_ctor
|
||||
|
||||
define i32 @test_load(i32* %a) sanitize_address {
|
||||
; First instrumentation in the function must be to load the dynamic shadow
|
||||
; address into a local variable.
|
||||
; CHECK-LABEL: @test_load
|
||||
; CHECK: entry:
|
||||
; CHECK-NEXT: %[[SHADOW:[^ ]*]] = load i64, i64* @__asan_shadow_memory_dynamic_address
|
||||
|
||||
; Shadow address is loaded and added into the whole offset computation.
|
||||
; CHECK add i64 %{{.*}}, %[[SHADOW] ]
|
||||
|
||||
entry:
|
||||
%tmp1 = load i32, i32* %a, align 4
|
||||
ret i32 %tmp1
|
||||
}
|
||||
|
||||
define i32 @__asan_options(i32* %a) sanitize_address {
|
||||
; Asan functions are not instrumented. Asan function may be called by
|
||||
; __asan_init before the shadow initialisation, which may lead to incorrect
|
||||
; behavior of the instrumented code.
|
||||
; CHECK-LABEL: @__asan_options
|
||||
; CHECK: entry:
|
||||
; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4
|
||||
; CHECK-NEXT: ret i32 %tmp1
|
||||
|
||||
entry:
|
||||
%tmp1 = load i32, i32* %a, align 4
|
||||
ret i32 %tmp1
|
||||
}
|
||||
@ -1,229 +0,0 @@
|
||||
; Test basic address sanitizer instrumentation.
|
||||
;
|
||||
; RUN: opt < %s -asan -asan-module -S | FileCheck --check-prefixes=CHECK,CHECK-S3 %s
|
||||
; RUN: opt < %s -asan -asan-module -asan-mapping-scale=5 -S | FileCheck --check-prefixes=CHECK,CHECK-S5 %s
|
||||
|
||||
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
|
||||
target triple = "x86_64-unknown-linux-gnu"
|
||||
; CHECK: @llvm.global_ctors = {{.*}}@asan.module_ctor
|
||||
|
||||
define i32 @test_load(i32* %a) sanitize_address {
|
||||
; CHECK-LABEL: @test_load
|
||||
; CHECK-NOT: load
|
||||
; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32* %a to i64
|
||||
; CHECK-S3: lshr i64 %[[LOAD_ADDR]], 3
|
||||
; CHECK-S5: lshr i64 %[[LOAD_ADDR]], 5
|
||||
; CHECK: {{or|add}}
|
||||
; CHECK: %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
|
||||
; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]]
|
||||
; CHECK: icmp ne i8
|
||||
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}!prof ![[PROF:[0-9]+]]
|
||||
;
|
||||
; First instrumentation block refines the shadow test.
|
||||
; CHECK-S3: and i64 %[[LOAD_ADDR]], 7
|
||||
; CHECK-S5: and i64 %[[LOAD_ADDR]], 31
|
||||
; CHECK: add i64 %{{.*}}, 3
|
||||
; CHECK: trunc i64 %{{.*}} to i8
|
||||
; CHECK: icmp sge i8 %{{.*}}, %[[LOAD_SHADOW]]
|
||||
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
|
||||
;
|
||||
; The crash block reports the error.
|
||||
; CHECK: call void @__asan_report_load4(i64 %[[LOAD_ADDR]])
|
||||
; CHECK: unreachable
|
||||
;
|
||||
; The actual load.
|
||||
; CHECK: %tmp1 = load i32, i32* %a
|
||||
; CHECK: ret i32 %tmp1
|
||||
|
||||
|
||||
|
||||
entry:
|
||||
%tmp1 = load i32, i32* %a, align 4
|
||||
ret i32 %tmp1
|
||||
}
|
||||
|
||||
define void @test_store(i32* %a) sanitize_address {
|
||||
; CHECK-LABEL: @test_store
|
||||
; CHECK-NOT: store
|
||||
; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %a to i64
|
||||
; CHECK-S3: lshr i64 %[[STORE_ADDR]], 3
|
||||
; CHECK-S5: lshr i64 %[[STORE_ADDR]], 5
|
||||
; CHECK: {{or|add}}
|
||||
; CHECK: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
|
||||
; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
|
||||
; CHECK: icmp ne i8
|
||||
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
|
||||
;
|
||||
; First instrumentation block refines the shadow test.
|
||||
; CHECK-S3: and i64 %[[STORE_ADDR]], 7
|
||||
; CHECK-S5: and i64 %[[STORE_ADDR]], 31
|
||||
; CHECK: add i64 %{{.*}}, 3
|
||||
; CHECK: trunc i64 %{{.*}} to i8
|
||||
; CHECK: icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]
|
||||
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
|
||||
;
|
||||
; The crash block reports the error.
|
||||
; CHECK: call void @__asan_report_store4(i64 %[[STORE_ADDR]])
|
||||
; CHECK: unreachable
|
||||
;
|
||||
; The actual load.
|
||||
; CHECK: store i32 42, i32* %a
|
||||
; CHECK: ret void
|
||||
;
|
||||
|
||||
entry:
|
||||
store i32 42, i32* %a, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that asan leaves just one alloca.
|
||||
|
||||
declare void @alloca_test_use([10 x i8]*)
|
||||
define void @alloca_test() sanitize_address {
|
||||
entry:
|
||||
%x = alloca [10 x i8], align 1
|
||||
%y = alloca [10 x i8], align 1
|
||||
%z = alloca [10 x i8], align 1
|
||||
call void @alloca_test_use([10 x i8]* %x)
|
||||
call void @alloca_test_use([10 x i8]* %y)
|
||||
call void @alloca_test_use([10 x i8]* %z)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: define void @alloca_test()
|
||||
; CHECK: %asan_local_stack_base = alloca
|
||||
; CHECK: = alloca
|
||||
; CHECK-NOT: = alloca
|
||||
; CHECK: ret void
|
||||
|
||||
define void @LongDoubleTest(x86_fp80* nocapture %a) nounwind uwtable sanitize_address {
|
||||
entry:
|
||||
store x86_fp80 0xK3FFF8000000000000000, x86_fp80* %a, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: LongDoubleTest
|
||||
; CHECK: __asan_report_store_n
|
||||
; CHECK: __asan_report_store_n
|
||||
; CHECK: ret void
|
||||
|
||||
|
||||
define void @i40test(i40* %a, i40* %b) nounwind uwtable sanitize_address {
|
||||
entry:
|
||||
%t = load i40, i40* %a
|
||||
store i40 %t, i40* %b, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i40test
|
||||
; CHECK: __asan_report_load_n{{.*}}, i64 5)
|
||||
; CHECK: __asan_report_load_n{{.*}}, i64 5)
|
||||
; CHECK: __asan_report_store_n{{.*}}, i64 5)
|
||||
; CHECK: __asan_report_store_n{{.*}}, i64 5)
|
||||
; CHECK: ret void
|
||||
|
||||
define void @i64test_align1(i64* %b) nounwind uwtable sanitize_address {
|
||||
entry:
|
||||
store i64 0, i64* %b, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i64test_align1
|
||||
; CHECK: __asan_report_store_n{{.*}}, i64 8)
|
||||
; CHECK: __asan_report_store_n{{.*}}, i64 8)
|
||||
; CHECK: ret void
|
||||
|
||||
|
||||
define void @i80test(i80* %a, i80* %b) nounwind uwtable sanitize_address {
|
||||
entry:
|
||||
%t = load i80, i80* %a
|
||||
store i80 %t, i80* %b, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i80test
|
||||
; CHECK: __asan_report_load_n{{.*}}, i64 10)
|
||||
; CHECK: __asan_report_load_n{{.*}}, i64 10)
|
||||
; CHECK: __asan_report_store_n{{.*}}, i64 10)
|
||||
; CHECK: __asan_report_store_n{{.*}}, i64 10)
|
||||
; CHECK: ret void
|
||||
|
||||
; asan should not instrument functions with available_externally linkage.
|
||||
define available_externally i32 @f_available_externally(i32* %a) sanitize_address {
|
||||
entry:
|
||||
%tmp1 = load i32, i32* %a
|
||||
ret i32 %tmp1
|
||||
}
|
||||
; CHECK-LABEL: @f_available_externally
|
||||
; CHECK-NOT: __asan_report
|
||||
; CHECK: ret i32
|
||||
|
||||
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
|
||||
declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) nounwind
|
||||
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) nounwind
|
||||
|
||||
define void @memintr_test(i8* %a, i8* %b) nounwind uwtable sanitize_address {
|
||||
entry:
|
||||
tail call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 100, i32 1, i1 false)
|
||||
tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i32 1, i1 false)
|
||||
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i32 1, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: memintr_test
|
||||
; CHECK: __asan_memset
|
||||
; CHECK: __asan_memmove
|
||||
; CHECK: __asan_memcpy
|
||||
; CHECK: ret void
|
||||
|
||||
declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture writeonly, i8, i64, i32) nounwind
|
||||
declare void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind
|
||||
declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind
|
||||
|
||||
define void @memintr_element_atomic_test(i8* %a, i8* %b) nounwind uwtable sanitize_address {
|
||||
; This is a canary test to make sure that these don't get lowered into calls that don't
|
||||
; have the element-atomic property. Eventually, asan will have to be enhanced to lower
|
||||
; these properly.
|
||||
; CHECK-LABEL: memintr_element_atomic_test
|
||||
; CHECK-NEXT: tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %a, i8 0, i64 100, i32 1)
|
||||
; CHECK-NEXT: tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1)
|
||||
; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1)
|
||||
; CHECK-NEXT: ret void
|
||||
tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %a, i8 0, i64 100, i32 1)
|
||||
tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1)
|
||||
tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; CHECK-LABEL: @test_swifterror
|
||||
; CHECK-NOT: __asan_report_load
|
||||
; CHECK: ret void
|
||||
define void @test_swifterror(i8** swifterror) sanitize_address {
|
||||
%swifterror_ptr_value = load i8*, i8** %0
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test_swifterror_2
|
||||
; CHECK-NOT: __asan_report_store
|
||||
; CHECK: ret void
|
||||
define void @test_swifterror_2(i8** swifterror) sanitize_address {
|
||||
store i8* null, i8** %0
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test_swifterror_3
|
||||
; CHECK-NOT: __asan_report_store
|
||||
; CHECK: ret void
|
||||
define void @test_swifterror_3() sanitize_address {
|
||||
%swifterror_addr = alloca swifterror i8*
|
||||
store i8* null, i8** %swifterror_addr
|
||||
call void @test_swifterror_2(i8** swifterror %swifterror_addr)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: define internal void @asan.module_ctor()
|
||||
; CHECK: call void @__asan_init()
|
||||
|
||||
; PROF
|
||||
; CHECK: ![[PROF]] = !{!"branch_weights", i32 1, i32 100000}
|
||||
@ -1,31 +0,0 @@
|
||||
; RUN: opt < %s -asan -asan-module -S | FileCheck %s
|
||||
source_filename = "version.c"
|
||||
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
|
||||
target triple = "x86_64-apple-macosx10.12.0"
|
||||
; CHECK: @version = constant { [5 x i8], [59 x i8] } {{.*}}, !dbg ![[GV:.*]]
|
||||
|
||||
@version = constant [5 x i8] c"4.00\00", align 1, !dbg !0
|
||||
|
||||
!llvm.dbg.cu = !{!2}
|
||||
!llvm.module.flags = !{!11, !12, !13}
|
||||
!llvm.ident = !{!14}
|
||||
; Should not have an expression:
|
||||
; CHECK: ![[GV]] = !DIGlobalVariableExpression(var: ![[GVAR:.*]], expr: !DIExpression())
|
||||
; CHECK: ![[GVAR]] = !DIGlobalVariable(name: "version"
|
||||
|
||||
!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
|
||||
!1 = !DIGlobalVariable(name: "version", scope: !2, file: !3, line: 2, type: !6, isLocal: false, isDefinition: true)
|
||||
!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 4.0.0 (trunk 281923) (llvm/trunk 281916)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5)
|
||||
!3 = !DIFile(filename: "version.c", directory: "/Volumes/Fusion/Data/radar/24899262")
|
||||
!4 = !{}
|
||||
!5 = !{!0}
|
||||
!6 = !DICompositeType(tag: DW_TAG_array_type, baseType: !7, size: 40, align: 8, elements: !9)
|
||||
!7 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !8)
|
||||
!8 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
|
||||
!9 = !{!10}
|
||||
!10 = !DISubrange(count: 5)
|
||||
!11 = !{i32 2, !"Dwarf Version", i32 4}
|
||||
!12 = !{i32 2, !"Debug Info Version", i32 3}
|
||||
!13 = !{i32 1, !"PIC Level", i32 2}
|
||||
!14 = !{!"clang version 4.0.0 (trunk 281923) (llvm/trunk 281916)"}
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user