Imported Upstream version 5.18.0.207

Former-commit-id: 3b152f462918d427ce18620a2cbe4f8b79650449

external/llvm/test/CodeGen/X86/pr35636.ll

@@ -1,35 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 | FileCheck %s
-
-define void @_Z15uint64_to_asciimPc(i64 %arg) {
-; CHECK-LABEL: _Z15uint64_to_asciimPc:
-; CHECK:       # %bb.0: # %bb
-; CHECK-NEXT:    movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD81
-; CHECK-NEXT:    movq %rdi, %rdx
-; CHECK-NEXT:    mulxq %rax, %rax, %rcx
-; CHECK-NEXT:    shrq $42, %rcx
-; CHECK-NEXT:    imulq $281474977, %rcx, %rax # imm = 0x10C6F7A1
-; CHECK-NEXT:    shrq $20, %rax
-; CHECK-NEXT:    leal 5(%rax,%rax,4), %eax
-; CHECK-NEXT:    andl $134217727, %eax # imm = 0x7FFFFFF
-; CHECK-NEXT:    leal (%rax,%rax,4), %eax
-; CHECK-NEXT:    shrl $26, %eax
-; CHECK-NEXT:    orb $48, %al
-; CHECK-NEXT:    movb %al, (%rax)
-; CHECK-NEXT:    retq
-bb:
-  %tmp = udiv i64 %arg, 100000000000000
-  %tmp1 = mul nuw nsw i64 %tmp, 281474977
-  %tmp2 = lshr i64 %tmp1, 20
-  %tmp3 = trunc i64 %tmp2 to i32
-  %tmp4 = add nuw nsw i32 %tmp3, 1
-  %tmp5 = and i32 %tmp4, 268435455
-  %tmp6 = mul nuw nsw i32 %tmp5, 5
-  %tmp7 = and i32 %tmp6, 134217727
-  %tmp8 = mul nuw nsw i32 %tmp7, 5
-  %tmp9 = lshr i32 %tmp8, 26
-  %tmp10 = trunc i32 %tmp9 to i8
-  %tmp11 = or i8 %tmp10, 48
-  store i8 %tmp11, i8* undef, align 1
-  ret void
-}