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Imported Upstream version 5.18.0.207
Former-commit-id: 3b152f462918d427ce18620a2cbe4f8b79650449
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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@vda = common global <2 x double> zeroinitializer, align 16
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@vdb = common global <2 x double> zeroinitializer, align 16
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@vdr = common global <2 x double> zeroinitializer, align 16
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@vfa = common global <4 x float> zeroinitializer, align 16
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@vfb = common global <4 x float> zeroinitializer, align 16
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@vfr = common global <4 x float> zeroinitializer, align 16
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@vbllr = common global <2 x i64> zeroinitializer, align 16
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@vbir = common global <4 x i32> zeroinitializer, align 16
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@vblla = common global <2 x i64> zeroinitializer, align 16
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@vbllb = common global <2 x i64> zeroinitializer, align 16
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@vbia = common global <4 x i32> zeroinitializer, align 16
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@vbib = common global <4 x i32> zeroinitializer, align 16
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; Function Attrs: nounwind
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define void @test1() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %1)
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store <2 x double> %2, <2 x double>* @vdr, align 16
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ret void
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; CHECK-LABEL: @test1
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; CHECK: xvdivdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test2() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @vfr, align 16
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ret void
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; CHECK-LABEL: @test2
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; CHECK: xvdivsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test3() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vda, align 16
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%2 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %1)
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store <2 x double> %2, <2 x double>* @vdr, align 16
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ret void
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; CHECK-LABEL: @test3
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; CHECK: xvrdpip {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test4() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfa, align 16
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%2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %1)
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store <4 x float> %2, <4 x float>* @vfr, align 16
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ret void
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; CHECK-LABEL: @test4
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; CHECK: xvrspip {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test5() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %0, <2 x double> %1)
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store <2 x i64> %2, <2 x i64>* @vbllr, align 16
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ret void
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; CHECK-LABEL: @test5
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; CHECK: xvcmpeqdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test6() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %0, <4 x float> %1)
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store <4 x i32> %2, <4 x i32>* @vbir, align 16
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ret void
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; CHECK-LABEL: @test6
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; CHECK: xvcmpeqsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test7() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %0, <2 x double> %1)
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store <2 x i64> %2, <2 x i64>* @vbllr, align 16
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ret void
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; CHECK-LABEL: @test7
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; CHECK: xvcmpgedp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test8() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %0, <4 x float> %1)
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store <4 x i32> %2, <4 x i32>* @vbir, align 16
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ret void
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; CHECK-LABEL: @test8
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; CHECK: xvcmpgesp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test9() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %0, <2 x double> %1)
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store <2 x i64> %2, <2 x i64>* @vbllr, align 16
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ret void
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; CHECK-LABEL: @test9
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; CHECK: xvcmpgtdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test10() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %0, <4 x float> %1)
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store <4 x i32> %2, <4 x i32>* @vbir, align 16
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ret void
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; CHECK-LABEL: @test10
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; CHECK: xvcmpgtsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define <4 x float> @emit_xvresp(<4 x float> %a) {
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entry:
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%a.addr = alloca <4 x float>, align 16
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store <4 x float> %a, <4 x float>* %a.addr, align 16
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%0 = load <4 x float>, <4 x float>* %a.addr, align 16
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%1 = call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float> %0)
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ret <4 x float> %1
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; CHECK-LABEL: @emit_xvresp
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; CHECK: xvresp {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define <2 x double> @emit_xvredp(<2 x double> %a) {
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entry:
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%a.addr = alloca <2 x double>, align 16
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store <2 x double> %a, <2 x double>* %a.addr, align 16
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%0 = load <2 x double>, <2 x double>* %a.addr, align 16
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%1 = call <2 x double> @llvm.ppc.vsx.xvredp(<2 x double> %0)
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ret <2 x double> %1
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; CHECK-LABEL: @emit_xvredp
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; CHECK: xvredp {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind readnone
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define <4 x i32> @emit_xvcvdpsxws(<2 x double> %a) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double> %a)
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ret <4 x i32> %0
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; CHECK-LABEL: @emit_xvcvdpsxws
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; CHECK: xvcvdpsxws 34, 34
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}
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; Function Attrs: nounwind readnone
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define <4 x i32> @emit_xvcvdpuxws(<2 x double> %a) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> %a)
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ret <4 x i32> %0
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; CHECK-LABEL: @emit_xvcvdpuxws
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; CHECK: xvcvdpuxws 34, 34
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}
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; Function Attrs: nounwind readnone
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define <2 x double> @emit_xvcvsxwdp(<4 x i32> %a) {
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entry:
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%0 = tail call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> %a)
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ret <2 x double> %0
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; CHECK-LABEL: @emit_xvcvsxwdp
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; CHECK: xvcvsxwdp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <2 x double> @emit_xvcvuxwdp(<4 x i32> %a) {
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entry:
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%0 = tail call <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32> %a)
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ret <2 x double> %0
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; CHECK-LABEL: @emit_xvcvuxwdp
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; CHECK: xvcvuxwdp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <2 x double> @emit_xvcvspdp(<4 x float> %a) {
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entry:
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%0 = tail call <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %a)
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ret <2 x double> %0
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; CHECK-LABEL: @emit_xvcvspdp
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; CHECK: xvcvspdp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <4 x float> @emit_xvcvsxdsp(<2 x i64> %a) {
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entry:
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%0 = tail call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> %a)
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ret <4 x float> %0
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; CHECK-LABEL: @emit_xvcvsxdsp
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; CHECK: xvcvsxdsp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <4 x float> @emit_xvcvuxdsp(<2 x i64> %a) {
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entry:
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%0 = tail call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> %a)
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ret <4 x float> %0
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; CHECK-LABEL: @emit_xvcvuxdsp
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; CHECK: xvcvuxdsp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <4 x float> @emit_xvcvdpsp(<2 x double> %a) {
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entry:
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%0 = tail call <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double> %a)
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ret <4 x float> %0
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; CHECK-LABEL: @emit_xvcvdpsp
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; CHECK: xvcvdpsp 34, 34
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}
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; Function Attrs: nounwind readnone
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>)
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; Function Attrs: nounwind readnone
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declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float>, <4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float>, <4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double>) #1
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declare <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>) #1
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declare <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>) #1
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declare <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>) #1
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declare <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>) #1
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declare <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float>) #1
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declare <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64>) #1
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declare <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64>) #1
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