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Imported Upstream version 5.18.0.207
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168
external/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
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168
external/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
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@ -1,168 +0,0 @@
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; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM
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; instruction format).
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; RUN: llc -march=mips -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s
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define i32 @msa_ir_cfcmsa_test() nounwind {
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entry:
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%0 = tail call i32 @llvm.mips.cfcmsa(i32 0)
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ret i32 %0
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}
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; CHECK: msa_ir_cfcmsa_test:
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; CHECK: cfcmsa $[[R1:[0-9]+]], $0
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; CHECK: .size msa_ir_cfcmsa_test
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;
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define i32 @msa_csr_cfcmsa_test() nounwind {
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entry:
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%0 = tail call i32 @llvm.mips.cfcmsa(i32 1)
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ret i32 %0
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}
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; CHECK: msa_csr_cfcmsa_test:
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; CHECK: cfcmsa $[[R1:[0-9]+]], $1
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; CHECK: .size msa_csr_cfcmsa_test
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;
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define i32 @msa_access_cfcmsa_test() nounwind {
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entry:
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%0 = tail call i32 @llvm.mips.cfcmsa(i32 2)
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ret i32 %0
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}
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; CHECK: msa_access_cfcmsa_test:
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; CHECK: cfcmsa $[[R1:[0-9]+]], $2
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; CHECK: .size msa_access_cfcmsa_test
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;
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define i32 @msa_save_cfcmsa_test() nounwind {
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entry:
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%0 = tail call i32 @llvm.mips.cfcmsa(i32 3)
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ret i32 %0
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}
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; CHECK: msa_save_cfcmsa_test:
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; CHECK: cfcmsa $[[R1:[0-9]+]], $3
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; CHECK: .size msa_save_cfcmsa_test
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;
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define i32 @msa_modify_cfcmsa_test() nounwind {
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entry:
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%0 = tail call i32 @llvm.mips.cfcmsa(i32 4)
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ret i32 %0
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}
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; CHECK: msa_modify_cfcmsa_test:
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; CHECK: cfcmsa $[[R1:[0-9]+]], $4
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; CHECK: .size msa_modify_cfcmsa_test
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;
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define i32 @msa_request_cfcmsa_test() nounwind {
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entry:
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%0 = tail call i32 @llvm.mips.cfcmsa(i32 5)
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ret i32 %0
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}
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; CHECK: msa_request_cfcmsa_test:
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; CHECK: cfcmsa $[[R1:[0-9]+]], $5
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; CHECK: .size msa_request_cfcmsa_test
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;
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define i32 @msa_map_cfcmsa_test() nounwind {
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entry:
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%0 = tail call i32 @llvm.mips.cfcmsa(i32 6)
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ret i32 %0
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}
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; CHECK: msa_map_cfcmsa_test:
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; CHECK: cfcmsa $[[R1:[0-9]+]], $6
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; CHECK: .size msa_map_cfcmsa_test
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;
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define i32 @msa_unmap_cfcmsa_test() nounwind {
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entry:
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%0 = tail call i32 @llvm.mips.cfcmsa(i32 7)
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ret i32 %0
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}
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; CHECK: msa_unmap_cfcmsa_test:
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; CHECK: cfcmsa $[[R1:[0-9]+]], $7
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; CHECK: .size msa_unmap_cfcmsa_test
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;
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define void @msa_ir_ctcmsa_test() nounwind {
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entry:
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tail call void @llvm.mips.ctcmsa(i32 0, i32 1)
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ret void
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}
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; CHECK: msa_ir_ctcmsa_test:
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; CHECK: ctcmsa $0
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; CHECK: .size msa_ir_ctcmsa_test
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;
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define void @msa_csr_ctcmsa_test() nounwind {
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entry:
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tail call void @llvm.mips.ctcmsa(i32 1, i32 1)
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ret void
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}
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; CHECK: msa_csr_ctcmsa_test:
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; CHECK: ctcmsa $1
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; CHECK: .size msa_csr_ctcmsa_test
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;
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define void @msa_access_ctcmsa_test() nounwind {
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entry:
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tail call void @llvm.mips.ctcmsa(i32 2, i32 1)
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ret void
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}
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; CHECK: msa_access_ctcmsa_test:
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; CHECK: ctcmsa $2
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; CHECK: .size msa_access_ctcmsa_test
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;
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define void @msa_save_ctcmsa_test() nounwind {
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entry:
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tail call void @llvm.mips.ctcmsa(i32 3, i32 1)
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ret void
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}
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; CHECK: msa_save_ctcmsa_test:
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; CHECK: ctcmsa $3
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; CHECK: .size msa_save_ctcmsa_test
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;
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define void @msa_modify_ctcmsa_test() nounwind {
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entry:
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tail call void @llvm.mips.ctcmsa(i32 4, i32 1)
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ret void
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}
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; CHECK: msa_modify_ctcmsa_test:
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; CHECK: ctcmsa $4
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; CHECK: .size msa_modify_ctcmsa_test
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;
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define void @msa_request_ctcmsa_test() nounwind {
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entry:
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tail call void @llvm.mips.ctcmsa(i32 5, i32 1)
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ret void
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}
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; CHECK: msa_request_ctcmsa_test:
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; CHECK: ctcmsa $5
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; CHECK: .size msa_request_ctcmsa_test
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;
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define void @msa_map_ctcmsa_test() nounwind {
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entry:
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tail call void @llvm.mips.ctcmsa(i32 6, i32 1)
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ret void
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}
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; CHECK: msa_map_ctcmsa_test:
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; CHECK: ctcmsa $6
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; CHECK: .size msa_map_ctcmsa_test
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;
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define void @msa_unmap_ctcmsa_test() nounwind {
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entry:
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tail call void @llvm.mips.ctcmsa(i32 7, i32 1)
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ret void
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}
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; CHECK: msa_unmap_ctcmsa_test:
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; CHECK: ctcmsa $7
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; CHECK: .size msa_unmap_ctcmsa_test
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;
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declare i32 @llvm.mips.cfcmsa(i32) nounwind
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declare void @llvm.mips.ctcmsa(i32, i32) nounwind
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