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Imported Upstream version 5.18.0.207
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34
external/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
vendored
34
external/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
vendored
@ -1,34 +0,0 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@b = global i32 1, align 4
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@i = global i32 0, align 4
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@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
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; Function Attrs: nounwind
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define void @br() #0 {
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entry:
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%0 = load i32, i32* @b, align 4
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%tobool = icmp eq i32 %0, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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store i32 6754, i32* @i, align 4
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br label %if.end
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if.end: ; preds = %entry, %if.then
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ret void
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; FIXME: This instruction is redundant.
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; CHECK: xor $[[REG1:[0-9]+]], ${{[0-9]+}}, $zero
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; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
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; CHECK: bgtz $[[REG2]], $BB[[BL:[0-9]+_[0-9]+]]
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; CHECK: nop
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; CHECK: addiu ${{[0-9]+}}, $zero, 6754
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; CHECK: sw ${{[0-9]+}}, 0(${{[0-9]+}})
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; CHECK: $BB[[BL]]:
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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@ -1,58 +0,0 @@
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
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; RUN: -fast-isel-abort=3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=32R1
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
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; RUN: -fast-isel-abort=3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=32R2
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@a = global i16 -21829, align 2
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@b = global i32 -1430532899, align 4
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@a1 = common global i16 0, align 2
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@b1 = common global i32 0, align 4
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declare i16 @llvm.bswap.i16(i16)
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declare i32 @llvm.bswap.i32(i32)
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define void @b16() {
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; ALL-LABEL: b16:
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; ALL: lw $[[A_ADDR:[0-9]+]], %got(a)($[[GOT_ADDR:[0-9]+]])
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; ALL: lhu $[[A_VAL:[0-9]+]], 0($[[A_ADDR]])
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; 32R1: sll $[[TMP1:[0-9]+]], $[[A_VAL]], 8
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; 32R1: srl $[[TMP2:[0-9]+]], $[[A_VAL]], 8
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; 32R1: or $[[TMP3:[0-9]+]], $[[TMP1]], $[[TMP2]]
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; 32R1: andi $[[TMP4:[0-9]+]], $[[TMP3]], 65535
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; 32R2: wsbh $[[RESULT:[0-9]+]], $[[A_VAL]]
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%1 = load i16, i16* @a, align 2
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%2 = call i16 @llvm.bswap.i16(i16 %1)
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store i16 %2, i16* @a1, align 2
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ret void
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}
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define void @b32() {
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; ALL-LABEL: b32:
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; ALL: lw $[[B_ADDR:[0-9]+]], %got(b)($[[GOT_ADDR:[0-9]+]])
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; ALL: lw $[[B_VAL:[0-9]+]], 0($[[B_ADDR]])
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; 32R1: srl $[[TMP1:[0-9]+]], $[[B_VAL]], 8
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; 32R1: srl $[[TMP2:[0-9]+]], $[[B_VAL]], 24
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; 32R1: andi $[[TMP3:[0-9]+]], $[[TMP1]], 65280
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; 32R1: or $[[TMP4:[0-9]+]], $[[TMP2]], $[[TMP3]]
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; 32R1: andi $[[TMP5:[0-9]+]], $[[B_VAL]], 65280
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; 32R1: sll $[[TMP6:[0-9]+]], $[[TMP5]], 8
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; 32R1: sll $[[TMP7:[0-9]+]], $[[B_VAL]], 24
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; 32R1: or $[[TMP8:[0-9]+]], $[[TMP4]], $[[TMP6]]
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; 32R1: or $[[RESULT:[0-9]+]], $[[TMP7]], $[[TMP8]]
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; 32R2: wsbh $[[TMP:[0-9]+]], $[[B_VAL]]
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; 32R2: rotr $[[RESULT:[0-9]+]], $[[TMP]], 16
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%1 = load i32, i32* @b, align 4
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%2 = call i32 @llvm.bswap.i32(i32 %1)
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store i32 %2, i32* @b1, align 4
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ret void
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}
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538
external/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
vendored
538
external/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
vendored
File diff suppressed because it is too large
Load Diff
@ -1,55 +0,0 @@
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; Targets where we should not enable FastISel.
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; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mattr=mips16 -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+micromips -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic -target-abi n64 \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic -target-abi n64 \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
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; Valid targets for FastISel.
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; RUN: llc -march=mips -mcpu=mips32r0 -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL
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; RUN: llc -march=mips -mcpu=mips32r2 -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL
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; The CHECK prefix is being used by those targets that do not support FastISel.
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; By checking that we don't emit the "FastISel missed terminator..." message,
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; we ensure that we do not generate code through FastISel.
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; CHECK-NOT: FastISel missed terminator: ret i64 0
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; The above CHECK will only be valid as long as we *do* emit the missed
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; terminator message for targets that support FastISel. If we add support
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; for i64 return values in the future, then the following FISEL check-prefix
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; will fail and we will have to come up with a new test.
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; FISEL: FastISel missed terminator: ret i64 0
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define i64 @foo() {
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entry:
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ret i64 0
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}
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@ -1,18 +0,0 @@
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; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \
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; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \
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; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s
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@ARR = external global [10 x i32], align 4
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define void @foo() {
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; CHECK-LABEL: foo
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; CHECK-DAG: lw $[[ARR:[0-9]+]], %got(ARR)({{.*}})
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; CHECK-DAG: addiu $[[T0:[0-9]+]], $zero, 12345
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; CHECK: sw $[[T0]], 8($[[ARR]])
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entry:
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store i32 12345, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ARR, i32 0, i32 2), align 4
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ret void
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}
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@ -1,55 +0,0 @@
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
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; RUN: -fast-isel-abort=3 | FileCheck %s
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
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; RUN: -fast-isel-abort=3 | FileCheck %s
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@sj = global i32 200000, align 4
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@sk = global i32 -47, align 4
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@uj = global i32 200000, align 4
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@uk = global i32 43, align 4
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@si = common global i32 0, align 4
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@ui = common global i32 0, align 4
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define void @divs() {
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; CHECK-LABEL: divs:
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; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
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; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])
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; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])
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; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])
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; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
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; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
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; CHECK-DAG: div $zero, $[[J]], $[[K]]
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; CHECK-DAG: teq $[[K]], $zero, 7
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; CHECK-DAG: mflo $[[RESULT:[0-9]+]]
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; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
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%1 = load i32, i32* @sj, align 4
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%2 = load i32, i32* @sk, align 4
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%div = sdiv i32 %1, %2
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store i32 %div, i32* @si, align 4
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ret void
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}
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define void @divu() {
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; CHECK-LABEL: divu:
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; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
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; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])
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; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])
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; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])
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; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
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; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
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; CHECK-DAG: divu $zero, $[[J]], $[[K]]
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; CHECK-DAG: teq $[[K]], $zero, 7
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; CHECK-DAG: mflo $[[RESULT:[0-9]+]]
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; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
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%1 = load i32, i32* @uj, align 4
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%2 = load i32, i32* @uk, align 4
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%div = udiv i32 %1, %2
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store i32 %div, i32* @ui, align 4
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ret void
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}
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@ -1,14 +0,0 @@
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; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \
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; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s
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; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently
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; supports AFGR64 only, which uses paired 32 bit registers.
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define zeroext i1 @f(double %value) {
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entry:
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; CHECK-LABEL: f:
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; CHECK: sdc1
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%value.addr = alloca double, align 8
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store double %value, double* %value.addr, align 8
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ret i1 false
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}
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@ -1,11 +0,0 @@
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; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \
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; RUN: -O0 -fast-isel-abort=3 -relocation-model=pic < %s
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; Test that FastISel aborts instead of trying to lower arguments for soft-float.
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define void @__signbit(double %__x) {
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entry:
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%__x.addr = alloca double, align 8
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store double %__x, double* %__x.addr, align 8
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ret void
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}
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@ -1,32 +0,0 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
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; RUN: < %s -verify-machineinstrs | FileCheck %s
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%struct.x = type { i32 }
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@i = common global i32 0, align 4
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define i32 @foobar(i32 signext %x) {
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entry:
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; CHECK-LABEL: foobar:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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%a = alloca %struct.x, align 4
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%c = alloca %struct.x*, align 4
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store i32 %x, i32* %x.addr, align 4
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%x1 = getelementptr inbounds %struct.x, %struct.x* %a, i32 0, i32 0
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%0 = load i32, i32* %x.addr, align 4
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store i32 %0, i32* %x1, align 4
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store %struct.x* %a, %struct.x** %c, align 4
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%1 = load %struct.x*, %struct.x** %c, align 4
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%x2 = getelementptr inbounds %struct.x, %struct.x* %1, i32 0, i32 0
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%2 = load i32, i32* %x2, align 4
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store i32 %2, i32* @i, align 4
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%3 = load i32, i32* %retval
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
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; CHECK-DAG: addiu $[[A_ADDR:[0-9]+]], $sp, 8
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; CHECK-DAG: sw $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp)
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; CHECK-DAG: lw $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp)
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; CHECK-DAG: lw $[[A_X:[0-9]+]], 0($[[A_ADDR2]])
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; CHECK-DAG: sw $[[A_X]], 0($[[I_ADDR]])
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ret i32 %3
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}
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@ -1,15 +0,0 @@
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
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; RUN: -pass-remarks-missed=isel 2>&1 | FileCheck %s
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; CHECK: FastISel missed call:
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; CHECK-SAME: %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b)
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define internal i32 @bar(i32 signext %a, i32 signext %b) {
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%s = and i32 %a, %b
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ret i32 %s
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}
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define i32 @foo(i32 signext %a, i32 signext %b) {
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%call = call fastcc i32 @foo(i32 signext %a, i32 signext %b)
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ret i32 %call
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}
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254
external/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
vendored
254
external/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
vendored
@ -1,254 +0,0 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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@f1 = common global float 0.000000e+00, align 4
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@f2 = common global float 0.000000e+00, align 4
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@b1 = common global i32 0, align 4
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@d1 = common global double 0.000000e+00, align 8
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@d2 = common global double 0.000000e+00, align 8
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; Function Attrs: nounwind
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define void @feq1() {
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entry:
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%0 = load float, float* @f1, align 4
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%1 = load float, float* @f2, align 4
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%cmp = fcmp oeq float %0, %1
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; CHECK-LABEL: feq1:
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; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
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; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
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; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]
|
||||
; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @fne1() {
|
||||
entry:
|
||||
%0 = load float, float* @f1, align 4
|
||||
%1 = load float, float* @f2, align 4
|
||||
%cmp = fcmp une float %0, %1
|
||||
; CHECK-LABEL: fne1:
|
||||
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
|
||||
; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
|
||||
; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]
|
||||
; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @flt1() {
|
||||
entry:
|
||||
%0 = load float, float* @f1, align 4
|
||||
%1 = load float, float* @f2, align 4
|
||||
%cmp = fcmp olt float %0, %1
|
||||
; CHECK-LABEL: flt1:
|
||||
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
|
||||
; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
|
||||
; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.olt.s $f[[REG_F1]], $f[[REG_F2]]
|
||||
; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @fgt1() {
|
||||
entry:
|
||||
%0 = load float, float* @f1, align 4
|
||||
%1 = load float, float* @f2, align 4
|
||||
%cmp = fcmp ogt float %0, %1
|
||||
; CHECK-LABEL: fgt1:
|
||||
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
|
||||
; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
|
||||
; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.ule.s $f[[REG_F1]], $f[[REG_F2]]
|
||||
; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @fle1() {
|
||||
entry:
|
||||
%0 = load float, float* @f1, align 4
|
||||
%1 = load float, float* @f2, align 4
|
||||
%cmp = fcmp ole float %0, %1
|
||||
; CHECK-LABEL: fle1:
|
||||
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
|
||||
; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
|
||||
; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.ole.s $f[[REG_F1]], $f[[REG_F2]]
|
||||
; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @fge1() {
|
||||
entry:
|
||||
%0 = load float, float* @f1, align 4
|
||||
%1 = load float, float* @f2, align 4
|
||||
%cmp = fcmp oge float %0, %1
|
||||
; CHECK-LABEL: fge1:
|
||||
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
|
||||
; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
|
||||
; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.ult.s $f[[REG_F1]], $f[[REG_F2]]
|
||||
; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @deq1() {
|
||||
entry:
|
||||
%0 = load double, double* @d1, align 8
|
||||
%1 = load double, double* @d2, align 8
|
||||
%cmp = fcmp oeq double %0, %1
|
||||
; CHECK-LABEL: deq1:
|
||||
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
|
||||
; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
|
||||
; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]
|
||||
; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dne1() {
|
||||
entry:
|
||||
%0 = load double, double* @d1, align 8
|
||||
%1 = load double, double* @d2, align 8
|
||||
%cmp = fcmp une double %0, %1
|
||||
; CHECK-LABEL: dne1:
|
||||
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
|
||||
; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
|
||||
; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]
|
||||
; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dlt1() {
|
||||
entry:
|
||||
%0 = load double, double* @d1, align 8
|
||||
%1 = load double, double* @d2, align 8
|
||||
%cmp = fcmp olt double %0, %1
|
||||
; CHECK-LABEL: dlt1:
|
||||
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
|
||||
; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
|
||||
; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.olt.d $f[[REG_D1]], $f[[REG_D2]]
|
||||
; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dgt1() {
|
||||
entry:
|
||||
%0 = load double, double* @d1, align 8
|
||||
%1 = load double, double* @d2, align 8
|
||||
%cmp = fcmp ogt double %0, %1
|
||||
; CHECK-LABEL: dgt1:
|
||||
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
|
||||
; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
|
||||
; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.ule.d $f[[REG_D1]], $f[[REG_D2]]
|
||||
; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dle1() {
|
||||
entry:
|
||||
%0 = load double, double* @d1, align 8
|
||||
%1 = load double, double* @d2, align 8
|
||||
%cmp = fcmp ole double %0, %1
|
||||
; CHECK-LABEL: dle1:
|
||||
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
|
||||
; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
|
||||
; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.ole.d $f[[REG_D1]], $f[[REG_D2]]
|
||||
; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dge1() {
|
||||
entry:
|
||||
%0 = load double, double* @d1, align 8
|
||||
%1 = load double, double* @d2, align 8
|
||||
%cmp = fcmp oge double %0, %1
|
||||
; CHECK-LABEL: dge1:
|
||||
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
|
||||
; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
|
||||
; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
|
||||
; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
|
||||
; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
|
||||
; CHECK: c.ult.d $f[[REG_D1]], $f[[REG_D2]]
|
||||
; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
|
||||
@f = global float 0x40147E6B80000000, align 4
|
||||
@d_f = common global double 0.000000e+00, align 8
|
||||
@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dv() #0 {
|
||||
entry:
|
||||
%0 = load float, float* @f, align 4
|
||||
%conv = fpext float %0 to double
|
||||
; CHECK: cvt.d.s $f{{[0-9]+}}, $f{{[0-9]+}}
|
||||
store double %conv, double* @d_f, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
attributes #1 = { nounwind }
|
||||
@ -1,35 +0,0 @@
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
|
||||
|
||||
@f = global float 0x40D6E83280000000, align 4
|
||||
@d = global double 0x4132D68780000000, align 8
|
||||
@i_f = common global i32 0, align 4
|
||||
@i_d = common global i32 0, align 4
|
||||
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @ifv() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent ifv
|
||||
%0 = load float, float* @f, align 4
|
||||
%conv = fptosi float %0 to i32
|
||||
; CHECK: trunc.w.s $f[[REG:[0-9]+]], $f{{[0-9]+}}
|
||||
; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]]
|
||||
store i32 %conv, i32* @i_f, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @idv() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent idv
|
||||
%0 = load double, double* @d, align 8
|
||||
%conv = fptosi double %0 to i32
|
||||
; CHECK: trunc.w.d $f[[REG:[0-9]+]], $f{{[0-9]+}}
|
||||
; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]]
|
||||
store i32 %conv, i32* @i_d, align 4
|
||||
ret void
|
||||
}
|
||||
@ -1,20 +0,0 @@
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
|
||||
@d = global double 0x40147E6B74DF0446, align 8
|
||||
@f = common global float 0.000000e+00, align 4
|
||||
@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @fv() #0 {
|
||||
entry:
|
||||
%0 = load double, double* @d, align 8
|
||||
%conv = fptrunc double %0 to float
|
||||
; CHECK: cvt.s.d $f{{[0-9]+}}, $f{{[0-9]+}}
|
||||
store float %conv, float* @f, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #1 = { nounwind }
|
||||
210
external/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
vendored
210
external/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
vendored
@ -1,210 +0,0 @@
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
|
||||
@c = global i32 4, align 4
|
||||
@d = global i32 9, align 4
|
||||
@uc = global i32 4, align 4
|
||||
@ud = global i32 9, align 4
|
||||
@b1 = common global i32 0, align 4
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @eq() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent eq
|
||||
|
||||
%0 = load i32, i32* @c, align 4
|
||||
%1 = load i32, i32* @d, align 4
|
||||
%cmp = icmp eq i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
|
||||
; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
|
||||
; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
|
||||
; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
|
||||
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @ne() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent ne
|
||||
%0 = load i32, i32* @c, align 4
|
||||
%1 = load i32, i32* @d, align 4
|
||||
%cmp = icmp ne i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
|
||||
; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
|
||||
; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
|
||||
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
|
||||
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @ugt() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent ugt
|
||||
%0 = load i32, i32* @uc, align 4
|
||||
%1 = load i32, i32* @ud, align 4
|
||||
%cmp = icmp ugt i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
|
||||
; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
|
||||
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
|
||||
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @ult() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent ult
|
||||
%0 = load i32, i32* @uc, align 4
|
||||
%1 = load i32, i32* @ud, align 4
|
||||
%cmp = icmp ult i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
|
||||
; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
|
||||
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @uge() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent uge
|
||||
%0 = load i32, i32* @uc, align 4
|
||||
%1 = load i32, i32* @ud, align 4
|
||||
%cmp = icmp uge i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
|
||||
; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
|
||||
; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
|
||||
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @ule() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent ule
|
||||
%0 = load i32, i32* @uc, align 4
|
||||
%1 = load i32, i32* @ud, align 4
|
||||
%cmp = icmp ule i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
|
||||
; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
|
||||
; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
|
||||
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @sgt() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent sgt
|
||||
%0 = load i32, i32* @c, align 4
|
||||
%1 = load i32, i32* @d, align 4
|
||||
%cmp = icmp sgt i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
|
||||
; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
|
||||
; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @slt() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent slt
|
||||
%0 = load i32, i32* @c, align 4
|
||||
%1 = load i32, i32* @d, align 4
|
||||
%cmp = icmp slt i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
|
||||
; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
|
||||
; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @sge() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent sge
|
||||
%0 = load i32, i32* @c, align 4
|
||||
%1 = load i32, i32* @d, align 4
|
||||
%cmp = icmp sge i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
|
||||
; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
|
||||
; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
|
||||
; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @sle() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent sle
|
||||
%0 = load i32, i32* @c, align 4
|
||||
%1 = load i32, i32* @d, align 4
|
||||
%cmp = icmp sle i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
|
||||
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
|
||||
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
|
||||
; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
|
||||
; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
|
||||
; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
|
||||
store i32 %conv, i32* @b1, align 4
|
||||
ret void
|
||||
}
|
||||
@ -1,85 +0,0 @@
|
||||
; ModuleID = 'loadstore2.c'
|
||||
target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
|
||||
target triple = "mips--linux-gnu"
|
||||
|
||||
@c2 = common global i8 0, align 1
|
||||
@c1 = common global i8 0, align 1
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
|
||||
@s2 = common global i16 0, align 2
|
||||
@s1 = common global i16 0, align 2
|
||||
@i2 = common global i32 0, align 4
|
||||
@i1 = common global i32 0, align 4
|
||||
@f2 = common global float 0.000000e+00, align 4
|
||||
@f1 = common global float 0.000000e+00, align 4
|
||||
@d2 = common global double 0.000000e+00, align 8
|
||||
@d1 = common global double 0.000000e+00, align 8
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @cfoo() #0 {
|
||||
entry:
|
||||
%0 = load i8, i8* @c2, align 1
|
||||
store i8 %0, i8* @c1, align 1
|
||||
; CHECK-LABEL: cfoo:
|
||||
; CHECK: lbu $[[REGc:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: sb $[[REGc]], 0(${{[0-9]+}})
|
||||
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @sfoo() #0 {
|
||||
entry:
|
||||
%0 = load i16, i16* @s2, align 2
|
||||
store i16 %0, i16* @s1, align 2
|
||||
; CHECK-LABEL: sfoo:
|
||||
; CHECK: lhu $[[REGs:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: sh $[[REGs]], 0(${{[0-9]+}})
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @ifoo() #0 {
|
||||
entry:
|
||||
%0 = load i32, i32* @i2, align 4
|
||||
store i32 %0, i32* @i1, align 4
|
||||
; CHECK-LABEL: ifoo:
|
||||
; CHECK: lw $[[REGi:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: sw $[[REGi]], 0(${{[0-9]+}})
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @ffoo() #0 {
|
||||
entry:
|
||||
%0 = load float, float* @f2, align 4
|
||||
store float %0, float* @f1, align 4
|
||||
; CHECK-LABEL: ffoo:
|
||||
; CHECK: lwc1 $f[[REGf:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: swc1 $f[[REGf]], 0(${{[0-9]+}})
|
||||
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dfoo() #0 {
|
||||
entry:
|
||||
%0 = load double, double* @d2, align 8
|
||||
store double %0, double* @d1, align 8
|
||||
; CHECK-LABEL: dfoo:
|
||||
; CHECK: ldc1 $f[[REGd:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: sdc1 $f[[REGd]], 0(${{[0-9]+}})
|
||||
; CHECK: .end dfoo
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
|
||||
|
||||
@ -1,179 +0,0 @@
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
|
||||
; RUN: < %s | FileCheck %s -check-prefix=mips32r2
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
|
||||
; RUN: < %s | FileCheck %s -check-prefix=mips32
|
||||
|
||||
@b2 = global i8 0, align 1
|
||||
@b1 = global i8 1, align 1
|
||||
@uc1 = global i8 0, align 1
|
||||
@uc2 = global i8 -1, align 1
|
||||
@sc1 = global i8 -128, align 1
|
||||
@sc2 = global i8 127, align 1
|
||||
@ss1 = global i16 -32768, align 2
|
||||
@ss2 = global i16 32767, align 2
|
||||
@us1 = global i16 0, align 2
|
||||
@us2 = global i16 -1, align 2
|
||||
@ssi = global i16 0, align 2
|
||||
@ssj = global i16 0, align 2
|
||||
@i = global i32 0, align 4
|
||||
@j = global i32 0, align 4
|
||||
@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
|
||||
@.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z3b_iv() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent _Z3b_iv
|
||||
%0 = load i8, i8* @b1, align 1
|
||||
%tobool = trunc i8 %0 to i1
|
||||
%frombool = zext i1 %tobool to i8
|
||||
store i8 %frombool, i8* @b2, align 1
|
||||
%1 = load i8, i8* @b2, align 1
|
||||
%tobool1 = trunc i8 %1 to i1
|
||||
%conv = zext i1 %tobool1 to i32
|
||||
store i32 %conv, i32* @i, align 4
|
||||
; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: andi $[[REG2:[0-9]+]], $[[REG1]], 1
|
||||
; CHECK: sb $[[REG2]], 0(${{[0-9]+}})
|
||||
|
||||
|
||||
|
||||
ret void
|
||||
; CHECK: .end _Z3b_iv
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z4uc_iv() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent _Z4uc_iv
|
||||
|
||||
%0 = load i8, i8* @uc1, align 1
|
||||
%conv = zext i8 %0 to i32
|
||||
store i32 %conv, i32* @i, align 4
|
||||
%1 = load i8, i8* @uc2, align 1
|
||||
%conv1 = zext i8 %1 to i32
|
||||
; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
|
||||
|
||||
store i32 %conv1, i32* @j, align 4
|
||||
ret void
|
||||
; CHECK: .end _Z4uc_iv
|
||||
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z4sc_iv() {
|
||||
entry:
|
||||
; mips32r2-LABEL: .ent _Z4sc_iv
|
||||
; mips32-LABEL: .ent _Z4sc_iv
|
||||
|
||||
%0 = load i8, i8* @sc1, align 1
|
||||
%conv = sext i8 %0 to i32
|
||||
store i32 %conv, i32* @i, align 4
|
||||
%1 = load i8, i8* @sc2, align 1
|
||||
%conv1 = sext i8 %1 to i32
|
||||
store i32 %conv1, i32* @j, align 4
|
||||
; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
|
||||
; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
|
||||
; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
|
||||
|
||||
ret void
|
||||
; CHECK: .end _Z4sc_iv
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z4us_iv() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent _Z4us_iv
|
||||
%0 = load i16, i16* @us1, align 2
|
||||
%conv = zext i16 %0 to i32
|
||||
store i32 %conv, i32* @i, align 4
|
||||
%1 = load i16, i16* @us2, align 2
|
||||
%conv1 = zext i16 %1 to i32
|
||||
store i32 %conv1, i32* @j, align 4
|
||||
ret void
|
||||
; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 65535
|
||||
; CHECK: .end _Z4us_iv
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z4ss_iv() {
|
||||
entry:
|
||||
; mips32r2-LABEL: .ent _Z4ss_iv
|
||||
; mips32=LABEL: .ent _Z4ss_iv
|
||||
|
||||
%0 = load i16, i16* @ss1, align 2
|
||||
%conv = sext i16 %0 to i32
|
||||
store i32 %conv, i32* @i, align 4
|
||||
%1 = load i16, i16* @ss2, align 2
|
||||
%conv1 = sext i16 %1 to i32
|
||||
store i32 %conv1, i32* @j, align 4
|
||||
; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; mips32r2: seh ${{[0-9]+}}, $[[REG1]]
|
||||
; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16
|
||||
; mips32: sra ${{[0-9]+}}, $[[REG2]], 16
|
||||
|
||||
ret void
|
||||
; CHECK: .end _Z4ss_iv
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z4b_ssv() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent _Z4b_ssv
|
||||
%0 = load i8, i8* @b2, align 1
|
||||
%tobool = trunc i8 %0 to i1
|
||||
%conv = zext i1 %tobool to i16
|
||||
store i16 %conv, i16* @ssi, align 2
|
||||
ret void
|
||||
; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
|
||||
; CHECK: .end _Z4b_ssv
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z5uc_ssv() {
|
||||
entry:
|
||||
; CHECK-LABEL: .ent _Z5uc_ssv
|
||||
%0 = load i8, i8* @uc1, align 1
|
||||
%conv = zext i8 %0 to i16
|
||||
store i16 %conv, i16* @ssi, align 2
|
||||
%1 = load i8, i8* @uc2, align 1
|
||||
%conv1 = zext i8 %1 to i16
|
||||
; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
|
||||
|
||||
store i16 %conv1, i16* @ssj, align 2
|
||||
ret void
|
||||
; CHECK: .end _Z5uc_ssv
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z5sc_ssv() {
|
||||
entry:
|
||||
; mips32r2-LABEL: .ent _Z5sc_ssv
|
||||
; mips32-LABEL: .ent _Z5sc_ssv
|
||||
%0 = load i8, i8* @sc1, align 1
|
||||
%conv = sext i8 %0 to i16
|
||||
store i16 %conv, i16* @ssi, align 2
|
||||
%1 = load i8, i8* @sc2, align 1
|
||||
%conv1 = sext i8 %1 to i16
|
||||
store i16 %conv1, i16* @ssj, align 2
|
||||
; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
|
||||
; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
|
||||
; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
|
||||
|
||||
ret void
|
||||
; CHECK: .end _Z5sc_ssv
|
||||
}
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
|
||||
; RUN: < %s | FileCheck %s
|
||||
|
||||
@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
|
||||
@s = common global i8* null, align 4
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @foo() #0 {
|
||||
entry:
|
||||
store i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i8** @s, align 4
|
||||
ret void
|
||||
; CHECK: .ent foo
|
||||
; CHECK: lw $[[REG1:[0-9]+]], %got($.str)(${{[0-9]+}})
|
||||
; CHECK: addiu ${{[0-9]+}}, $[[REG1]], %lo($.str)
|
||||
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
|
||||
606
external/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
vendored
606
external/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
vendored
File diff suppressed because it is too large
Load Diff
@ -1,74 +0,0 @@
|
||||
; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
|
||||
; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefix=ALL -check-prefix=32R1
|
||||
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
|
||||
; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefix=ALL -check-prefix=32R2
|
||||
|
||||
@str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1
|
||||
@src = global i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i32 0, i32 0), align 4
|
||||
@i = global i32 12, align 4
|
||||
@dest = common global [50 x i8] zeroinitializer, align 1
|
||||
|
||||
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1)
|
||||
declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1)
|
||||
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1)
|
||||
|
||||
define void @cpy(i8* %src, i32 %i) {
|
||||
; ALL-LABEL: cpy:
|
||||
|
||||
; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
|
||||
; ALL-DAG: sw $4, 24($sp)
|
||||
; ALL-DAG: move $4, $[[T0]]
|
||||
; ALL-DAG: sw $5, 20($sp)
|
||||
; ALL-DAG: lw $[[T1:[0-9]+]], 24($sp)
|
||||
; ALL-DAG: move $5, $[[T1]]
|
||||
; ALL-DAG: lw $6, 20($sp)
|
||||
; ALL-DAG: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}})
|
||||
; ALL: jalr $[[T2]]
|
||||
; ALL-NEXT: nop
|
||||
; ALL-NOT: {{.*}}$2{{.*}}
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0),
|
||||
i8* %src, i32 %i, i32 1, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @mov(i8* %src, i32 %i) {
|
||||
; ALL-LABEL: mov:
|
||||
|
||||
|
||||
; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
|
||||
; ALL-DAG: sw $4, 24($sp)
|
||||
; ALL-DAG: move $4, $[[T0]]
|
||||
; ALL-DAG: sw $5, 20($sp)
|
||||
; ALL-DAG: lw $[[T1:[0-9]+]], 24($sp)
|
||||
; ALL-DAG: move $5, $[[T1]]
|
||||
; ALL-DAG: lw $6, 20($sp)
|
||||
; ALL-DAG: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}})
|
||||
; ALL: jalr $[[T2]]
|
||||
; ALL-NEXT: nop
|
||||
; ALL-NOT: {{.*}}$2{{.*}}
|
||||
call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0),
|
||||
i8* %src, i32 %i, i32 1, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @clear(i32 %i) {
|
||||
; ALL-LABEL: clear:
|
||||
|
||||
; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
|
||||
; ALL-DAG: sw $4, 16($sp)
|
||||
; ALL-DAG: move $4, $[[T0]]
|
||||
; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 42
|
||||
; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T1]], 24
|
||||
; 32R1-DAG: sra $5, $[[T2]], 24
|
||||
; 32R2-DAG: seb $5, $[[T1]]
|
||||
; ALL-DAG: lw $6, 16($sp)
|
||||
; ALL-DAG: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}})
|
||||
; ALL: jalr $[[T2]]
|
||||
; ALL-NEXT: nop
|
||||
; ALL-NOT: {{.*}}$2{{.*}}
|
||||
call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0),
|
||||
i8 42, i32 %i, i32 1, i1 false)
|
||||
ret void
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user