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Imported Upstream version 5.18.0.207

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Former-commit-id: 3b152f462918d427ce18620a2cbe4f8b79650449
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Xamarin Public Jenkins (auto-signing)
2018-11-17 08:23:10 +00:00
parent 8e12397d70
commit eb85e2fc17
28480 changed files with 72 additions and 3866936 deletions
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84
external/llvm/test/CodeGen/Hexagon/Atomics.ll vendored
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@@ -1,84 +0,0 @@
; RUN: llc < %s -march=hexagon
@si = common global i32 0, align 4
@sll = common global i64 0, align 8
define void @test_op_ignore() nounwind {
entry:
%t00 = atomicrmw add i32* @si, i32 1 monotonic
%t01 = atomicrmw add i64* @sll, i64 1 monotonic
%t10 = atomicrmw sub i32* @si, i32 1 monotonic
%t11 = atomicrmw sub i64* @sll, i64 1 monotonic
%t20 = atomicrmw or i32* @si, i32 1 monotonic
%t21 = atomicrmw or i64* @sll, i64 1 monotonic
%t30 = atomicrmw xor i32* @si, i32 1 monotonic
%t31 = atomicrmw xor i64* @sll, i64 1 monotonic
%t40 = atomicrmw and i32* @si, i32 1 monotonic
%t41 = atomicrmw and i64* @sll, i64 1 monotonic
%t50 = atomicrmw nand i32* @si, i32 1 monotonic
%t51 = atomicrmw nand i64* @sll, i64 1 monotonic
br label %return
return: ; preds = %entry
ret void
}
define void @test_fetch_and_op() nounwind {
entry:
%t00 = atomicrmw add i32* @si, i32 11 monotonic
store i32 %t00, i32* @si, align 4
%t01 = atomicrmw add i64* @sll, i64 11 monotonic
store i64 %t01, i64* @sll, align 8
%t10 = atomicrmw sub i32* @si, i32 11 monotonic
store i32 %t10, i32* @si, align 4
%t11 = atomicrmw sub i64* @sll, i64 11 monotonic
store i64 %t11, i64* @sll, align 8
%t20 = atomicrmw or i32* @si, i32 11 monotonic
store i32 %t20, i32* @si, align 4
%t21 = atomicrmw or i64* @sll, i64 11 monotonic
store i64 %t21, i64* @sll, align 8
%t30 = atomicrmw xor i32* @si, i32 11 monotonic
store i32 %t30, i32* @si, align 4
%t31 = atomicrmw xor i64* @sll, i64 11 monotonic
store i64 %t31, i64* @sll, align 8
%t40 = atomicrmw and i32* @si, i32 11 monotonic
store i32 %t40, i32* @si, align 4
%t41 = atomicrmw and i64* @sll, i64 11 monotonic
store i64 %t41, i64* @sll, align 8
%t50 = atomicrmw nand i32* @si, i32 11 monotonic
store i32 %t50, i32* @si, align 4
%t51 = atomicrmw nand i64* @sll, i64 11 monotonic
store i64 %t51, i64* @sll, align 8
br label %return
return: ; preds = %entry
ret void
}
define void @test_lock() nounwind {
entry:
%t00 = atomicrmw xchg i32* @si, i32 1 monotonic
store i32 %t00, i32* @si, align 4
%t01 = atomicrmw xchg i64* @sll, i64 1 monotonic
store i64 %t01, i64* @sll, align 8
fence seq_cst
store volatile i32 0, i32* @si, align 4
store volatile i64 0, i64* @sll, align 8
br label %return
return: ; preds = %entry
ret void
}
define i64 @fred() nounwind {
entry:
%s0 = cmpxchg i32* undef, i32 undef, i32 undef seq_cst seq_cst
%s1 = extractvalue { i32, i1 } %s0, 0
%t0 = cmpxchg i64* undef, i64 undef, i64 undef seq_cst seq_cst
%t1 = extractvalue { i64, i1 } %t0, 0
%u0 = zext i32 %s1 to i64
%u1 = add i64 %u0, %t1
ret i64 %u1
}

76
external/llvm/test/CodeGen/Hexagon/BranchPredict.ll vendored
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@@ -1,76 +0,0 @@
; RUN: llc -march=hexagon -ifcvt-limit=0 < %s | FileCheck %s
; Check if the branch probabilities are reflected in the instructions:
; The basic block placement pass should place the more probable successor
; block as the fall-through block. The unconditional jump in the predecessor
; should then get the right hint (not_taken or ":nt")
@j = external global i32
define i32 @foo(i32 %a) nounwind {
; CHECK: if (!p{{[0-3]}}.new) jump:nt
entry:
%tobool = icmp eq i32 %a, 0
br i1 %tobool, label %if.else, label %if.then, !prof !0
if.then: ; preds = %entry
%add = add nsw i32 %a, 10
%call = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add) nounwind
br label %return
if.else: ; preds = %entry
%call2 = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 4) nounwind
br label %return
return: ; preds = %if.else, %if.then
%retval.0 = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
ret i32 %retval.0
}
declare i32 @foobar(...)
define i32 @bar(i32 %a) nounwind {
; CHECK: if (p{{[0-3]}}.new) jump:nt
entry:
%tobool = icmp eq i32 %a, 0
br i1 %tobool, label %if.else, label %if.then, !prof !1
if.then: ; preds = %entry
%add = add nsw i32 %a, 10
%call = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add) nounwind
br label %return
if.else: ; preds = %entry
%call2 = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 4) nounwind
br label %return
return: ; preds = %if.else, %if.then
%retval.0 = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
ret i32 %retval.0
}
define i32 @foo_bar(i32 %a, i16 signext %b) nounwind {
; CHECK: if (!cmp.eq(r{{[0-9]*}}.new,#0)) jump:nt
entry:
%0 = load i32, i32* @j, align 4
%tobool = icmp eq i32 %0, 0
br i1 %tobool, label %if.else, label %if.then, !prof !0
if.then: ; preds = %entry
%add = add nsw i32 %a, 10
%call = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add) nounwind
br label %return
if.else: ; preds = %entry
%add1 = add nsw i32 %a, 4
%call2 = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add1) nounwind
br label %return
return: ; preds = %if.else, %if.then
%retval.0 = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
ret i32 %retval.0
}
!0 = !{!"branch_weights", i32 64, i32 4}
!1 = !{!"branch_weights", i32 4, i32 64}

89
external/llvm/test/CodeGen/Hexagon/NVJumpCmp.ll vendored
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@@ -1,89 +0,0 @@
; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s
; Look for an instruction, we really just do not want to see an abort.
; CHECK: trace_event
; REQUIRES: asserts
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind
define void @_ZN6Halide7Runtime8Internal13default_traceEPvPK18halide_trace_event() #0 {
entry:
br i1 undef, label %if.then, label %if.else
if.then: ; preds = %entry
br label %while.cond
while.cond: ; preds = %while.cond, %if.then
br i1 undef, label %while.cond, label %while.end
while.end: ; preds = %while.cond
%add = add i32 undef, 48
br i1 undef, label %if.end, label %if.then17
if.then17: ; preds = %while.end
unreachable
if.end: ; preds = %while.end
%arrayidx21 = getelementptr inbounds [4096 x i8], [4096 x i8]* undef, i32 0, i32 8
store i8 undef, i8* %arrayidx21, align 4, !tbaa !1
br i1 undef, label %for.body42.preheader6, label %min.iters.checked
for.body42.preheader6: ; preds = %vector.body.preheader, %min.iters.checked, %if.end
unreachable
min.iters.checked: ; preds = %if.end
br i1 undef, label %for.body42.preheader6, label %vector.body.preheader
vector.body.preheader: ; preds = %min.iters.checked
br i1 undef, label %for.cond48.preheader, label %for.body42.preheader6
for.cond48.preheader: ; preds = %vector.body.preheader
br i1 undef, label %while.cond.i, label %for.body61.lr.ph
for.body61.lr.ph: ; preds = %for.cond48.preheader
br i1 undef, label %for.body61, label %min.iters.checked595
min.iters.checked595: ; preds = %for.body61.lr.ph
br i1 undef, label %for.body61, label %vector.memcheck608
vector.memcheck608: ; preds = %min.iters.checked595
%scevgep600 = getelementptr [4096 x i8], [4096 x i8]* undef, i32 0, i32 %add
%bound0604 = icmp ule i8* %scevgep600, undef
%memcheck.conflict607 = and i1 undef, %bound0604
br i1 %memcheck.conflict607, label %for.body61, label %vector.body590
vector.body590: ; preds = %vector.body590, %vector.memcheck608
br i1 undef, label %middle.block591, label %vector.body590, !llvm.loop !4
middle.block591: ; preds = %vector.body590
%cmp.n613 = icmp eq i32 undef, 0
br i1 %cmp.n613, label %while.cond.i, label %for.body61
while.cond.i: ; preds = %for.body61, %while.cond.i, %middle.block591, %for.cond48.preheader
br i1 undef, label %_ZN6Halide7Runtime8Internal14ScopedSpinLockC2EPVi.exit, label %while.cond.i
_ZN6Halide7Runtime8Internal14ScopedSpinLockC2EPVi.exit: ; preds = %while.cond.i
unreachable
for.body61: ; preds = %for.body61, %middle.block591, %vector.memcheck608, %min.iters.checked595, %for.body61.lr.ph
%cmp59 = icmp ult i32 undef, undef
br i1 %cmp59, label %for.body61, label %while.cond.i, !llvm.loop !7
if.else: ; preds = %entry
unreachable
}
attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
!llvm.module.flags = !{!0}
!0 = !{i32 2, !"halide_mattrs", !"+hvx"}
!1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"}
!4 = distinct !{!4, !5, !6}
!5 = !{!"llvm.loop.vectorize.width", i32 1}
!6 = !{!"llvm.loop.interleave.count", i32 1}
!7 = distinct !{!7, !5, !6}

50
external/llvm/test/CodeGen/Hexagon/PR33749.ll vendored
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@@ -1,50 +0,0 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; This testcase used to fail with "cannot select 'i1 = add x, y'".
; Check for some sane output:
; CHECK: xor(p{{[0-3]}},p{{[0-3]}})
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define void @foo(i32* nocapture %a0) local_unnamed_addr #0 {
b1:
%v2 = getelementptr inbounds i32, i32* %a0, i32 26
%v3 = load i32, i32* %v2, align 4
%v4 = add nsw i32 %v3, 1
%v5 = load i32, i32* %a0, align 4
br label %b6
b6: ; preds = %b28, %b1
%v7 = phi i32 [ %v29, %b28 ], [ %v5, %b1 ]
%v8 = mul nsw i32 %v4, %v7
%v9 = add nsw i32 %v8, %v7
%v10 = mul i32 %v7, %v7
%v11 = mul i32 %v10, %v9
%v12 = add nsw i32 %v11, 1
%v13 = mul nsw i32 %v12, %v7
%v14 = add nsw i32 %v13, %v7
%v15 = mul i32 %v10, %v14
%v16 = and i32 %v15, 1
%v17 = add nsw i32 %v16, -1
%v18 = mul i32 %v10, %v7
%v19 = mul i32 %v18, %v11
%v20 = mul i32 %v19, %v17
%v21 = and i32 %v20, 1
%v22 = add nsw i32 %v21, -1
%v23 = mul nsw i32 %v22, %v3
%v24 = sub nsw i32 %v7, %v23
%v25 = mul i32 %v10, %v24
%v26 = sub i32 0, %v7
%v27 = icmp eq i32 %v25, %v26
br i1 %v27, label %b30, label %b28
b28: ; preds = %b6
%v29 = add nsw i32 %v3, %v7
store i32 %v29, i32* %a0, align 4
br label %b6
b30: ; preds = %b6
ret void
}
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" }

202
external/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll vendored
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@@ -1,202 +0,0 @@
; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s
; This was aborting while processing SUnits.
; CHECK: vmem
source_filename = "bugpoint-output-bdb0052.bc"
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #0
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #0
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #0
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32>, <16 x i32>, i32) #0
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32>, <16 x i32>) #0
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32>, <16 x i32>) #0
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32>, <16 x i32>) #0
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32>, <16 x i32>, i32) #0
define void @__error_op_vmpy_v__uh_v__uh__1() #1 {
entry:
%in_u16.host181 = load i16*, i16** undef, align 4
%in_u32.host182 = load i32*, i32** undef, align 4
br label %"for op_vmpy_v__uh_v__uh__1.s0.y"
"for op_vmpy_v__uh_v__uh__1.s0.y": ; preds = %"end for op_vmpy_v__uh_v__uh__1.s0.x.x", %entry
%op_vmpy_v__uh_v__uh__1.s0.y = phi i32 [ 0, %entry ], [ %63, %"end for op_vmpy_v__uh_v__uh__1.s0.x.x" ]
%0 = mul nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.y, 768
%1 = add nuw nsw i32 %0, 32
%2 = add nuw nsw i32 %0, 64
%3 = add nuw nsw i32 %0, 96
br label %"for op_vmpy_v__uh_v__uh__1.s0.x.x"
"for op_vmpy_v__uh_v__uh__1.s0.x.x": ; preds = %"for op_vmpy_v__uh_v__uh__1.s0.x.x", %"for op_vmpy_v__uh_v__uh__1.s0.y"
%.phi210 = phi i32* [ %in_u32.host182, %"for op_vmpy_v__uh_v__uh__1.s0.y" ], [ %.inc211.3, %"for op_vmpy_v__uh_v__uh__1.s0.x.x" ]
%.phi213 = phi i16* [ %in_u16.host181, %"for op_vmpy_v__uh_v__uh__1.s0.y" ], [ %.inc214.3, %"for op_vmpy_v__uh_v__uh__1.s0.x.x" ]
%op_vmpy_v__uh_v__uh__1.s0.x.x = phi i32 [ 0, %"for op_vmpy_v__uh_v__uh__1.s0.y" ], [ %61, %"for op_vmpy_v__uh_v__uh__1.s0.x.x" ]
%4 = mul nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.x.x, 32
%5 = bitcast i32* %.phi210 to <16 x i32>*
%6 = load <16 x i32>, <16 x i32>* %5, align 64, !tbaa !1
%7 = add nuw nsw i32 %4, 16
%8 = getelementptr inbounds i32, i32* %in_u32.host182, i32 %7
%9 = bitcast i32* %8 to <16 x i32>*
%10 = load <16 x i32>, <16 x i32>* %9, align 64, !tbaa !1
%11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %10, <16 x i32> %6)
%e.i = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %11) #2
%o.i = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %11) #2
%r.i = tail call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> %o.i, <16 x i32> %e.i, i32 -4) #2
%12 = bitcast i16* %.phi213 to <16 x i32>*
%13 = load <16 x i32>, <16 x i32>* %12, align 64, !tbaa !4
%a_lo.i = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i) #2
%a_hi.i = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i) #2
%a_e.i = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> %a_hi.i, <16 x i32> %a_lo.i) #2
%a_o.i = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %a_hi.i, <16 x i32> %a_lo.i) #2
%ab_e.i = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_e.i, <16 x i32> %13) #2
%ab_o.i = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_o.i, <16 x i32> %13) #2
%a_lo.i.i = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %ab_e.i) #2
%l_lo.i.i = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %ab_o.i) #2
%s_lo.i.i = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %a_lo.i.i, <16 x i32> %l_lo.i.i, i32 16) #2
%l_hi.i.i = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_o.i) #2
%s_hi.i.i = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> undef, <16 x i32> %l_hi.i.i, i32 16) #2
%s.i.i = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %s_hi.i.i, <16 x i32> %s_lo.i.i) #2
%e.i189 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %s.i.i) #2
%o.i190 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %s.i.i) #2
%r.i191 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %o.i190, <16 x i32> %e.i189, i32 -4) #2
%14 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i191)
%15 = add nuw nsw i32 %4, %0
%16 = getelementptr inbounds i32, i32* undef, i32 %15
%17 = bitcast i32* %16 to <16 x i32>*
store <16 x i32> %14, <16 x i32>* %17, align 64, !tbaa !6
%18 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i191)
store <16 x i32> %18, <16 x i32>* undef, align 64, !tbaa !6
%.inc211 = getelementptr i32, i32* %.phi210, i32 32
%.inc214 = getelementptr i16, i16* %.phi213, i32 32
%19 = bitcast i32* %.inc211 to <16 x i32>*
%20 = load <16 x i32>, <16 x i32>* %19, align 64, !tbaa !1
%21 = add nuw nsw i32 %4, 48
%22 = getelementptr inbounds i32, i32* %in_u32.host182, i32 %21
%23 = bitcast i32* %22 to <16 x i32>*
%24 = load <16 x i32>, <16 x i32>* %23, align 64, !tbaa !1
%25 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %24, <16 x i32> %20)
%e.i.1 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %25) #2
%r.i.1 = tail call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> undef, <16 x i32> %e.i.1, i32 -4) #2
%26 = bitcast i16* %.inc214 to <16 x i32>*
%27 = load <16 x i32>, <16 x i32>* %26, align 64, !tbaa !4
%a_lo.i.1 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i.1) #2
%a_e.i.1 = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> undef, <16 x i32> %a_lo.i.1) #2
%a_o.i.1 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> undef, <16 x i32> %a_lo.i.1) #2
%ab_e.i.1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_e.i.1, <16 x i32> %27) #2
%ab_o.i.1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_o.i.1, <16 x i32> %27) #2
%a_lo.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %ab_e.i.1) #2
%s_lo.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %a_lo.i.i.1, <16 x i32> undef, i32 16) #2
%a_hi.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_e.i.1) #2
%l_hi.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_o.i.1) #2
%s_hi.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %a_hi.i.i.1, <16 x i32> %l_hi.i.i.1, i32 16) #2
%s.i.i.1 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %s_hi.i.i.1, <16 x i32> %s_lo.i.i.1) #2
%e.i189.1 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %s.i.i.1) #2
%o.i190.1 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %s.i.i.1) #2
%r.i191.1 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %o.i190.1, <16 x i32> %e.i189.1, i32 -4) #2
%28 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i191.1)
%29 = add nuw nsw i32 %1, %4
%30 = getelementptr inbounds i32, i32* undef, i32 %29
%31 = bitcast i32* %30 to <16 x i32>*
store <16 x i32> %28, <16 x i32>* %31, align 64, !tbaa !6
%32 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i191.1)
%33 = add nuw nsw i32 %29, 16
%34 = getelementptr inbounds i32, i32* undef, i32 %33
%35 = bitcast i32* %34 to <16 x i32>*
store <16 x i32> %32, <16 x i32>* %35, align 64, !tbaa !6
%.inc211.1 = getelementptr i32, i32* %.phi210, i32 64
%.inc214.1 = getelementptr i16, i16* %.phi213, i32 64
%36 = bitcast i32* %.inc211.1 to <16 x i32>*
%37 = load <16 x i32>, <16 x i32>* %36, align 64, !tbaa !1
%38 = add nuw nsw i32 %4, 80
%39 = getelementptr inbounds i32, i32* %in_u32.host182, i32 %38
%40 = bitcast i32* %39 to <16 x i32>*
%41 = load <16 x i32>, <16 x i32>* %40, align 64, !tbaa !1
%42 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %41, <16 x i32> %37)
%e.i.2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %42) #2
%o.i.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %42) #2
%r.i.2 = tail call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> %o.i.2, <16 x i32> %e.i.2, i32 -4) #2
%43 = bitcast i16* %.inc214.1 to <16 x i32>*
%44 = load <16 x i32>, <16 x i32>* %43, align 64, !tbaa !4
%a_lo.i.2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i.2) #2
%a_hi.i.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i.2) #2
%a_e.i.2 = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> %a_hi.i.2, <16 x i32> %a_lo.i.2) #2
%a_o.i.2 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %a_hi.i.2, <16 x i32> %a_lo.i.2) #2
%ab_e.i.2 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_e.i.2, <16 x i32> %44) #2
%ab_o.i.2 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_o.i.2, <16 x i32> %44) #2
%l_lo.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %ab_o.i.2) #2
%s_lo.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> undef, <16 x i32> %l_lo.i.i.2, i32 16) #2
%a_hi.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_e.i.2) #2
%l_hi.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_o.i.2) #2
%s_hi.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %a_hi.i.i.2, <16 x i32> %l_hi.i.i.2, i32 16) #2
%s.i.i.2 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %s_hi.i.i.2, <16 x i32> %s_lo.i.i.2) #2
%e.i189.2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %s.i.i.2) #2
%o.i190.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %s.i.i.2) #2
%r.i191.2 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %o.i190.2, <16 x i32> %e.i189.2, i32 -4) #2
%45 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i191.2)
%46 = add nuw nsw i32 %2, %4
%47 = getelementptr inbounds i32, i32* undef, i32 %46
%48 = bitcast i32* %47 to <16 x i32>*
store <16 x i32> %45, <16 x i32>* %48, align 64, !tbaa !6
%49 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i191.2)
%50 = add nuw nsw i32 %46, 16
%51 = getelementptr inbounds i32, i32* undef, i32 %50
%52 = bitcast i32* %51 to <16 x i32>*
store <16 x i32> %49, <16 x i32>* %52, align 64, !tbaa !6
%e.i189.3 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> undef) #2
%r.i191.3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %e.i189.3, i32 -4) #2
%53 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i191.3)
%54 = add nuw nsw i32 %3, %4
%55 = getelementptr inbounds i32, i32* undef, i32 %54
%56 = bitcast i32* %55 to <16 x i32>*
store <16 x i32> %53, <16 x i32>* %56, align 64, !tbaa !6
%57 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i191.3)
%58 = add nuw nsw i32 %54, 16
%59 = getelementptr inbounds i32, i32* undef, i32 %58
%60 = bitcast i32* %59 to <16 x i32>*
store <16 x i32> %57, <16 x i32>* %60, align 64, !tbaa !6
%61 = add nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.x.x, 4
%62 = icmp eq i32 %61, 24
%.inc211.3 = getelementptr i32, i32* %.phi210, i32 128
%.inc214.3 = getelementptr i16, i16* %.phi213, i32 128
br i1 %62, label %"end for op_vmpy_v__uh_v__uh__1.s0.x.x", label %"for op_vmpy_v__uh_v__uh__1.s0.x.x"
"end for op_vmpy_v__uh_v__uh__1.s0.x.x": ; preds = %"for op_vmpy_v__uh_v__uh__1.s0.x.x"
%63 = add nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.y, 1
br label %"for op_vmpy_v__uh_v__uh__1.s0.y"
}
attributes #0 = { nounwind readnone }
attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #2 = { nounwind }
!llvm.module.flags = !{!0}
!0 = !{i32 2, !"halide_mattrs", !"+hvx"}
!1 = !{!2, !2, i64 0}
!2 = !{!"in_u32", !3}
!3 = !{!"Halide buffer"}
!4 = !{!5, !5, i64 0}
!5 = !{!"in_u16", !3}
!6 = !{!7, !7, i64 0}
!7 = !{!"op_vmpy_v__uh_v__uh__1", !3}

49
external/llvm/test/CodeGen/Hexagon/absaddr-store.ll vendored
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@@ -1,49 +0,0 @@
; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s
; Check that we generate load instructions with absolute addressing mode.
@a0 = external global i32
@a1 = external global i32
@b0 = external global i8
@b1 = external global i8
@c0 = external global i16
@c1 = external global i16
@d = external global i64
define zeroext i8 @absStoreByte() nounwind {
; CHECK: memb(##b1){{ *}}={{ *}}r{{[0-9]+}}
entry:
%0 = load i8, i8* @b0, align 1
%conv = zext i8 %0 to i32
%mul = mul nsw i32 100, %conv
%conv1 = trunc i32 %mul to i8
store i8 %conv1, i8* @b1, align 1
ret i8 %conv1
}
define signext i16 @absStoreHalf() nounwind {
; CHECK: memh(##c1){{ *}}={{ *}}r{{[0-9]+}}
entry:
%0 = load i16, i16* @c0, align 2
%conv = sext i16 %0 to i32
%mul = mul nsw i32 100, %conv
%conv1 = trunc i32 %mul to i16
store i16 %conv1, i16* @c1, align 2
ret i16 %conv1
}
define i32 @absStoreWord() nounwind {
; CHECK: memw(##a1){{ *}}={{ *}}r{{[0-9]+}}
entry:
%0 = load i32, i32* @a0, align 4
%mul = mul nsw i32 100, %0
store i32 %mul, i32* @a1, align 4
ret i32 %mul
}
define void @absStoreDouble() nounwind {
; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}}
entry:
store i64 100, i64* @d, align 8
ret void
}

18
external/llvm/test/CodeGen/Hexagon/absimm.ll vendored
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@@ -1,18 +0,0 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we generate absolute addressing mode instructions
; with immediate value.
define i32 @f1(i32 %i) nounwind {
; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}}
entry:
store volatile i32 %i, i32* inttoptr (i32 786432 to i32*), align 262144
ret i32 %i
}
define i32* @f2(i32* nocapture %i) nounwind {
entry:
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##786432)
%0 = load volatile i32, i32* inttoptr (i32 786432 to i32*), align 262144
%1 = inttoptr i32 %0 to i32*
ret i32* %1
}

13
external/llvm/test/CodeGen/Hexagon/addaddi.ll vendored
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@@ -1,13 +0,0 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check for S4_addaddi:
; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},add(r{{[0-9]+}},#2))
define i32 @fred(i32 %a0, i32 %a1, i32* nocapture %a2) #0 {
b3:
%v4 = add nsw i32 %a0, 2
%v5 = add nsw i32 %v4, %a1
store i32 %v5, i32* %a2, align 4
ret i32 undef
}
attributes #0 = { nounwind }

27
external/llvm/test/CodeGen/Hexagon/adde.ll vendored
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@@ -1,27 +0,0 @@
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
; CHECK-DAG: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
; CHECK-DAG: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
; CHECK-DAG: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
; CHECK-DAG: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
; CHECK-DAG: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
; CHECK-DAG: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
define void @check_adde_addc(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64* %a4, i64* %a5) {
b6:
%v7 = zext i64 %a0 to i128
%v8 = zext i64 %a1 to i128
%v9 = shl i128 %v8, 64
%v10 = or i128 %v7, %v9
%v11 = zext i64 %a2 to i128
%v12 = zext i64 %a3 to i128
%v13 = shl i128 %v12, 64
%v14 = or i128 %v11, %v13
%v15 = add i128 %v10, %v14
%v16 = lshr i128 %v15, 64
%v17 = trunc i128 %v15 to i64
%v18 = trunc i128 %v16 to i64
store i64 %v17, i64* %a4
store i64 %v18, i64* %a5
ret void
}

23
external/llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll vendored
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@@ -1,23 +0,0 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{H|h}})
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon-unknown-none"
define i32 @foo(i16 %a, i32 %b) #0 {
%and = and i16 %a, -4
%conv3 = sext i16 %and to i32
%add13 = mul i32 %b, 65536
%sext = add i32 %add13, 262144
%phitmp = ashr exact i32 %sext, 16
ret i32 %phitmp
}
attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
!0 = !{!"short", !1}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
!3 = !{!"any pointer", !1}

21
external/llvm/test/CodeGen/Hexagon/addh-shifted.ll vendored
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@@ -1,21 +0,0 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}}):<<16
define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone {
entry:
%conv.i = zext i16 %arg1 to i32
%conv1.i = zext i16 %arg2 to i32
%sub.i = add nsw i32 %conv.i, %conv1.i
%sext.i = shl i32 %sub.i, 16
%cmp.i = icmp slt i32 %sext.i, 65536
%0 = ashr exact i32 %sext.i, 16
%conv7.i = select i1 %cmp.i, i32 1, i32 %0
%cmp8.i = icmp sgt i32 %conv7.i, 4
%conv7.op.i = add i32 %conv7.i, 65535
%shl = shl i64 %arg0, 2
%.mask = and i32 %conv7.op.i, 65535
%1 = zext i32 %.mask to i64
%conv = select i1 %cmp8.i, i64 3, i64 %1
%or = or i64 %conv, %shl
ret i64 %or
}

21
external/llvm/test/CodeGen/Hexagon/addh.ll vendored
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@@ -1,21 +0,0 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}})
define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone {
entry:
%conv.i = zext i16 %arg1 to i32
%conv1.i = zext i16 %arg2 to i32
%sub.i = add nsw i32 %conv.i, %conv1.i
%sext.i = shl i32 %sub.i, 16
%cmp.i = icmp slt i32 %sext.i, 65536
%0 = ashr exact i32 %sext.i, 16
%conv7.i = select i1 %cmp.i, i32 1, i32 %0
%cmp8.i = icmp sgt i32 %conv7.i, 4
%conv7.op.i = add i32 %conv7.i, 65535
%shl = shl i64 %arg0, 2
%.mask = and i32 %conv7.op.i, 65535
%1 = zext i32 %.mask to i64
%conv = select i1 %cmp8.i, i64 3, i64 %1
%or = or i64 %conv, %shl
ret i64 %or
}

54
external/llvm/test/CodeGen/Hexagon/addr-calc-opt.ll vendored
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@@ -1,54 +0,0 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
;
; Test whether we can produce minimal code for this complex address
; calculation.
;
; CHECK: r0 = memub(r{{[0-9]+}}<<#3{{ *}}+{{ *}}##the_global+516)
%0 = type { [3 x %1] }
%1 = type { %2, i8, i8, i8, i8, i8, [4 x i8], i8, [10 x i8], [10 x i8], [10 x i8], i8, [3 x %4], i16, i16, i16, i16, i32, i8, [4 x i8], i8, i8, i8, i8, %5, i8, i8, i8, i8, i8, i16, i8, i8, i8, i16, i16, i8, i8, [2 x i8], [2 x i8], i8, i8, i8, i8, i8, i16, i16, i8, i8, i8, i8, i8, i8, %9, i8, [6 x [2 x i8]], i16, i32, %10, [28 x i8], [4 x %17] }
%2 = type { %3 }
%3 = type { i8, i8, i8, i8, i8, i16, i16, i16, i16, i16 }
%4 = type { i16, i16 }
%5 = type { [10 x %6] }
%6 = type { [2 x %7] }
%7 = type { i8, [2 x %8] }
%8 = type { [4 x i8] }
%9 = type { i8 }
%10 = type { %11, %13 }
%11 = type { [2 x [2 x i8]], [2 x [8 x %12]], [6 x i16], [6 x i16] }
%12 = type { i8, i8 }
%13 = type { [4 x %12], [4 x %12], [2 x [4 x %14]], [6 x i16] }
%14 = type { %15, %16 }
%15 = type { i8, i8 }
%16 = type { i8, i8 }
%17 = type { i8, i8, %1*, i16, i16, i16, i64, i32, i32, %18, i8, %21, i8, [2 x i16], i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i16, i16, i16, i8, i8, i8, i16, i16, [2 x i16], i16, [2 x i32], [2 x i16], [2 x i16], i8, i8, [6 x %23], i8, i8, i8, %24, %25, %26, %28 }
%18 = type { %19, [10 x %20] }
%19 = type { i32 }
%20 = type { [2 x i8], [2 x i8], i8, i8, i8, i8 }
%21 = type { i8, i8, i8, [8 x %22] }
%22 = type { i8, i8, i8, i32 }
%23 = type { i32, i16, i16, [2 x i16], [2 x i16], [2 x i16], i32 }
%24 = type { [2 x i32], [2 x i64*], [2 x i64*], [2 x i64*], [2 x i32], [2 x i32], i32 }
%25 = type { [2 x i32], [2 x i32], [2 x i32] }
%26 = type { i8, i8, i8, i16, i16, %27, i32, i32, i32, i16 }
%27 = type { i64 }
%28 = type { %29, %31, [24 x i8] }
%29 = type { [2 x %30], [16 x i32] }
%30 = type { [16 x i32], [8 x i32], [16 x i32], [64 x i32], [2 x i32], i64, i32, i32, i32, i32 }
%31 = type { [2 x %32] }
%32 = type { [4 x %33], i32 }
%33 = type { i32, i32 }
@the_global = external global %0
; Function Attrs: nounwind optsize readonly ssp
define zeroext i8 @myFun(i8 zeroext, i8 zeroext) {
%3 = zext i8 %1 to i32
%4 = zext i8 %0 to i32
%5 = getelementptr inbounds %0, %0* @the_global, i32 0, i32 0, i32 %4, i32 60, i32 0, i32 9, i32 1, i32 %3, i32 0, i32 0
%6 = load i8, i8* %5, align 4
ret i8 %6
}

25
external/llvm/test/CodeGen/Hexagon/addrmode-globoff.mir vendored
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@@ -1,25 +0,0 @@
# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s
--- |
@g0 = external global [16 x i16], align 8
define void @foo() {
ret void
}
...
---
name: foo
tracksRegLiveness: true
body: |
bb.0:
liveins: %r0
; Make sure that the offset in @g0 is 8.
; CHECK: S4_storerh_ur killed %r0, 2, @g0 + 8, %r0
%r1 = A2_tfrsi @g0+4
%r2 = S2_addasl_rrri %r1, %r0, 2
S2_storerh_io %r2, 4, %r0
...

92
external/llvm/test/CodeGen/Hexagon/addrmode-indoff.ll vendored
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@@ -1,92 +0,0 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
;
; Bug 6840. Use absolute+index addressing.
@ga = common global [1024 x i8] zeroinitializer, align 8
; CHECK-LABEL: test0
; CHECK: memub(r{{[0-9]+}}+##ga)
define zeroext i8 @test0(i32 %i) nounwind readonly {
entry:
%t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %i
%0 = load i8, i8* %t, align 1
ret i8 %0
}
; CHECK-LABEL: test1
; CHECK: memb(r{{[0-9]+}}+##ga)
define signext i8 @test1(i32 %i) nounwind readonly {
entry:
%t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %i
%0 = load i8, i8* %t, align 1
ret i8 %0
}
; CHECK-LABEL: test2
; CHECK: memub(r{{[0-9]+}}<<#1+##ga)
define zeroext i8 @test2(i32 %i) nounwind readonly {
entry:
%j = shl nsw i32 %i, 1
%t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
%0 = load i8, i8* %t, align 1
ret i8 %0
}
; CHECK-LABEL: test3
; CHECK: memb(r{{[0-9]+}}<<#1+##ga)
define signext i8 @test3(i32 %i) nounwind readonly {
entry:
%j = shl nsw i32 %i, 1
%t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
%0 = load i8, i8* %t, align 1
ret i8 %0
}
; CHECK-LABEL: test4
; CHECK: memub(r{{[0-9]+}}<<#2+##ga)
define zeroext i8 @test4(i32 %i) nounwind readonly {
entry:
%j = shl nsw i32 %i, 2
%t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
%0 = load i8, i8* %t, align 1
ret i8 %0
}
; CHECK-LABEL: test5
; CHECK: memb(r{{[0-9]+}}<<#2+##ga)
define signext i8 @test5(i32 %i) nounwind readonly {
entry:
%j = shl nsw i32 %i, 2
%t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
%0 = load i8, i8* %t, align 1
ret i8 %0
}
; CHECK-LABEL: test10
; CHECK: memb(r{{[0-9]+}}+##ga)
define void @test10(i32 %i, i8 zeroext %v) nounwind {
entry:
%t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %i
store i8 %v, i8* %t, align 1
ret void
}
; CHECK-LABEL: test11
; CHECK: memb(r{{[0-9]+}}<<#1+##ga)
define void @test11(i32 %i, i8 signext %v) nounwind {
entry:
%j = shl nsw i32 %i, 1
%t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
store i8 %v, i8* %t, align 1
ret void
}
; CHECK-LABEL: test12
; CHECK: memb(r{{[0-9]+}}<<#2+##ga)
define void @test12(i32 %i, i8 zeroext %v) nounwind {
entry:
%j = shl nsw i32 %i, 2
%t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
store i8 %v, i8* %t, align 1
ret void
}

30
external/llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir vendored
View File

@@ -1,30 +0,0 @@
# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s
# Check that the addasl is not propagated into the addressing mode.
# CHECK-NOT: L4_loadri_ur
--- |
@g = global i32 zeroinitializer
define void @fred() { ret void }
...
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
liveins: %p0
%r0 = A2_tfrsi @g
%r1 = A2_tfrsi 1
%r2 = S2_addasl_rrri %r0, %r1, 1
J2_jumpt %p0, %bb.2, implicit-def %pc
bb.1:
liveins: %r0, %r2
%r1 = A2_tfrsi 2
bb.2:
liveins: %r0, %r2
%r3 = L2_loadri_io %r2, 0
...

22
external/llvm/test/CodeGen/Hexagon/addrmode-rr-to-io.mir vendored
View File

@@ -1,22 +0,0 @@
# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s
# This testcase used to crash.
# CHECK: S2_storerb_io killed %r0, @var_i8, killed %r2
--- |
define void @fred() { ret void }
@var_i8 = global [10 x i8] zeroinitializer, align 8
...
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
liveins: %r0
%r1 = A2_tfrsi @var_i8
%r2 = A2_tfrsi 255
S4_storerb_rr killed %r0, killed %r1, 0, killed %r2
PS_jmpret %r31, implicit-def %pc
...

81
external/llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll vendored
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@@ -1,81 +0,0 @@
; RUN: llc -march=hexagon -disable-post-ra < %s | FileCheck %s
; Make sure that if there's only one store to the stack, it gets packetized
; with allocframe as there's a latency of 2 cycles between allocframe and
; the following store if not in the same packet.
; CHECK: {
; CHECK: memd(r29
; CHECK-NOT: {
; CHECK: allocframe
; CHECK: }
; CHECK: = memw(gp+#G)
%struct.0 = type { %struct.0*, i32, %struct.2 }
%struct.1 = type { i32, i32, [31 x i8] }
%struct.2 = type { %struct.1 }
@G = common global %struct.0* null, align 4
define i32 @test(%struct.0* nocapture %a0) #0 {
b1:
%v2 = alloca %struct.0*, align 4
%v3 = bitcast %struct.0** %v2 to i8*
%v4 = getelementptr inbounds %struct.0, %struct.0* %a0, i32 0, i32 0
%v5 = load %struct.0*, %struct.0** %v4, align 4
store %struct.0* %v5, %struct.0** %v2, align 4
%v6 = bitcast %struct.0* %v5 to i8*
%v7 = load i8*, i8** bitcast (%struct.0** @G to i8**), align 4
tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %v6, i8* %v7, i32 48, i32 4, i1 false)
%v8 = getelementptr inbounds %struct.0, %struct.0* %a0, i32 0, i32 2, i32 0, i32 1
store i32 5, i32* %v8, align 4
%v9 = getelementptr inbounds %struct.0, %struct.0* %v5, i32 0, i32 2, i32 0, i32 1
store i32 5, i32* %v9, align 4
%v10 = bitcast %struct.0* %a0 to i32*
%v11 = load i32, i32* %v10, align 4
%v12 = bitcast %struct.0* %v5 to i32*
store i32 %v11, i32* %v12, align 4
%v13 = call i32 bitcast (i32 (...)* @f0 to i32 (%struct.0**)*)(%struct.0** nonnull %v2)
%v14 = load %struct.0*, %struct.0** %v2, align 4
%v15 = getelementptr inbounds %struct.0, %struct.0* %v14, i32 0, i32 1
%v16 = load i32, i32* %v15, align 4
%v17 = icmp eq i32 %v16, 0
br i1 %v17, label %b18, label %b32
b18: ; preds = %b1
%v19 = bitcast %struct.0** %v2 to i32**
%v20 = getelementptr inbounds %struct.0, %struct.0* %v14, i32 0, i32 2, i32 0, i32 1
store i32 6, i32* %v20, align 4
%v21 = getelementptr inbounds %struct.0, %struct.0* %a0, i32 0, i32 2, i32 0, i32 0
%v22 = load i32, i32* %v21, align 4
%v23 = getelementptr inbounds %struct.0, %struct.0* %v14, i32 0, i32 2, i32 0, i32 0
%v24 = call i32 bitcast (i32 (...)* @f1 to i32 (i32, i32*)*)(i32 %v22, i32* %v23)
%v25 = load i32*, i32** bitcast (%struct.0** @G to i32**), align 4
%v26 = load i32, i32* %v25, align 4
%v27 = load i32*, i32** %v19, align 4
store i32 %v26, i32* %v27, align 4
%v28 = load %struct.0*, %struct.0** %v2, align 4
%v29 = getelementptr inbounds %struct.0, %struct.0* %v28, i32 0, i32 2, i32 0, i32 1
%v30 = load i32, i32* %v29, align 4
%v31 = call i32 bitcast (i32 (...)* @f2 to i32 (i32, i32, i32*)*)(i32 %v30, i32 10, i32* %v29)
br label %b36
b32: ; preds = %b1
%v33 = bitcast %struct.0* %a0 to i8**
%v34 = load i8*, i8** %v33, align 4
%v35 = bitcast %struct.0* %a0 to i8*
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %v35, i8* %v34, i32 48, i32 4, i1 false)
br label %b36
b36: ; preds = %b32, %b18
ret i32 undef
}
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i32, i1) #1
declare i32 @f0(...) #0
declare i32 @f1(...) #0
declare i32 @f2(...) #0
attributes #0 = { nounwind }
attributes #1 = { argmemonly nounwind }

599
external/llvm/test/CodeGen/Hexagon/alu64.ll vendored
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File diff suppressed because it is too large Load Diff

45
external/llvm/test/CodeGen/Hexagon/always-ext.ll vendored
View File

@@ -1,45 +0,0 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we don't generate an invalid packet with too many instructions
; due to a store that has a must-extend operand.
; CHECK: CuSuiteAdd.exit.us
; CHECK: {
; CHECK-NOT: call abort
; CHECK: memw(##0)
; CHECK: memw(r{{[0-9+]}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##4)
; CHECK: }
%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111 = type { i8*, void (%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*)*, i32, i32, i8*, [23 x i32]* }
%struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112 = type { i32, [1024 x %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*], i32 }
@__func__.CuSuiteAdd = external unnamed_addr constant [11 x i8], align 8
@.str24 = external unnamed_addr constant [140 x i8], align 8
declare void @_Assert()
define void @CuSuiteAddSuite() nounwind {
entry:
br i1 undef, label %for.body.us, label %for.end
for.body.us: ; preds = %entry
%0 = load %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*, %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** null, align 4
%1 = load i32, i32* undef, align 4
%cmp.i.us = icmp slt i32 %1, 1024
br i1 %cmp.i.us, label %CuSuiteAdd.exit.us, label %cond.false6.i.us
cond.false6.i.us: ; preds = %for.body.us
tail call void @_Assert() nounwind
unreachable
CuSuiteAdd.exit.us: ; preds = %for.body.us
%arrayidx.i.us = getelementptr inbounds %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112, %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112* null, i32 0, i32 1, i32 %1
store %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111* %0, %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** %arrayidx.i.us, align 4
call void @llvm.trap()
unreachable
for.end: ; preds = %entry
ret void
}
declare void @llvm.trap() noreturn nounwind

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