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Imported Upstream version 5.18.0.207
Former-commit-id: 3b152f462918d427ce18620a2cbe4f8b79650449
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external/llvm/test/CodeGen/AArch64/bics.ll
vendored
40
external/llvm/test/CodeGen/AArch64/bics.ll
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@ -1,40 +0,0 @@
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
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define i1 @andn_cmp(i32 %x, i32 %y) {
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; CHECK-LABEL: andn_cmp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bics wzr, w1, w0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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;
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%notx = xor i32 %x, -1
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%and = and i32 %notx, %y
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define i1 @and_cmp(i32 %x, i32 %y) {
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; CHECK-LABEL: and_cmp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bics wzr, w1, w0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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;
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%and = and i32 %x, %y
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%cmp = icmp eq i32 %and, %y
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ret i1 %cmp
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}
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define i1 @and_cmp_const(i32 %x) {
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; CHECK-LABEL: and_cmp_const:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43
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; CHECK-NEXT: bics wzr, w8, w0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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;
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%and = and i32 %x, 43
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%cmp = icmp eq i32 %and, 43
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ret i1 %cmp
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}
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