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external/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
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405
external/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
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//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the SPARC target.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcTargetMachine.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class SparcDAGToDAGISel : public SelectionDAGISel {
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/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const SparcSubtarget *Subtarget;
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public:
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explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void Select(SDNode *N) override;
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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StringRef getPassName() const override {
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return "SPARC DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "SparcGenDAGISel.inc"
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private:
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SDNode* getGlobalBaseReg();
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bool tryInlineAsm(SDNode *N);
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};
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} // end anonymous namespace
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SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
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return CurDAG->getRegister(GlobalBaseReg,
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TLI->getPointerTy(CurDAG->getDataLayout()))
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.getNode();
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}
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bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
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SDValue &Base, SDValue &Offset) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(
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FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (isInt<13>(CN->getSExtValue())) {
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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// Constant offset from frame ref.
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Base = CurDAG->getTargetFrameIndex(
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FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
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} else {
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Base = Addr.getOperand(0);
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}
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
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MVT::i32);
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return true;
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}
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}
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
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Base = Addr.getOperand(1);
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (isInt<13>(CN->getSExtValue()))
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return false; // Let the reg+imm pattern catch this!
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
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Addr.getOperand(1).getOpcode() == SPISD::Lo)
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return false; // Let the reg+imm pattern catch this!
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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return true;
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}
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R1 = Addr;
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R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout()));
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return true;
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}
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// Re-assemble i64 arguments split up in SelectionDAGBuilder's
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// visitInlineAsm / GetRegistersForValue functions.
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//
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// Note: This function was copied from, and is essentially identical
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// to ARMISelDAGToDAG::SelectInlineAsm. It is very unfortunate that
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// such hacking-up is necessary; a rethink of how inline asm operands
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// are handled may be in order to make doing this more sane.
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//
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// TODO: fix inline asm support so I can simply tell it that 'i64'
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// inputs to asm need to be allocated to the IntPair register type,
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// and have that work. Then, delete this function.
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bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
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std::vector<SDValue> AsmNodeOperands;
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unsigned Flag, Kind;
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bool Changed = false;
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unsigned NumOps = N->getNumOperands();
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// Normally, i64 data is bounded to two arbitrary GPRs for "%r"
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// constraint. However, some instructions (e.g. ldd/std) require
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// (even/even+1) GPRs.
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// So, here, we check for this case, and mutate the inlineasm to use
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// a single IntPair register instead, which guarantees such even/odd
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// placement.
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SDLoc dl(N);
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SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
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: SDValue(nullptr,0);
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SmallVector<bool, 8> OpChanged;
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// Glue node will be appended late.
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for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
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SDValue op = N->getOperand(i);
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AsmNodeOperands.push_back(op);
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if (i < InlineAsm::Op_FirstOperand)
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continue;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
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Flag = C->getZExtValue();
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Kind = InlineAsm::getKind(Flag);
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}
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else
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continue;
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// Immediate operands to inline asm in the SelectionDAG are modeled with
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// two operands. The first is a constant of value InlineAsm::Kind_Imm, and
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// the second is a constant with the value of the immediate. If we get here
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// and we have a Kind_Imm, skip the next operand, and continue.
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if (Kind == InlineAsm::Kind_Imm) {
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SDValue op = N->getOperand(++i);
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AsmNodeOperands.push_back(op);
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continue;
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}
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unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
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if (NumRegs)
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OpChanged.push_back(false);
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unsigned DefIdx = 0;
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bool IsTiedToChangedOp = false;
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// If it's a use that is tied with a previous def, it has no
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// reg class constraint.
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if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
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IsTiedToChangedOp = OpChanged[DefIdx];
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if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
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&& Kind != InlineAsm::Kind_RegDefEarlyClobber)
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continue;
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unsigned RC;
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bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
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if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
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|| NumRegs != 2)
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continue;
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assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
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SDValue V0 = N->getOperand(i+1);
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SDValue V1 = N->getOperand(i+2);
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unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
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unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
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SDValue PairedReg;
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MachineRegisterInfo &MRI = MF->getRegInfo();
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if (Kind == InlineAsm::Kind_RegDef ||
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Kind == InlineAsm::Kind_RegDefEarlyClobber) {
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// Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
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// the original GPRs.
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unsigned GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
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PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
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SDValue Chain = SDValue(N,0);
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SDNode *GU = N->getGluedUser();
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SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32,
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Chain.getValue(1));
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// Extract values from a GPRPair reg and copy to the original GPR reg.
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SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32,
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RegCopy);
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SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32,
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RegCopy);
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SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
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RegCopy.getValue(1));
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SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
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// Update the original glue user.
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std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
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Ops.push_back(T1.getValue(1));
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CurDAG->UpdateNodeOperands(GU, Ops);
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}
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else {
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// For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
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// GPRPair and then pass the GPRPair to the inline asm.
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SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
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// As REG_SEQ doesn't take RegisterSDNode, we copy them first.
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SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
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Chain.getValue(1));
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SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
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T0.getValue(1));
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SDValue Pair = SDValue(
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CurDAG->getMachineNode(
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TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32,
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{
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CurDAG->getTargetConstant(SP::IntPairRegClassID, dl,
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MVT::i32),
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T0,
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CurDAG->getTargetConstant(SP::sub_even, dl, MVT::i32),
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T1,
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CurDAG->getTargetConstant(SP::sub_odd, dl, MVT::i32),
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}),
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0);
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// Copy REG_SEQ into a GPRPair-typed VR and replace the original two
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// i32 VRs of inline asm with it.
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unsigned GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
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PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
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Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
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AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
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Glue = Chain.getValue(1);
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}
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Changed = true;
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if(PairedReg.getNode()) {
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OpChanged[OpChanged.size() -1 ] = true;
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Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
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if (IsTiedToChangedOp)
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Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
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else
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Flag = InlineAsm::getFlagWordForRegClass(Flag, SP::IntPairRegClassID);
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// Replace the current flag.
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AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
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Flag, dl, MVT::i32);
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// Add the new register node and skip the original two GPRs.
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AsmNodeOperands.push_back(PairedReg);
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// Skip the next two GPRs.
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i += 2;
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}
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}
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if (Glue.getNode())
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AsmNodeOperands.push_back(Glue);
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if (!Changed)
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return false;
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SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
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CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
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New->setNodeId(-1);
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ReplaceNode(N, New.getNode());
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return true;
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}
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void SparcDAGToDAGISel::Select(SDNode *N) {
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SDLoc dl(N);
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if (N->isMachineOpcode()) {
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N->setNodeId(-1);
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return; // Already selected.
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}
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switch (N->getOpcode()) {
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default: break;
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case ISD::INLINEASM: {
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if (tryInlineAsm(N))
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return;
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break;
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}
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case SPISD::GLOBAL_BASE_REG:
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ReplaceNode(N, getGlobalBaseReg());
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return;
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case ISD::SDIV:
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case ISD::UDIV: {
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// sdivx / udivx handle 64-bit divides.
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if (N->getValueType(0) == MVT::i64)
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break;
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// FIXME: should use a custom expander to expose the SRA to the dag.
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SDValue DivLHS = N->getOperand(0);
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SDValue DivRHS = N->getOperand(1);
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// Set the Y register to the high-part.
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SDValue TopPart;
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if (N->getOpcode() == ISD::SDIV) {
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TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
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CurDAG->getTargetConstant(31, dl, MVT::i32)),
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0);
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} else {
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TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
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}
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TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SP::Y, TopPart,
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SDValue())
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.getValue(1);
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// FIXME: Handle div by immediate.
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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// SDIV is a hardware erratum on some LEON2 processors. Replace it with SDIVcc here.
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if (((SparcTargetMachine&)TM).getSubtargetImpl()->performSDIVReplace()
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&&
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Opcode == SP::SDIVrr) {
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Opcode = SP::SDIVCCrr;
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}
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CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
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return;
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}
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}
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SelectCode(N);
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool
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SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1;
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switch (ConstraintID) {
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default: return true;
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_o:
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case InlineAsm::Constraint_m: // memory
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if (!SelectADDRrr(Op, Op0, Op1))
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SelectADDRri(Op, Op0, Op1);
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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/// createSparcISelDag - This pass converts a legalized DAG into a
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/// SPARC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
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return new SparcDAGToDAGISel(TM);
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}
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