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external/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
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449
external/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
vendored
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//===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format SPARC assembly language.
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//
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//===----------------------------------------------------------------------===//
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#include "InstPrinter/SparcInstPrinter.h"
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#include "MCTargetDesc/SparcMCExpr.h"
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#include "Sparc.h"
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#include "SparcInstrInfo.h"
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#include "SparcTargetMachine.h"
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#include "SparcTargetStreamer.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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namespace {
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class SparcAsmPrinter : public AsmPrinter {
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SparcTargetStreamer &getTargetStreamer() {
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return static_cast<SparcTargetStreamer &>(
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*OutStreamer->getTargetStreamer());
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}
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public:
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explicit SparcAsmPrinter(TargetMachine &TM,
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std::unique_ptr<MCStreamer> Streamer)
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: AsmPrinter(TM, std::move(Streamer)) {}
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StringRef getPassName() const override { return "Sparc Assembly Printer"; }
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void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
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void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
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const char *Modifier = nullptr);
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void EmitFunctionBodyStart() override;
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void EmitInstruction(const MachineInstr *MI) override;
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static const char *getRegisterName(unsigned RegNo) {
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return SparcInstPrinter::getRegisterName(RegNo);
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}
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O) override;
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O) override;
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void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
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const MCSubtargetInfo &STI);
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};
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} // end of anonymous namespace
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static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind,
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MCSymbol *Sym, MCContext &OutContext) {
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const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Sym,
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OutContext);
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const SparcMCExpr *expr = SparcMCExpr::create(Kind, MCSym, OutContext);
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return MCOperand::createExpr(expr);
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}
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static MCOperand createPCXCallOP(MCSymbol *Label,
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MCContext &OutContext) {
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return createSparcMCOperand(SparcMCExpr::VK_Sparc_None, Label, OutContext);
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}
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static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
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MCSymbol *GOTLabel, MCSymbol *StartLabel,
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MCSymbol *CurLabel,
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MCContext &OutContext)
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{
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const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext);
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const MCSymbolRefExpr *Start = MCSymbolRefExpr::create(StartLabel,
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OutContext);
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const MCSymbolRefExpr *Cur = MCSymbolRefExpr::create(CurLabel,
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OutContext);
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const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Cur, Start, OutContext);
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const MCBinaryExpr *Add = MCBinaryExpr::createAdd(GOT, Sub, OutContext);
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const SparcMCExpr *expr = SparcMCExpr::create(Kind,
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Add, OutContext);
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return MCOperand::createExpr(expr);
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}
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static void EmitCall(MCStreamer &OutStreamer,
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MCOperand &Callee,
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const MCSubtargetInfo &STI)
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{
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MCInst CallInst;
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CallInst.setOpcode(SP::CALL);
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CallInst.addOperand(Callee);
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OutStreamer.EmitInstruction(CallInst, STI);
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}
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static void EmitSETHI(MCStreamer &OutStreamer,
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MCOperand &Imm, MCOperand &RD,
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const MCSubtargetInfo &STI)
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{
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MCInst SETHIInst;
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SETHIInst.setOpcode(SP::SETHIi);
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SETHIInst.addOperand(RD);
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SETHIInst.addOperand(Imm);
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OutStreamer.EmitInstruction(SETHIInst, STI);
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}
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static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
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MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
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const MCSubtargetInfo &STI)
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{
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MCInst Inst;
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Inst.setOpcode(Opcode);
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Inst.addOperand(RD);
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Inst.addOperand(RS1);
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Inst.addOperand(Src2);
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OutStreamer.EmitInstruction(Inst, STI);
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}
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static void EmitOR(MCStreamer &OutStreamer,
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MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
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const MCSubtargetInfo &STI) {
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EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
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}
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static void EmitADD(MCStreamer &OutStreamer,
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MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
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const MCSubtargetInfo &STI) {
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EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
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}
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static void EmitSHL(MCStreamer &OutStreamer,
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MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
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const MCSubtargetInfo &STI) {
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EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI);
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}
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static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
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SparcMCExpr::VariantKind HiKind,
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SparcMCExpr::VariantKind LoKind,
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MCOperand &RD,
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MCContext &OutContext,
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const MCSubtargetInfo &STI) {
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MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext);
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MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext);
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EmitSETHI(OutStreamer, hi, RD, STI);
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EmitOR(OutStreamer, RD, lo, RD, STI);
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}
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void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
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const MCSubtargetInfo &STI)
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{
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MCSymbol *GOTLabel =
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OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
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const MachineOperand &MO = MI->getOperand(0);
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assert(MO.getReg() != SP::O7 &&
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"%o7 is assigned as destination for getpcx!");
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MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
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if (!isPositionIndependent()) {
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// Just load the address of GOT to MCRegOP.
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switch(TM.getCodeModel()) {
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default:
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llvm_unreachable("Unsupported absolute code model");
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case CodeModel::Small:
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EmitHiLo(*OutStreamer, GOTLabel,
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SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
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MCRegOP, OutContext, STI);
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break;
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case CodeModel::Medium: {
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EmitHiLo(*OutStreamer, GOTLabel,
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SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44,
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MCRegOP, OutContext, STI);
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MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(12,
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OutContext));
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EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
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MCOperand lo = createSparcMCOperand(SparcMCExpr::VK_Sparc_L44,
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GOTLabel, OutContext);
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EmitOR(*OutStreamer, MCRegOP, lo, MCRegOP, STI);
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break;
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}
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case CodeModel::Large: {
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EmitHiLo(*OutStreamer, GOTLabel,
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SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM,
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MCRegOP, OutContext, STI);
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MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(32,
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OutContext));
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EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
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// Use register %o7 to load the lower 32 bits.
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MCOperand RegO7 = MCOperand::createReg(SP::O7);
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EmitHiLo(*OutStreamer, GOTLabel,
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SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
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RegO7, OutContext, STI);
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EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
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}
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}
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return;
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}
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MCSymbol *StartLabel = OutContext.createTempSymbol();
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MCSymbol *EndLabel = OutContext.createTempSymbol();
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MCSymbol *SethiLabel = OutContext.createTempSymbol();
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MCOperand RegO7 = MCOperand::createReg(SP::O7);
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// <StartLabel>:
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// call <EndLabel>
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// <SethiLabel>:
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// sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
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// <EndLabel>:
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// or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
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// add <MO>, %o7, <MO>
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OutStreamer->EmitLabel(StartLabel);
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MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
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EmitCall(*OutStreamer, Callee, STI);
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OutStreamer->EmitLabel(SethiLabel);
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MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22,
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GOTLabel, StartLabel, SethiLabel,
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OutContext);
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EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI);
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OutStreamer->EmitLabel(EndLabel);
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MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC10,
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GOTLabel, StartLabel, EndLabel,
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OutContext);
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EmitOR(*OutStreamer, MCRegOP, loImm, MCRegOP, STI);
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EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
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}
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void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
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{
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switch (MI->getOpcode()) {
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default: break;
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case TargetOpcode::DBG_VALUE:
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// FIXME: Debug Value.
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return;
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case SP::GETPCX:
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LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
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return;
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}
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MachineBasicBlock::const_instr_iterator I = MI->getIterator();
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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MCInst TmpInst;
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LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this);
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EmitToStreamer(*OutStreamer, TmpInst);
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} while ((++I != E) && I->isInsideBundle()); // Delay slot check.
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}
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void SparcAsmPrinter::EmitFunctionBodyStart() {
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if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
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return;
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
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for (unsigned i = 0; globalRegs[i] != 0; ++i) {
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unsigned reg = globalRegs[i];
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if (MRI.use_empty(reg))
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continue;
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if (reg == SP::G6 || reg == SP::G7)
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getTargetStreamer().emitSparcRegisterIgnore(reg);
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else
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getTargetStreamer().emitSparcRegisterScratch(reg);
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}
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}
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void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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raw_ostream &O) {
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const DataLayout &DL = getDataLayout();
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const MachineOperand &MO = MI->getOperand (opNum);
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SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags();
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#ifndef NDEBUG
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// Verify the target flags.
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if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
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if (MI->getOpcode() == SP::CALL)
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assert(TF == SparcMCExpr::VK_Sparc_None &&
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"Cannot handle target flags on call address");
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else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
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assert((TF == SparcMCExpr::VK_Sparc_HI
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|| TF == SparcMCExpr::VK_Sparc_H44
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|| TF == SparcMCExpr::VK_Sparc_HH
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|| TF == SparcMCExpr::VK_Sparc_TLS_GD_HI22
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|| TF == SparcMCExpr::VK_Sparc_TLS_LDM_HI22
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|| TF == SparcMCExpr::VK_Sparc_TLS_LDO_HIX22
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|| TF == SparcMCExpr::VK_Sparc_TLS_IE_HI22
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|| TF == SparcMCExpr::VK_Sparc_TLS_LE_HIX22) &&
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"Invalid target flags for address operand on sethi");
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else if (MI->getOpcode() == SP::TLS_CALL)
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assert((TF == SparcMCExpr::VK_Sparc_None
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|| TF == SparcMCExpr::VK_Sparc_TLS_GD_CALL
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|| TF == SparcMCExpr::VK_Sparc_TLS_LDM_CALL) &&
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"Cannot handle target flags on tls call address");
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else if (MI->getOpcode() == SP::TLS_ADDrr)
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assert((TF == SparcMCExpr::VK_Sparc_TLS_GD_ADD
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|| TF == SparcMCExpr::VK_Sparc_TLS_LDM_ADD
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|| TF == SparcMCExpr::VK_Sparc_TLS_LDO_ADD
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|| TF == SparcMCExpr::VK_Sparc_TLS_IE_ADD) &&
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"Cannot handle target flags on add for TLS");
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else if (MI->getOpcode() == SP::TLS_LDrr)
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assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LD &&
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"Cannot handle target flags on ld for TLS");
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else if (MI->getOpcode() == SP::TLS_LDXrr)
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assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LDX &&
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"Cannot handle target flags on ldx for TLS");
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else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
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assert((TF == SparcMCExpr::VK_Sparc_TLS_LDO_LOX10
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|| TF == SparcMCExpr::VK_Sparc_TLS_LE_LOX10) &&
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"Cannot handle target flags on xor for TLS");
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else
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assert((TF == SparcMCExpr::VK_Sparc_LO
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|| TF == SparcMCExpr::VK_Sparc_M44
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|| TF == SparcMCExpr::VK_Sparc_L44
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|| TF == SparcMCExpr::VK_Sparc_HM
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|| TF == SparcMCExpr::VK_Sparc_TLS_GD_LO10
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|| TF == SparcMCExpr::VK_Sparc_TLS_LDM_LO10
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|| TF == SparcMCExpr::VK_Sparc_TLS_IE_LO10 ) &&
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"Invalid target flags for small address operand");
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}
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#endif
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bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
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break;
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case MachineOperand::MO_Immediate:
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O << (int)MO.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MO.getMBB()->getSymbol()->print(O, MAI);
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return;
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case MachineOperand::MO_GlobalAddress:
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getSymbol(MO.getGlobal())->print(O, MAI);
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break;
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case MachineOperand::MO_BlockAddress:
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O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
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break;
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case MachineOperand::MO_ExternalSymbol:
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O << MO.getSymbolName();
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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O << DL.getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
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<< MO.getIndex();
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break;
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case MachineOperand::MO_Metadata:
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MO.getMetadata()->printAsOperand(O, MMI->getModule());
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break;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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if (CloseParen) O << ")";
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}
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void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
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raw_ostream &O, const char *Modifier) {
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printOperand(MI, opNum, O);
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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O << ", ";
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printOperand(MI, opNum+1, O);
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return;
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}
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if (MI->getOperand(opNum+1).isReg() &&
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MI->getOperand(opNum+1).getReg() == SP::G0)
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return; // don't print "+%g0"
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if (MI->getOperand(opNum+1).isImm() &&
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MI->getOperand(opNum+1).getImm() == 0)
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return; // don't print "+0"
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O << "+";
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printOperand(MI, opNum+1, O);
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}
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/// PrintAsmOperand - Print out an operand for an inline asm expression.
|
||||
///
|
||||
bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
|
||||
unsigned AsmVariant,
|
||||
const char *ExtraCode,
|
||||
raw_ostream &O) {
|
||||
if (ExtraCode && ExtraCode[0]) {
|
||||
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
||||
|
||||
switch (ExtraCode[0]) {
|
||||
default:
|
||||
// See if this is a generic print operand
|
||||
return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
|
||||
case 'f':
|
||||
case 'r':
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
printOperand(MI, OpNo, O);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
||||
unsigned OpNo, unsigned AsmVariant,
|
||||
const char *ExtraCode,
|
||||
raw_ostream &O) {
|
||||
if (ExtraCode && ExtraCode[0])
|
||||
return true; // Unknown modifier
|
||||
|
||||
O << '[';
|
||||
printMemOperand(MI, OpNo, O);
|
||||
O << ']';
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Force static initialization.
|
||||
extern "C" void LLVMInitializeSparcAsmPrinter() {
|
||||
RegisterAsmPrinter<SparcAsmPrinter> X(getTheSparcTarget());
|
||||
RegisterAsmPrinter<SparcAsmPrinter> Y(getTheSparcV9Target());
|
||||
RegisterAsmPrinter<SparcAsmPrinter> Z(getTheSparcelTarget());
|
||||
}
|
||||
Reference in New Issue
Block a user