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external/llvm/lib/Target/ARM/ARMSubtarget.cpp
vendored
395
external/llvm/lib/Target/ARM/ARMSubtarget.cpp
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//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARM specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMCallLowering.h"
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#include "ARMLegalizerInfo.h"
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#include "ARMRegisterBankInfo.h"
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#include "ARMSubtarget.h"
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#include "ARMFrameLowering.h"
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#include "ARMInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "ARMTargetMachine.h"
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#include "MCTargetDesc/ARMMCTargetDesc.h"
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#include "Thumb1FrameLowering.h"
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#include "Thumb1InstrInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetParser.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "arm-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "ARMGenSubtargetInfo.inc"
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static cl::opt<bool>
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UseFusedMulOps("arm-use-mulops",
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cl::init(true), cl::Hidden);
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enum ITMode {
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DefaultIT,
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RestrictedIT,
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NoRestrictedIT
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};
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static cl::opt<ITMode>
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IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
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cl::ZeroOrMore,
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cl::values(clEnumValN(DefaultIT, "arm-default-it",
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"Generate IT block based on arch"),
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clEnumValN(RestrictedIT, "arm-restrict-it",
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"Disallow deprecated IT based on ARMv8"),
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clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
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"Allow IT blocks based on ARMv7")));
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/// ForceFastISel - Use the fast-isel, even for subtargets where it is not
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/// currently supported (for testing only).
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static cl::opt<bool>
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ForceFastISel("arm-force-fast-isel",
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cl::init(false), cl::Hidden);
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/// initializeSubtargetDependencies - Initializes using a CPU and feature string
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/// so that we can use initializer lists for subtarget initialization.
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ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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initializeEnvironment();
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initSubtargetFeatures(CPU, FS);
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return *this;
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}
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ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
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StringRef FS) {
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ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
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if (STI.isThumb1Only())
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return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
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return new ARMFrameLowering(STI);
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}
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ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS,
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const ARMBaseTargetMachine &TM, bool IsLittle)
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: ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
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CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
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TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
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// At this point initializeSubtargetDependencies has been called so
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// we can query directly.
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InstrInfo(isThumb1Only()
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? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
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: !isThumb()
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? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
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: (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
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TLInfo(TM, *this) {
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CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
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Legalizer.reset(new ARMLegalizerInfo(*this));
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auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
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// FIXME: At this point, we can't rely on Subtarget having RBI.
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// It's awkward to mix passing RBI and the Subtarget; should we pass
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// TII/TRI as well?
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InstSelector.reset(createARMInstructionSelector(
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*static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
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RegBankInfo.reset(RBI);
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}
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const CallLowering *ARMSubtarget::getCallLowering() const {
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return CallLoweringInfo.get();
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}
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const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
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return InstSelector.get();
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}
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const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
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return Legalizer.get();
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}
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const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
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return RegBankInfo.get();
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}
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bool ARMSubtarget::isXRaySupported() const {
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// We don't currently suppport Thumb, but Windows requires Thumb.
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return hasV6Ops() && hasARMOps() && !isTargetWindows();
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}
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void ARMSubtarget::initializeEnvironment() {
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// MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
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// directly from it, but we can try to make sure they're consistent when both
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// available.
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UseSjLjEH = (isTargetDarwin() && !isTargetWatchABI() &&
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Options.ExceptionModel == ExceptionHandling::None) ||
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Options.ExceptionModel == ExceptionHandling::SjLj;
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assert((!TM.getMCAsmInfo() ||
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(TM.getMCAsmInfo()->getExceptionHandlingType() ==
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ExceptionHandling::SjLj) == UseSjLjEH) &&
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"inconsistent sjlj choice between CodeGen and MC");
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}
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void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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if (CPUString.empty()) {
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CPUString = "generic";
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if (isTargetDarwin()) {
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StringRef ArchName = TargetTriple.getArchName();
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ARM::ArchKind AK = ARM::parseArch(ArchName);
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if (AK == ARM::ArchKind::ARMV7S)
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// Default to the Swift CPU when targeting armv7s/thumbv7s.
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CPUString = "swift";
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else if (AK == ARM::ArchKind::ARMV7K)
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// Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
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// ARMv7k does not use SjLj exception handling.
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CPUString = "cortex-a7";
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}
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}
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// Insert the architecture feature derived from the target triple into the
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// feature string. This is important for setting features that are implied
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// based on the architecture version.
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std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = (Twine(ArchFS) + "," + FS).str();
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else
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ArchFS = FS;
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}
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ParseSubtargetFeatures(CPUString, ArchFS);
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// FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
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// Assert this for now to make the change obvious.
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assert(hasV6T2Ops() || !hasThumb2());
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// Execute only support requires movt support
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if (genExecuteOnly())
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assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
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// Keep a pointer to static instruction cost data for the specified CPU.
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SchedModel = getSchedModelForCPU(CPUString);
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUString);
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// FIXME: this is invalid for WindowsCE
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if (isTargetWindows())
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NoARM = true;
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if (isAAPCS_ABI())
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stackAlignment = 8;
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if (isTargetNaCl() || isAAPCS16_ABI())
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stackAlignment = 16;
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// FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
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// emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
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// the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
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// support in the assembler and linker to be used. This would need to be
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// fixed to fully support tail calls in Thumb1.
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//
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// For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
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// baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
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// means if we need to reload LR, it takes extra instructions, which outweighs
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// the value of the tail call; but here we don't know yet whether LR is going
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// to be used. We take the optimistic approach of generating the tail call and
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// perhaps taking a hit if we need to restore the LR.
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// Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
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// but we need to make sure there are enough registers; the only valid
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// registers are the 4 used for parameters. We don't currently do this
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// case.
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SupportsTailCall = !isThumb() || hasV8MBaselineOps();
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if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
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SupportsTailCall = false;
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switch (IT) {
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case DefaultIT:
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RestrictIT = hasV8Ops();
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break;
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case RestrictedIT:
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RestrictIT = true;
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break;
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case NoRestrictedIT:
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RestrictIT = false;
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break;
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}
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// NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
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const FeatureBitset &Bits = getFeatureBits();
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if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
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(Options.UnsafeFPMath || isTargetDarwin()))
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UseNEONForSinglePrecisionFP = true;
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if (isRWPI())
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ReserveR9 = true;
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// FIXME: Teach TableGen to deal with these instead of doing it manually here.
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switch (ARMProcFamily) {
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case Others:
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case CortexA5:
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break;
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case CortexA7:
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LdStMultipleTiming = DoubleIssue;
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break;
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case CortexA8:
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LdStMultipleTiming = DoubleIssue;
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break;
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case CortexA9:
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LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
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PreISelOperandLatencyAdjustment = 1;
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break;
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case CortexA12:
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break;
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case CortexA15:
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MaxInterleaveFactor = 2;
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PreISelOperandLatencyAdjustment = 1;
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PartialUpdateClearance = 12;
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break;
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case CortexA17:
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case CortexA32:
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case CortexA35:
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case CortexA53:
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case CortexA55:
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case CortexA57:
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case CortexA72:
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case CortexA73:
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case CortexA75:
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case CortexR4:
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case CortexR4F:
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case CortexR5:
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case CortexR7:
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case CortexM3:
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case CortexR52:
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case ExynosM1:
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case Kryo:
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break;
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case Krait:
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PreISelOperandLatencyAdjustment = 1;
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break;
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case Swift:
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MaxInterleaveFactor = 2;
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LdStMultipleTiming = SingleIssuePlusExtras;
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PreISelOperandLatencyAdjustment = 1;
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PartialUpdateClearance = 12;
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break;
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}
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}
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bool ARMSubtarget::isAPCS_ABI() const {
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assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
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return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
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}
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bool ARMSubtarget::isAAPCS_ABI() const {
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assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
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return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
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TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
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}
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bool ARMSubtarget::isAAPCS16_ABI() const {
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assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
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return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
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}
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bool ARMSubtarget::isROPI() const {
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return TM.getRelocationModel() == Reloc::ROPI ||
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TM.getRelocationModel() == Reloc::ROPI_RWPI;
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}
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bool ARMSubtarget::isRWPI() const {
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return TM.getRelocationModel() == Reloc::RWPI ||
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TM.getRelocationModel() == Reloc::ROPI_RWPI;
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}
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bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
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if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
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return true;
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// 32 bit macho has no relocation for a-b if a is undefined, even if b is in
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// the section that is being relocated. This means we have to use o load even
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// for GVs that are known to be local to the dso.
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if (isTargetMachO() && TM.isPositionIndependent() &&
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(GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
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return true;
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return false;
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}
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bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
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return isTargetELF() && TM.isPositionIndependent() &&
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!TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
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}
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unsigned ARMSubtarget::getMispredictionPenalty() const {
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return SchedModel.MispredictPenalty;
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}
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bool ARMSubtarget::enableMachineScheduler() const {
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// Enable the MachineScheduler before register allocation for subtargets
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// with the use-misched feature.
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return useMachineScheduler();
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}
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// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
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bool ARMSubtarget::enablePostRAScheduler() const {
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if (disablePostRAScheduler())
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return false;
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// Don't reschedule potential IT blocks.
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return !isThumb1Only();
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}
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bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
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bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
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// For general targets, the prologue can grow when VFPs are allocated with
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// stride 4 (more vpush instructions). But WatchOS uses a compact unwind
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// format which it's more important to get right.
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return isTargetWatchABI() || (isSwift() && !MF.getFunction().optForMinSize());
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}
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bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
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// NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
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// immediates as it is inherently position independent, and may be out of
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// range otherwise.
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return !NoMovt && hasV8MBaselineOps() &&
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(isTargetWindows() || !MF.getFunction().optForMinSize() || genExecuteOnly());
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}
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bool ARMSubtarget::useFastISel() const {
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// Enable fast-isel for any target, for testing only.
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if (ForceFastISel)
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return true;
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// Limit fast-isel to the targets that are or have been tested.
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if (!hasV6Ops())
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return false;
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// Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
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return TM.Options.EnableFastISel &&
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((isTargetMachO() && !isThumb1Only()) ||
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(isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
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}
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