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//===-- R600MachineScheduler.cpp - R600 Scheduler Interface -*- C++ -*-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 Machine Scheduler interface
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//
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//===----------------------------------------------------------------------===//
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#include "R600MachineScheduler.h"
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#include "AMDGPUSubtarget.h"
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#include "R600InstrInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "machine-scheduler"
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void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
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assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness");
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DAG = static_cast<ScheduleDAGMILive*>(dag);
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const R600Subtarget &ST = DAG->MF.getSubtarget<R600Subtarget>();
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TII = static_cast<const R600InstrInfo*>(DAG->TII);
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TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
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VLIW5 = !ST.hasCaymanISA();
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MRI = &DAG->MRI;
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CurInstKind = IDOther;
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CurEmitted = 0;
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OccupedSlotsMask = 31;
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InstKindLimit[IDAlu] = TII->getMaxAlusPerClause();
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InstKindLimit[IDOther] = 32;
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InstKindLimit[IDFetch] = ST.getTexVTXClauseSize();
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AluInstCount = 0;
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FetchInstCount = 0;
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}
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void R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc,
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std::vector<SUnit *> &QDst)
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{
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QDst.insert(QDst.end(), QSrc.begin(), QSrc.end());
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QSrc.clear();
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}
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static unsigned getWFCountLimitedByGPR(unsigned GPRCount) {
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assert (GPRCount && "GPRCount cannot be 0");
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return 248 / GPRCount;
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}
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SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
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SUnit *SU = nullptr;
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NextInstKind = IDOther;
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IsTopNode = false;
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// check if we might want to switch current clause type
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bool AllowSwitchToAlu = (CurEmitted >= InstKindLimit[CurInstKind]) ||
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(Available[CurInstKind].empty());
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bool AllowSwitchFromAlu = (CurEmitted >= InstKindLimit[CurInstKind]) &&
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(!Available[IDFetch].empty() || !Available[IDOther].empty());
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if (CurInstKind == IDAlu && !Available[IDFetch].empty()) {
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// We use the heuristic provided by AMD Accelerated Parallel Processing
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// OpenCL Programming Guide :
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// The approx. number of WF that allows TEX inst to hide ALU inst is :
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// 500 (cycles for TEX) / (AluFetchRatio * 8 (cycles for ALU))
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float ALUFetchRationEstimate =
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(AluInstCount + AvailablesAluCount() + Pending[IDAlu].size()) /
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(FetchInstCount + Available[IDFetch].size());
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if (ALUFetchRationEstimate == 0) {
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AllowSwitchFromAlu = true;
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} else {
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unsigned NeededWF = 62.5f / ALUFetchRationEstimate;
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DEBUG( dbgs() << NeededWF << " approx. Wavefronts Required\n" );
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// We assume the local GPR requirements to be "dominated" by the requirement
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// of the TEX clause (which consumes 128 bits regs) ; ALU inst before and
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// after TEX are indeed likely to consume or generate values from/for the
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// TEX clause.
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// Available[IDFetch].size() * 2 : GPRs required in the Fetch clause
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// We assume that fetch instructions are either TnXYZW = TEX TnXYZW (need
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// one GPR) or TmXYZW = TnXYZW (need 2 GPR).
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// (TODO : use RegisterPressure)
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// If we are going too use too many GPR, we flush Fetch instruction to lower
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// register pressure on 128 bits regs.
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unsigned NearRegisterRequirement = 2 * Available[IDFetch].size();
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if (NeededWF > getWFCountLimitedByGPR(NearRegisterRequirement))
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AllowSwitchFromAlu = true;
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}
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}
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if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
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(!AllowSwitchFromAlu && CurInstKind == IDAlu))) {
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// try to pick ALU
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SU = pickAlu();
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if (!SU && !PhysicalRegCopy.empty()) {
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SU = PhysicalRegCopy.front();
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PhysicalRegCopy.erase(PhysicalRegCopy.begin());
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}
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if (SU) {
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if (CurEmitted >= InstKindLimit[IDAlu])
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CurEmitted = 0;
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NextInstKind = IDAlu;
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}
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}
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if (!SU) {
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// try to pick FETCH
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SU = pickOther(IDFetch);
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if (SU)
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NextInstKind = IDFetch;
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}
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// try to pick other
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if (!SU) {
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SU = pickOther(IDOther);
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if (SU)
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NextInstKind = IDOther;
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}
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DEBUG(
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if (SU) {
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dbgs() << " ** Pick node **\n";
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SU->dump(DAG);
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} else {
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dbgs() << "NO NODE \n";
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for (unsigned i = 0; i < DAG->SUnits.size(); i++) {
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const SUnit &S = DAG->SUnits[i];
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if (!S.isScheduled)
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S.dump(DAG);
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}
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}
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);
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return SU;
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}
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void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
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if (NextInstKind != CurInstKind) {
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DEBUG(dbgs() << "Instruction Type Switch\n");
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if (NextInstKind != IDAlu)
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OccupedSlotsMask |= 31;
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CurEmitted = 0;
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CurInstKind = NextInstKind;
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}
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if (CurInstKind == IDAlu) {
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AluInstCount ++;
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switch (getAluKind(SU)) {
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case AluT_XYZW:
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CurEmitted += 4;
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break;
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case AluDiscarded:
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break;
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default: {
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++CurEmitted;
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for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(),
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E = SU->getInstr()->operands_end(); It != E; ++It) {
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MachineOperand &MO = *It;
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if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
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++CurEmitted;
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}
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}
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}
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} else {
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++CurEmitted;
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}
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DEBUG(dbgs() << CurEmitted << " Instructions Emitted in this clause\n");
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if (CurInstKind != IDFetch) {
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MoveUnits(Pending[IDFetch], Available[IDFetch]);
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} else
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FetchInstCount++;
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}
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static bool
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isPhysicalRegCopy(MachineInstr *MI) {
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if (MI->getOpcode() != AMDGPU::COPY)
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return false;
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return !TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg());
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}
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void R600SchedStrategy::releaseTopNode(SUnit *SU) {
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DEBUG(dbgs() << "Top Releasing ";SU->dump(DAG););
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}
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void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
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DEBUG(dbgs() << "Bottom Releasing ";SU->dump(DAG););
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if (isPhysicalRegCopy(SU->getInstr())) {
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PhysicalRegCopy.push_back(SU);
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return;
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}
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int IK = getInstKind(SU);
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// There is no export clause, we can schedule one as soon as its ready
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if (IK == IDOther)
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Available[IDOther].push_back(SU);
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else
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Pending[IK].push_back(SU);
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}
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bool R600SchedStrategy::regBelongsToClass(unsigned Reg,
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const TargetRegisterClass *RC) const {
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if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
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return RC->contains(Reg);
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} else {
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return MRI->getRegClass(Reg) == RC;
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}
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}
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R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
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MachineInstr *MI = SU->getInstr();
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if (TII->isTransOnly(*MI))
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return AluTrans;
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switch (MI->getOpcode()) {
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case AMDGPU::PRED_X:
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return AluPredX;
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case AMDGPU::INTERP_PAIR_XY:
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case AMDGPU::INTERP_PAIR_ZW:
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case AMDGPU::INTERP_VEC_LOAD:
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case AMDGPU::DOT_4:
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return AluT_XYZW;
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case AMDGPU::COPY:
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if (MI->getOperand(1).isUndef()) {
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// MI will become a KILL, don't considers it in scheduling
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return AluDiscarded;
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}
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default:
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break;
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}
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// Does the instruction take a whole IG ?
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// XXX: Is it possible to add a helper function in R600InstrInfo that can
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// be used here and in R600PacketizerList::isSoloInstruction() ?
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if(TII->isVector(*MI) ||
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TII->isCubeOp(MI->getOpcode()) ||
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TII->isReductionOp(MI->getOpcode()) ||
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MI->getOpcode() == AMDGPU::GROUP_BARRIER) {
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return AluT_XYZW;
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}
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if (TII->isLDSInstr(MI->getOpcode())) {
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return AluT_X;
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}
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// Is the result already assigned to a channel ?
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unsigned DestSubReg = MI->getOperand(0).getSubReg();
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switch (DestSubReg) {
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case AMDGPU::sub0:
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return AluT_X;
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case AMDGPU::sub1:
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return AluT_Y;
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case AMDGPU::sub2:
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return AluT_Z;
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case AMDGPU::sub3:
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return AluT_W;
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default:
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break;
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}
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// Is the result already member of a X/Y/Z/W class ?
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unsigned DestReg = MI->getOperand(0).getReg();
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if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
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regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
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return AluT_X;
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if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
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return AluT_Y;
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if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
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return AluT_Z;
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if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
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return AluT_W;
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if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
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return AluT_XYZW;
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// LDS src registers cannot be used in the Trans slot.
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if (TII->readsLDSSrcReg(*MI))
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return AluT_XYZW;
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return AluAny;
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}
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int R600SchedStrategy::getInstKind(SUnit* SU) {
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int Opcode = SU->getInstr()->getOpcode();
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if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
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return IDFetch;
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if (TII->isALUInstr(Opcode)) {
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return IDAlu;
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}
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switch (Opcode) {
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case AMDGPU::PRED_X:
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case AMDGPU::COPY:
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case AMDGPU::CONST_COPY:
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case AMDGPU::INTERP_PAIR_XY:
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case AMDGPU::INTERP_PAIR_ZW:
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case AMDGPU::INTERP_VEC_LOAD:
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case AMDGPU::DOT_4:
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return IDAlu;
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default:
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return IDOther;
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}
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}
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SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) {
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if (Q.empty())
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return nullptr;
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for (std::vector<SUnit *>::reverse_iterator It = Q.rbegin(), E = Q.rend();
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It != E; ++It) {
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SUnit *SU = *It;
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InstructionsGroupCandidate.push_back(SU->getInstr());
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if (TII->fitsConstReadLimitations(InstructionsGroupCandidate) &&
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(!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) {
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InstructionsGroupCandidate.pop_back();
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Q.erase((It + 1).base());
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return SU;
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} else {
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InstructionsGroupCandidate.pop_back();
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}
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}
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return nullptr;
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}
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void R600SchedStrategy::LoadAlu() {
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std::vector<SUnit *> &QSrc = Pending[IDAlu];
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for (unsigned i = 0, e = QSrc.size(); i < e; ++i) {
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AluKind AK = getAluKind(QSrc[i]);
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AvailableAlus[AK].push_back(QSrc[i]);
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}
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QSrc.clear();
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}
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void R600SchedStrategy::PrepareNextSlot() {
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DEBUG(dbgs() << "New Slot\n");
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assert (OccupedSlotsMask && "Slot wasn't filled");
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OccupedSlotsMask = 0;
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// if (HwGen == R600Subtarget::NORTHERN_ISLANDS)
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// OccupedSlotsMask |= 16;
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InstructionsGroupCandidate.clear();
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LoadAlu();
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}
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void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) {
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int DstIndex = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
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if (DstIndex == -1) {
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return;
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}
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unsigned DestReg = MI->getOperand(DstIndex).getReg();
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// PressureRegister crashes if an operand is def and used in the same inst
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// and we try to constraint its regclass
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for (MachineInstr::mop_iterator It = MI->operands_begin(),
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E = MI->operands_end(); It != E; ++It) {
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MachineOperand &MO = *It;
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if (MO.isReg() && !MO.isDef() &&
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MO.getReg() == DestReg)
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return;
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}
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// Constrains the regclass of DestReg to assign it to Slot
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switch (Slot) {
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case 0:
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MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass);
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break;
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case 1:
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MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass);
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break;
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case 2:
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MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass);
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break;
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case 3:
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MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);
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break;
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}
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}
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SUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot, bool AnyAlu) {
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static const AluKind IndexToID[] = {AluT_X, AluT_Y, AluT_Z, AluT_W};
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SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu);
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if (SlotedSU)
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return SlotedSU;
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SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu);
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if (UnslotedSU)
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AssignSlot(UnslotedSU->getInstr(), Slot);
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return UnslotedSU;
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}
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unsigned R600SchedStrategy::AvailablesAluCount() const {
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return AvailableAlus[AluAny].size() + AvailableAlus[AluT_XYZW].size() +
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AvailableAlus[AluT_X].size() + AvailableAlus[AluT_Y].size() +
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AvailableAlus[AluT_Z].size() + AvailableAlus[AluT_W].size() +
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AvailableAlus[AluTrans].size() + AvailableAlus[AluDiscarded].size() +
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AvailableAlus[AluPredX].size();
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}
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SUnit* R600SchedStrategy::pickAlu() {
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while (AvailablesAluCount() || !Pending[IDAlu].empty()) {
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if (!OccupedSlotsMask) {
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// Bottom up scheduling : predX must comes first
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if (!AvailableAlus[AluPredX].empty()) {
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OccupedSlotsMask |= 31;
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return PopInst(AvailableAlus[AluPredX], false);
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}
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// Flush physical reg copies (RA will discard them)
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if (!AvailableAlus[AluDiscarded].empty()) {
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OccupedSlotsMask |= 31;
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return PopInst(AvailableAlus[AluDiscarded], false);
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}
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// If there is a T_XYZW alu available, use it
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if (!AvailableAlus[AluT_XYZW].empty()) {
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OccupedSlotsMask |= 15;
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return PopInst(AvailableAlus[AluT_XYZW], false);
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}
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}
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bool TransSlotOccuped = OccupedSlotsMask & 16;
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if (!TransSlotOccuped && VLIW5) {
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if (!AvailableAlus[AluTrans].empty()) {
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OccupedSlotsMask |= 16;
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return PopInst(AvailableAlus[AluTrans], false);
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}
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SUnit *SU = AttemptFillSlot(3, true);
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if (SU) {
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OccupedSlotsMask |= 16;
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return SU;
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}
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}
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for (int Chan = 3; Chan > -1; --Chan) {
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bool isOccupied = OccupedSlotsMask & (1 << Chan);
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if (!isOccupied) {
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SUnit *SU = AttemptFillSlot(Chan, false);
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if (SU) {
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OccupedSlotsMask |= (1 << Chan);
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InstructionsGroupCandidate.push_back(SU->getInstr());
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return SU;
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}
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}
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}
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PrepareNextSlot();
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}
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return nullptr;
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}
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SUnit* R600SchedStrategy::pickOther(int QID) {
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SUnit *SU = nullptr;
|
||||
std::vector<SUnit *> &AQ = Available[QID];
|
||||
|
||||
if (AQ.empty()) {
|
||||
MoveUnits(Pending[QID], AQ);
|
||||
}
|
||||
if (!AQ.empty()) {
|
||||
SU = AQ.back();
|
||||
AQ.resize(AQ.size() - 1);
|
||||
}
|
||||
return SU;
|
||||
}
|
||||
Reference in New Issue
Block a user