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Imported Upstream version 5.18.0.207
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//===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AMDGPUFixupKinds.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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namespace {
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class AMDGPUAsmBackend : public MCAsmBackend {
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public:
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AMDGPUAsmBackend(const Target &T)
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: MCAsmBackend() {}
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unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
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void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved) const override;
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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return false;
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}
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void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
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MCInst &Res) const override {
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llvm_unreachable("Not implemented");
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}
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bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
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unsigned getMinimumNopSize() const override;
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
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};
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} //End anonymous namespace
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static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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case AMDGPU::fixup_si_sopp_br:
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return 2;
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case FK_SecRel_1:
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case FK_Data_1:
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return 1;
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case FK_SecRel_2:
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case FK_Data_2:
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return 2;
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case FK_SecRel_4:
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case FK_Data_4:
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case FK_PCRel_4:
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return 4;
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case FK_SecRel_8:
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case FK_Data_8:
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return 8;
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default:
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llvm_unreachable("Unknown fixup kind!");
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}
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}
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static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext *Ctx) {
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int64_t SignedValue = static_cast<int64_t>(Value);
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switch (static_cast<unsigned>(Fixup.getKind())) {
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case AMDGPU::fixup_si_sopp_br: {
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int64_t BrImm = (SignedValue - 4) / 4;
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if (Ctx && !isInt<16>(BrImm))
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Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16");
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return BrImm;
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}
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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case FK_PCRel_4:
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case FK_SecRel_4:
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return Value;
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default:
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llvm_unreachable("unhandled fixup kind");
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}
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}
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void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target,
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MutableArrayRef<char> Data, uint64_t Value,
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bool IsResolved) const {
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Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
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if (!Value)
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return; // Doesn't change encoding.
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MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
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uint32_t Offset = Fixup.getOffset();
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assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the bits from
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// the fixup value.
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for (unsigned i = 0; i != NumBytes; ++i)
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Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
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}
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const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
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MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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return Infos[Kind - FirstTargetFixupKind];
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}
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unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
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return 4;
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}
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bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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// If the count is not 4-byte aligned, we must be writing data into the text
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// section (otherwise we have unaligned instructions, and thus have far
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// bigger problems), so just write zeros instead.
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OW->WriteZeros(Count % 4);
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// We are properly aligned, so write NOPs as requested.
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Count /= 4;
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// FIXME: R600 support.
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// s_nop 0
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const uint32_t Encoded_S_NOP_0 = 0xbf800000;
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for (uint64_t I = 0; I != Count; ++I)
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OW->write32(Encoded_S_NOP_0);
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return true;
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}
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//===----------------------------------------------------------------------===//
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// ELFAMDGPUAsmBackend class
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//===----------------------------------------------------------------------===//
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namespace {
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class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
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bool Is64Bit;
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bool HasRelocationAddend;
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uint8_t OSABI = ELF::ELFOSABI_NONE;
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public:
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ELFAMDGPUAsmBackend(const Target &T, const Triple &TT) :
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AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
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HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {
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switch (TT.getOS()) {
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case Triple::AMDHSA:
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OSABI = ELF::ELFOSABI_AMDGPU_HSA;
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break;
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case Triple::AMDPAL:
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OSABI = ELF::ELFOSABI_AMDGPU_PAL;
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break;
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case Triple::Mesa3D:
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OSABI = ELF::ELFOSABI_AMDGPU_MESA3D;
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break;
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default:
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break;
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}
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}
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std::unique_ptr<MCObjectWriter>
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createObjectWriter(raw_pwrite_stream &OS) const override {
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return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend, OS);
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}
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};
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} // end anonymous namespace
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MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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// Use 64-bit ELF for amdgcn
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return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());
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}
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