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//===- AMDGPUInstructionSelector.cpp ----------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the InstructionSelector class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstructionSelector.h"
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPURegisterBankInfo.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "amdgpu-isel"
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using namespace llvm;
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AMDGPUInstructionSelector::AMDGPUInstructionSelector(
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const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI)
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: InstructionSelector(), TII(*STI.getInstrInfo()),
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TRI(*STI.getRegisterInfo()), RBI(RBI), AMDGPUASI(STI.getAMDGPUAS()) {}
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MachineOperand
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AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
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unsigned SubIdx) const {
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MachineInstr *MI = MO.getParent();
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MachineBasicBlock *BB = MO.getParent()->getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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if (MO.isReg()) {
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unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx);
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unsigned Reg = MO.getReg();
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BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
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.addReg(Reg, 0, ComposedSubIdx);
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return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
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MO.isKill(), MO.isDead(), MO.isUndef(),
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MO.isEarlyClobber(), 0, MO.isDebug(),
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MO.isInternalRead());
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}
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assert(MO.isImm());
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APInt Imm(64, MO.getImm());
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switch (SubIdx) {
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default:
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llvm_unreachable("do not know to split immediate with this sub index.");
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case AMDGPU::sub0:
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return MachineOperand::CreateImm(Imm.getLoBits(32).getSExtValue());
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case AMDGPU::sub1:
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return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
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}
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}
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bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
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unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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if (Size != 64)
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return false;
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DebugLoc DL = I.getDebugLoc();
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MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
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MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
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.add(Lo1)
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.add(Lo2);
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MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
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MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
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.add(Hi1)
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.add(Hi2);
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
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.addReg(DstLo)
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.addImm(AMDGPU::sub0)
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.addReg(DstHi)
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.addImm(AMDGPU::sub1);
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for (MachineOperand &MO : I.explicit_operands()) {
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if (!MO.isReg() || TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
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continue;
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RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI);
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}
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I.eraseFromParent();
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return true;
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}
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bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
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return selectG_ADD(I);
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}
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bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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DebugLoc DL = I.getDebugLoc();
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// FIXME: Select store instruction based on address space
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MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(AMDGPU::FLAT_STORE_DWORD))
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.add(I.getOperand(1))
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.add(I.getOperand(0))
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.addImm(0) // offset
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.addImm(0) // glc
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.addImm(0); // slc
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// Now that we selected an opcode, we need to constrain the register
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// operands to use appropriate classes.
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bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
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I.eraseFromParent();
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return Ret;
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}
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bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned DstReg = I.getOperand(0).getReg();
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unsigned Size = RBI.getSizeInBits(DstReg, MRI, TRI);
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if (Size == 32) {
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I.setDesc(TII.get(AMDGPU::S_MOV_B32));
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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assert(Size == 64);
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DebugLoc DL = I.getDebugLoc();
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unsigned LoReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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unsigned HiReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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const APInt &Imm = I.getOperand(1).getCImm()->getValue();
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), LoReg)
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.addImm(Imm.trunc(32).getZExtValue());
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg)
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.addImm(Imm.ashr(32).getZExtValue());
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
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.addReg(LoReg)
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.addImm(AMDGPU::sub0)
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.addReg(HiReg)
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.addImm(AMDGPU::sub1);
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// We can't call constrainSelectedInstRegOperands here, because it doesn't
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// work for target independent opcodes
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I.eraseFromParent();
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return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, MRI);
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}
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static bool isConstant(const MachineInstr &MI) {
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return MI.getOpcode() == TargetOpcode::G_CONSTANT;
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}
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void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
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const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const {
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const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
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assert(PtrMI);
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if (PtrMI->getOpcode() != TargetOpcode::G_GEP)
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return;
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GEPInfo GEPInfo(*PtrMI);
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for (unsigned i = 1, e = 3; i < e; ++i) {
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const MachineOperand &GEPOp = PtrMI->getOperand(i);
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const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
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assert(OpDef);
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if (isConstant(*OpDef)) {
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// FIXME: Is it possible to have multiple Imm parts? Maybe if we
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// are lacking other optimizations.
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assert(GEPInfo.Imm == 0);
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GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
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continue;
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}
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const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI);
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if (OpBank->getID() == AMDGPU::SGPRRegBankID)
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GEPInfo.SgprParts.push_back(GEPOp.getReg());
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else
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GEPInfo.VgprParts.push_back(GEPOp.getReg());
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}
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AddrInfo.push_back(GEPInfo);
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getAddrModeInfo(*PtrMI, MRI, AddrInfo);
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}
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static bool isInstrUniform(const MachineInstr &MI) {
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if (!MI.hasOneMemOperand())
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return false;
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const MachineMemOperand *MMO = *MI.memoperands_begin();
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const Value *Ptr = MMO->getValue();
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// UndefValue means this is a load of a kernel input. These are uniform.
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// Sometimes LDS instructions have constant pointers.
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// If Ptr is null, then that means this mem operand contains a
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// PseudoSourceValue like GOT.
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if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
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isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
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return true;
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const Instruction *I = dyn_cast<Instruction>(Ptr);
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return I && I->getMetadata("amdgpu.uniform");
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}
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static unsigned getSmrdOpcode(unsigned BaseOpcode, unsigned LoadSize) {
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if (LoadSize == 32)
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return BaseOpcode;
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switch (BaseOpcode) {
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case AMDGPU::S_LOAD_DWORD_IMM:
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switch (LoadSize) {
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case 64:
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return AMDGPU::S_LOAD_DWORDX2_IMM;
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case 128:
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return AMDGPU::S_LOAD_DWORDX4_IMM;
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case 256:
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return AMDGPU::S_LOAD_DWORDX8_IMM;
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case 512:
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return AMDGPU::S_LOAD_DWORDX16_IMM;
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}
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break;
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case AMDGPU::S_LOAD_DWORD_IMM_ci:
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switch (LoadSize) {
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case 64:
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return AMDGPU::S_LOAD_DWORDX2_IMM_ci;
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case 128:
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return AMDGPU::S_LOAD_DWORDX4_IMM_ci;
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case 256:
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return AMDGPU::S_LOAD_DWORDX8_IMM_ci;
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case 512:
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return AMDGPU::S_LOAD_DWORDX16_IMM_ci;
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}
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break;
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case AMDGPU::S_LOAD_DWORD_SGPR:
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switch (LoadSize) {
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case 64:
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return AMDGPU::S_LOAD_DWORDX2_SGPR;
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case 128:
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return AMDGPU::S_LOAD_DWORDX4_SGPR;
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case 256:
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return AMDGPU::S_LOAD_DWORDX8_SGPR;
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case 512:
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return AMDGPU::S_LOAD_DWORDX16_SGPR;
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}
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break;
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}
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llvm_unreachable("Invalid base smrd opcode or size");
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}
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bool AMDGPUInstructionSelector::hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const {
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for (const GEPInfo &GEPInfo : AddrInfo) {
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if (!GEPInfo.VgprParts.empty())
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return true;
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}
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return false;
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}
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bool AMDGPUInstructionSelector::selectSMRD(MachineInstr &I,
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ArrayRef<GEPInfo> AddrInfo) const {
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if (!I.hasOneMemOperand())
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return false;
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if ((*I.memoperands_begin())->getAddrSpace() != AMDGPUASI.CONSTANT_ADDRESS)
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return false;
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if (!isInstrUniform(I))
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return false;
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if (hasVgprParts(AddrInfo))
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return false;
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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const SISubtarget &Subtarget = MF->getSubtarget<SISubtarget>();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned DstReg = I.getOperand(0).getReg();
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const DebugLoc &DL = I.getDebugLoc();
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unsigned Opcode;
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unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
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if (!AddrInfo.empty() && AddrInfo[0].SgprParts.size() == 1) {
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const GEPInfo &GEPInfo = AddrInfo[0];
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unsigned PtrReg = GEPInfo.SgprParts[0];
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int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(Subtarget, GEPInfo.Imm);
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if (AMDGPU::isLegalSMRDImmOffset(Subtarget, GEPInfo.Imm)) {
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Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);
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MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
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.addReg(PtrReg)
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.addImm(EncodedImm)
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.addImm(0); // glc
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return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
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}
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if (Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS &&
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isUInt<32>(EncodedImm)) {
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Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM_ci, LoadSize);
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MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
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.addReg(PtrReg)
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.addImm(EncodedImm)
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.addImm(0); // glc
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return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
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}
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if (isUInt<32>(GEPInfo.Imm)) {
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Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_SGPR, LoadSize);
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unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), OffsetReg)
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.addImm(GEPInfo.Imm);
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MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
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.addReg(PtrReg)
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.addReg(OffsetReg)
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.addImm(0); // glc
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return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
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}
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}
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unsigned PtrReg = I.getOperand(1).getReg();
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Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);
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MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
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.addReg(PtrReg)
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.addImm(0)
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.addImm(0); // glc
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return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
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}
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bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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DebugLoc DL = I.getDebugLoc();
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unsigned DstReg = I.getOperand(0).getReg();
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unsigned PtrReg = I.getOperand(1).getReg();
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unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
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unsigned Opcode;
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SmallVector<GEPInfo, 4> AddrInfo;
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getAddrModeInfo(I, MRI, AddrInfo);
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if (selectSMRD(I, AddrInfo)) {
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I.eraseFromParent();
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return true;
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}
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switch (LoadSize) {
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default:
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llvm_unreachable("Load size not supported\n");
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case 32:
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Opcode = AMDGPU::FLAT_LOAD_DWORD;
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break;
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case 64:
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Opcode = AMDGPU::FLAT_LOAD_DWORDX2;
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break;
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}
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MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
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.add(I.getOperand(0))
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.addReg(PtrReg)
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.addImm(0) // offset
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.addImm(0) // glc
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.addImm(0); // slc
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bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
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I.eraseFromParent();
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return Ret;
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}
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bool AMDGPUInstructionSelector::select(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const {
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if (!isPreISelGenericOpcode(I.getOpcode()))
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return true;
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switch (I.getOpcode()) {
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default:
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break;
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case TargetOpcode::G_ADD:
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return selectG_ADD(I);
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case TargetOpcode::G_CONSTANT:
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return selectG_CONSTANT(I);
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case TargetOpcode::G_GEP:
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return selectG_GEP(I);
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case TargetOpcode::G_LOAD:
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return selectG_LOAD(I);
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case TargetOpcode::G_STORE:
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return selectG_STORE(I);
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}
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return false;
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}
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