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Imported Upstream version 5.18.0.207
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//===- AArch64MacroFusion.cpp - AArch64 Macro Fusion ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the AArch64 implementation of the DAG scheduling
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/// mutation to pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64Subtarget.h"
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#include "llvm/CodeGen/MacroFusion.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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using namespace llvm;
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namespace {
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/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
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/// together. Given SecondMI, when FirstMI is unspecified, then check if
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/// SecondMI may be part of a fused pair at all.
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static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
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const TargetSubtargetInfo &TSI,
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const MachineInstr *FirstMI,
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const MachineInstr &SecondMI) {
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const AArch64InstrInfo &II = static_cast<const AArch64InstrInfo&>(TII);
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const AArch64Subtarget &ST = static_cast<const AArch64Subtarget&>(TSI);
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// Assume wildcards for unspecified instrs.
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unsigned FirstOpcode =
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FirstMI ? FirstMI->getOpcode()
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: static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
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unsigned SecondOpcode = SecondMI.getOpcode();
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if (ST.hasArithmeticBccFusion())
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// Fuse CMN, CMP, TST followed by Bcc.
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if (SecondOpcode == AArch64::Bcc)
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switch (FirstOpcode) {
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default:
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return false;
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case AArch64::ADDSWri:
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case AArch64::ADDSWrr:
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case AArch64::ADDSXri:
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case AArch64::ADDSXrr:
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case AArch64::ANDSWri:
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case AArch64::ANDSWrr:
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case AArch64::ANDSXri:
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case AArch64::ANDSXrr:
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case AArch64::SUBSWri:
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case AArch64::SUBSWrr:
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case AArch64::SUBSXri:
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case AArch64::SUBSXrr:
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case AArch64::BICSWrr:
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case AArch64::BICSXrr:
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return true;
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case AArch64::ADDSWrs:
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case AArch64::ADDSXrs:
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case AArch64::ANDSWrs:
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case AArch64::ANDSXrs:
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case AArch64::SUBSWrs:
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case AArch64::SUBSXrs:
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case AArch64::BICSWrs:
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case AArch64::BICSXrs:
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// Shift value can be 0 making these behave like the "rr" variant...
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return !II.hasShiftedReg(*FirstMI);
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case AArch64::INSTRUCTION_LIST_END:
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return true;
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}
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if (ST.hasArithmeticCbzFusion())
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// Fuse ALU operations followed by CBZ/CBNZ.
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if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
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SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX)
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switch (FirstOpcode) {
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default:
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return false;
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case AArch64::ADDWri:
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case AArch64::ADDWrr:
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case AArch64::ADDXri:
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case AArch64::ADDXrr:
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case AArch64::ANDWri:
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case AArch64::ANDWrr:
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case AArch64::ANDXri:
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case AArch64::ANDXrr:
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case AArch64::EORWri:
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case AArch64::EORWrr:
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case AArch64::EORXri:
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case AArch64::EORXrr:
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case AArch64::ORRWri:
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case AArch64::ORRWrr:
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case AArch64::ORRXri:
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case AArch64::ORRXrr:
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case AArch64::SUBWri:
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case AArch64::SUBWrr:
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case AArch64::SUBXri:
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case AArch64::SUBXrr:
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return true;
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case AArch64::ADDWrs:
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case AArch64::ADDXrs:
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case AArch64::ANDWrs:
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case AArch64::ANDXrs:
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case AArch64::SUBWrs:
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case AArch64::SUBXrs:
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case AArch64::BICWrs:
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case AArch64::BICXrs:
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// Shift value can be 0 making these behave like the "rr" variant...
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return !II.hasShiftedReg(*FirstMI);
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case AArch64::INSTRUCTION_LIST_END:
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return true;
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}
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if (ST.hasFuseAES())
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// Fuse AES crypto operations.
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switch(SecondOpcode) {
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// AES encode.
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case AArch64::AESMCrr:
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case AArch64::AESMCrrTied:
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return FirstOpcode == AArch64::AESErr ||
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FirstOpcode == AArch64::INSTRUCTION_LIST_END;
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// AES decode.
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case AArch64::AESIMCrr:
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case AArch64::AESIMCrrTied:
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return FirstOpcode == AArch64::AESDrr ||
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FirstOpcode == AArch64::INSTRUCTION_LIST_END;
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}
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if (ST.hasFuseLiterals())
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// Fuse literal generation operations.
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switch (SecondOpcode) {
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// PC relative address.
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case AArch64::ADDXri:
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return FirstOpcode == AArch64::ADRP ||
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FirstOpcode == AArch64::INSTRUCTION_LIST_END;
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// 32 bit immediate.
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case AArch64::MOVKWi:
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return (FirstOpcode == AArch64::MOVZWi &&
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SecondMI.getOperand(3).getImm() == 16) ||
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FirstOpcode == AArch64::INSTRUCTION_LIST_END;
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// Lower and upper half of 64 bit immediate.
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case AArch64::MOVKXi:
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return FirstOpcode == AArch64::INSTRUCTION_LIST_END ||
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(FirstOpcode == AArch64::MOVZXi &&
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SecondMI.getOperand(3).getImm() == 16) ||
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(FirstOpcode == AArch64::MOVKXi &&
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FirstMI->getOperand(3).getImm() == 32 &&
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SecondMI.getOperand(3).getImm() == 48);
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}
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return false;
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}
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} // end namespace
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namespace llvm {
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std::unique_ptr<ScheduleDAGMutation> createAArch64MacroFusionDAGMutation () {
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return createMacroFusionDAGMutation(shouldScheduleAdjacent);
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}
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} // end namespace llvm
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