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external/llvm/lib/CodeGen/OptimizePHIs.cpp
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external/llvm/lib/CodeGen/OptimizePHIs.cpp
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//===- OptimizePHIs.cpp - Optimize machine instruction PHIs ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass optimizes machine instruction PHIs to take advantage of
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// opportunities created during DAG legalization.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Pass.h"
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#include <cassert>
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using namespace llvm;
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#define DEBUG_TYPE "opt-phis"
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STATISTIC(NumPHICycles, "Number of PHI cycles replaced");
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STATISTIC(NumDeadPHICycles, "Number of dead PHI cycles");
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namespace {
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class OptimizePHIs : public MachineFunctionPass {
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MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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public:
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static char ID; // Pass identification
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OptimizePHIs() : MachineFunctionPass(ID) {
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initializeOptimizePHIsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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using InstrSet = SmallPtrSet<MachineInstr *, 16>;
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using InstrSetIterator = SmallPtrSetIterator<MachineInstr *>;
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bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg,
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InstrSet &PHIsInCycle);
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bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle);
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bool OptimizeBB(MachineBasicBlock &MBB);
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};
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} // end anonymous namespace
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char OptimizePHIs::ID = 0;
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char &llvm::OptimizePHIsID = OptimizePHIs::ID;
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INITIALIZE_PASS(OptimizePHIs, DEBUG_TYPE,
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"Optimize machine instruction PHIs", false, false)
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bool OptimizePHIs::runOnMachineFunction(MachineFunction &Fn) {
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if (skipFunction(Fn.getFunction()))
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return false;
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MRI = &Fn.getRegInfo();
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TII = Fn.getSubtarget().getInstrInfo();
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// Find dead PHI cycles and PHI cycles that can be replaced by a single
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// value. InstCombine does these optimizations, but DAG legalization may
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// introduce new opportunities, e.g., when i64 values are split up for
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// 32-bit targets.
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bool Changed = false;
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for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
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Changed |= OptimizeBB(*I);
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return Changed;
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}
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/// IsSingleValuePHICycle - Check if MI is a PHI where all the source operands
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/// are copies of SingleValReg, possibly via copies through other PHIs. If
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/// SingleValReg is zero on entry, it is set to the register with the single
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/// non-copy value. PHIsInCycle is a set used to keep track of the PHIs that
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/// have been scanned.
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bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI,
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unsigned &SingleValReg,
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InstrSet &PHIsInCycle) {
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assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction");
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unsigned DstReg = MI->getOperand(0).getReg();
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// See if we already saw this register.
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if (!PHIsInCycle.insert(MI).second)
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return true;
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// Don't scan crazily complex things.
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if (PHIsInCycle.size() == 16)
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return false;
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// Scan the PHI operands.
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for (unsigned i = 1; i != MI->getNumOperands(); i += 2) {
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unsigned SrcReg = MI->getOperand(i).getReg();
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if (SrcReg == DstReg)
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continue;
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MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
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// Skip over register-to-register moves.
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if (SrcMI && SrcMI->isCopy() &&
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!SrcMI->getOperand(0).getSubReg() &&
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!SrcMI->getOperand(1).getSubReg() &&
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TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
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SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
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if (!SrcMI)
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return false;
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if (SrcMI->isPHI()) {
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if (!IsSingleValuePHICycle(SrcMI, SingleValReg, PHIsInCycle))
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return false;
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} else {
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// Fail if there is more than one non-phi/non-move register.
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if (SingleValReg != 0)
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return false;
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SingleValReg = SrcReg;
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}
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}
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return true;
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}
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/// IsDeadPHICycle - Check if the register defined by a PHI is only used by
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/// other PHIs in a cycle.
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bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle) {
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assert(MI->isPHI() && "IsDeadPHICycle expects a PHI instruction");
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unsigned DstReg = MI->getOperand(0).getReg();
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assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
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"PHI destination is not a virtual register");
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// See if we already saw this register.
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if (!PHIsInCycle.insert(MI).second)
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return true;
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// Don't scan crazily complex things.
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if (PHIsInCycle.size() == 16)
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return false;
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for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) {
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if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle))
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return false;
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}
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return true;
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}
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/// OptimizeBB - Remove dead PHI cycles and PHI cycles that can be replaced by
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/// a single value.
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bool OptimizePHIs::OptimizeBB(MachineBasicBlock &MBB) {
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bool Changed = false;
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for (MachineBasicBlock::iterator
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MII = MBB.begin(), E = MBB.end(); MII != E; ) {
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MachineInstr *MI = &*MII++;
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if (!MI->isPHI())
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break;
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// Check for single-value PHI cycles.
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unsigned SingleValReg = 0;
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InstrSet PHIsInCycle;
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if (IsSingleValuePHICycle(MI, SingleValReg, PHIsInCycle) &&
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SingleValReg != 0) {
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unsigned OldReg = MI->getOperand(0).getReg();
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if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
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continue;
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MRI->replaceRegWith(OldReg, SingleValReg);
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MI->eraseFromParent();
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++NumPHICycles;
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Changed = true;
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continue;
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}
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// Check for dead PHI cycles.
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PHIsInCycle.clear();
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if (IsDeadPHICycle(MI, PHIsInCycle)) {
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for (InstrSetIterator PI = PHIsInCycle.begin(), PE = PHIsInCycle.end();
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PI != PE; ++PI) {
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MachineInstr *PhiMI = *PI;
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if (MII == PhiMI)
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++MII;
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PhiMI->eraseFromParent();
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}
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++NumDeadPHICycles;
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Changed = true;
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}
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}
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return Changed;
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}
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