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external/llvm/lib/CodeGen/LivePhysRegs.cpp
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external/llvm/lib/CodeGen/LivePhysRegs.cpp
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//===--- LivePhysRegs.cpp - Live Physical Register Set --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LivePhysRegs utility for tracking liveness of
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// physical registers across machine instructions in forward or backward order.
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// A more detailed description can be found in the corresponding header file.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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/// \brief Remove all registers from the set that get clobbered by the register
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/// mask.
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/// The clobbers set will be the list of live registers clobbered
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/// by the regmask.
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void LivePhysRegs::removeRegsInMask(const MachineOperand &MO,
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SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> *Clobbers) {
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SparseSet<unsigned>::iterator LRI = LiveRegs.begin();
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while (LRI != LiveRegs.end()) {
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if (MO.clobbersPhysReg(*LRI)) {
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if (Clobbers)
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Clobbers->push_back(std::make_pair(*LRI, &MO));
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LRI = LiveRegs.erase(LRI);
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} else
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++LRI;
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}
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}
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/// Remove defined registers and regmask kills from the set.
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void LivePhysRegs::removeDefs(const MachineInstr &MI) {
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for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
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if (O->isReg()) {
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if (!O->isDef())
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continue;
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unsigned Reg = O->getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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removeReg(Reg);
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} else if (O->isRegMask())
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removeRegsInMask(*O);
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}
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}
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/// Add uses to the set.
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void LivePhysRegs::addUses(const MachineInstr &MI) {
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for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
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if (!O->isReg() || !O->readsReg())
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continue;
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unsigned Reg = O->getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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addReg(Reg);
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}
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}
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/// Simulates liveness when stepping backwards over an instruction(bundle):
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/// Remove Defs, add uses. This is the recommended way of calculating liveness.
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void LivePhysRegs::stepBackward(const MachineInstr &MI) {
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// Remove defined registers and regmask kills from the set.
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removeDefs(MI);
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// Add uses to the set.
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addUses(MI);
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}
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/// Simulates liveness when stepping forward over an instruction(bundle): Remove
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/// killed-uses, add defs. This is the not recommended way, because it depends
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/// on accurate kill flags. If possible use stepBackward() instead of this
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/// function.
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void LivePhysRegs::stepForward(const MachineInstr &MI,
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SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> &Clobbers) {
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// Remove killed registers from the set.
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for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
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if (O->isReg()) {
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unsigned Reg = O->getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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if (O->isDef()) {
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// Note, dead defs are still recorded. The caller should decide how to
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// handle them.
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Clobbers.push_back(std::make_pair(Reg, &*O));
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} else {
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if (!O->isKill())
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continue;
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assert(O->isUse());
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removeReg(Reg);
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}
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} else if (O->isRegMask())
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removeRegsInMask(*O, &Clobbers);
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}
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// Add defs to the set.
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for (auto Reg : Clobbers) {
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// Skip dead defs. They shouldn't be added to the set.
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if (Reg.second->isReg() && Reg.second->isDead())
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continue;
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addReg(Reg.first);
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}
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}
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/// Prin the currently live registers to OS.
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void LivePhysRegs::print(raw_ostream &OS) const {
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OS << "Live Registers:";
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if (!TRI) {
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OS << " (uninitialized)\n";
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return;
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}
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if (empty()) {
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OS << " (empty)\n";
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return;
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}
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for (const_iterator I = begin(), E = end(); I != E; ++I)
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OS << " " << printReg(*I, TRI);
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OS << "\n";
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD void LivePhysRegs::dump() const {
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dbgs() << " " << *this;
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}
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#endif
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bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
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unsigned Reg) const {
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if (LiveRegs.count(Reg))
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return false;
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if (MRI.isReserved(Reg))
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return false;
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for (MCRegAliasIterator R(Reg, TRI, false); R.isValid(); ++R) {
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if (LiveRegs.count(*R))
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return false;
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}
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return true;
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}
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/// Add live-in registers of basic block \p MBB to \p LiveRegs.
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void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
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for (const auto &LI : MBB.liveins()) {
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unsigned Reg = LI.PhysReg;
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LaneBitmask Mask = LI.LaneMask;
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MCSubRegIndexIterator S(Reg, TRI);
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assert(Mask.any() && "Invalid livein mask");
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if (Mask.all() || !S.isValid()) {
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addReg(Reg);
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continue;
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}
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for (; S.isValid(); ++S) {
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unsigned SI = S.getSubRegIndex();
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if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())
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addReg(S.getSubReg());
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}
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}
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}
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/// Adds all callee saved registers to \p LiveRegs.
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static void addCalleeSavedRegs(LivePhysRegs &LiveRegs,
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const MachineFunction &MF) {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR)
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LiveRegs.addReg(*CSR);
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}
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void LivePhysRegs::addPristines(const MachineFunction &MF) {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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if (!MFI.isCalleeSavedInfoValid())
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return;
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/// This function will usually be called on an empty object, handle this
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/// as a special case.
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if (empty()) {
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/// Add all callee saved regs, then remove the ones that are saved and
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/// restored.
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addCalleeSavedRegs(*this, MF);
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/// Remove the ones that are not saved/restored; they are pristine.
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for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
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removeReg(Info.getReg());
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return;
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}
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/// If a callee-saved register that is not pristine is already present
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/// in the set, we should make sure that it stays in it. Precompute the
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/// set of pristine registers in a separate object.
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/// Add all callee saved regs, then remove the ones that are saved+restored.
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LivePhysRegs Pristine(*TRI);
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addCalleeSavedRegs(Pristine, MF);
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/// Remove the ones that are not saved/restored; they are pristine.
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for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
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Pristine.removeReg(Info.getReg());
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for (MCPhysReg R : Pristine)
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addReg(R);
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}
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void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) {
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// To get the live-outs we simply merge the live-ins of all successors.
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for (const MachineBasicBlock *Succ : MBB.successors())
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addBlockLiveIns(*Succ);
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if (MBB.isReturnBlock()) {
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// Return blocks are a special case because we currently don't mark up
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// return instructions completely: specifically, there is no explicit
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// use for callee-saved registers. So we add all callee saved registers
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// that are saved and restored (somewhere). This does not include
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// callee saved registers that are unused and hence not saved and
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// restored; they are called pristine.
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// FIXME: PEI should add explicit markings to return instructions
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// instead of implicitly handling them here.
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const MachineFunction &MF = *MBB.getParent();
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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if (MFI.isCalleeSavedInfoValid()) {
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for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
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if (Info.isRestored())
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addReg(Info.getReg());
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}
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}
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}
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void LivePhysRegs::addLiveOuts(const MachineBasicBlock &MBB) {
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const MachineFunction &MF = *MBB.getParent();
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addPristines(MF);
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addLiveOutsNoPristines(MBB);
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}
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void LivePhysRegs::addLiveIns(const MachineBasicBlock &MBB) {
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const MachineFunction &MF = *MBB.getParent();
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addPristines(MF);
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addBlockLiveIns(MBB);
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}
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void llvm::computeLiveIns(LivePhysRegs &LiveRegs,
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const MachineBasicBlock &MBB) {
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const MachineFunction &MF = *MBB.getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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LiveRegs.init(TRI);
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LiveRegs.addLiveOutsNoPristines(MBB);
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for (const MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend()))
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LiveRegs.stepBackward(MI);
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}
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void llvm::addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs) {
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assert(MBB.livein_empty() && "Expected empty live-in list");
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const MachineFunction &MF = *MBB.getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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for (MCPhysReg Reg : LiveRegs) {
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if (MRI.isReserved(Reg))
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continue;
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// Skip the register if we are about to add one of its super registers.
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bool ContainsSuperReg = false;
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for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {
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if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
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ContainsSuperReg = true;
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break;
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}
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}
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if (ContainsSuperReg)
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continue;
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MBB.addLiveIn(Reg);
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}
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}
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void llvm::recomputeLivenessFlags(MachineBasicBlock &MBB) {
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const MachineFunction &MF = *MBB.getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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// We walk through the block backwards and start with the live outs.
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LivePhysRegs LiveRegs;
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LiveRegs.init(TRI);
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LiveRegs.addLiveOutsNoPristines(MBB);
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for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
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// Recompute dead flags.
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for (MIBundleOperands MO(MI); MO.isValid(); ++MO) {
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if (!MO->isReg() || !MO->isDef() || MO->isDebug())
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continue;
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unsigned Reg = MO->getReg();
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if (Reg == 0)
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continue;
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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bool IsNotLive = LiveRegs.available(MRI, Reg);
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MO->setIsDead(IsNotLive);
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}
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// Step backward over defs.
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LiveRegs.removeDefs(MI);
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// Recompute kill flags.
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for (MIBundleOperands MO(MI); MO.isValid(); ++MO) {
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if (!MO->isReg() || !MO->readsReg() || MO->isDebug())
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continue;
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unsigned Reg = MO->getReg();
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if (Reg == 0)
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continue;
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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bool IsNotLive = LiveRegs.available(MRI, Reg);
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MO->setIsKill(IsNotLive);
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}
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// Complete the stepbackward.
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LiveRegs.addUses(MI);
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}
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}
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void llvm::computeAndAddLiveIns(LivePhysRegs &LiveRegs,
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MachineBasicBlock &MBB) {
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computeLiveIns(LiveRegs, MBB);
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addLiveIns(MBB, LiveRegs);
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}
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