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Imported Upstream version 5.18.0.161

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Former-commit-id: 4db48158d3a35497b8f118ab21b5f08ac3d86d98
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Xamarin Public Jenkins (auto-signing)
2018-10-19 08:34:24 +00:00
parent 37fbf886a3
commit e19d552987
28702 changed files with 3868076 additions and 803 deletions
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18
external/llvm/test/CodeGen/SystemZ/regalloc-GR128.ll vendored Normal file
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -O3 -o /dev/null
;
; Test that regalloc does not run out of registers
; This test will include a GR128 virtual reg.
define void @test0(i64 %dividend, i64 %divisor) {
%rem = urem i64 %dividend, %divisor
call void asm sideeffect "", "{r0},{r1},{r2},{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14}"(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 %rem)
ret void
}
; This test will include an ADDR128 virtual reg.
define i64 @test1(i64 %dividend, i64 %divisor) {
%rem = urem i64 %dividend, %divisor
call void asm sideeffect "", "{r2},{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14}"(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 %rem)
%ret = add i64 %rem, 1
ret i64 %ret
}