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Imported Upstream version 5.18.0.161

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Former-commit-id: 4db48158d3a35497b8f118ab21b5f08ac3d86d98
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Xamarin Public Jenkins (auto-signing)
2018-10-19 08:34:24 +00:00
parent 37fbf886a3
commit e19d552987
28702 changed files with 3868076 additions and 803 deletions
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22
external/llvm/test/CodeGen/AArch64/aarch64-wide-shuffle.ll vendored Normal file
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; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"
define <4 x i16> @f(<4 x i32> %vqdmlal_v3.i, <8 x i16> %x5) {
entry:
; Check that we don't just dup the input vector. The code emitted is ext, dup, ext, ext
; but only match the last three instructions as the first two could be combined to
; a dup2 at some stage.
; CHECK: dup
; CHECK: ext
; CHECK: ext
%x4 = extractelement <4 x i32> %vqdmlal_v3.i, i32 2
%vgetq_lane = trunc i32 %x4 to i16
%vecinit.i = insertelement <4 x i16> undef, i16 %vgetq_lane, i32 0
%vecinit2.i = insertelement <4 x i16> %vecinit.i, i16 %vgetq_lane, i32 2
%vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vgetq_lane, i32 3
%vgetq_lane261 = extractelement <8 x i16> %x5, i32 0
%vset_lane267 = insertelement <4 x i16> %vecinit3.i, i16 %vgetq_lane261, i32 1
ret <4 x i16> %vset_lane267
}