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external/llvm/lib/CodeGen/RegAllocBasic.cpp
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external/llvm/lib/CodeGen/RegAllocBasic.cpp
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//===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RABasic function pass, which provides a minimal
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// implementation of the basic register allocator.
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//
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//===----------------------------------------------------------------------===//
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#include "AllocationOrder.h"
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#include "LiveDebugVariables.h"
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#include "RegAllocBase.h"
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#include "Spiller.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/LiveRegMatrix.h"
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#include "llvm/CodeGen/LiveStacks.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/PassAnalysisSupport.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cstdlib>
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#include <queue>
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
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createBasicRegisterAllocator);
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namespace {
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struct CompSpillWeight {
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bool operator()(LiveInterval *A, LiveInterval *B) const {
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return A->weight < B->weight;
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}
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};
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}
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namespace {
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/// RABasic provides a minimal implementation of the basic register allocation
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/// algorithm. It prioritizes live virtual registers by spill weight and spills
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/// whenever a register is unavailable. This is not practical in production but
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/// provides a useful baseline both for measuring other allocators and comparing
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/// the speed of the basic algorithm against other styles of allocators.
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class RABasic : public MachineFunctionPass,
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public RegAllocBase,
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private LiveRangeEdit::Delegate {
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// context
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MachineFunction *MF;
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// state
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std::unique_ptr<Spiller> SpillerInstance;
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std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
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CompSpillWeight> Queue;
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// Scratch space. Allocated here to avoid repeated malloc calls in
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// selectOrSplit().
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BitVector UsableRegs;
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bool LRE_CanEraseVirtReg(unsigned) override;
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void LRE_WillShrinkVirtReg(unsigned) override;
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public:
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RABasic();
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/// Return the pass name.
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StringRef getPassName() const override { return "Basic Register Allocator"; }
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/// RABasic analysis usage.
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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void releaseMemory() override;
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Spiller &spiller() override { return *SpillerInstance; }
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void enqueue(LiveInterval *LI) override {
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Queue.push(LI);
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}
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LiveInterval *dequeue() override {
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if (Queue.empty())
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return nullptr;
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LiveInterval *LI = Queue.top();
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Queue.pop();
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return LI;
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}
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unsigned selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<unsigned> &SplitVRegs) override;
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/// Perform register allocation.
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bool runOnMachineFunction(MachineFunction &mf) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoPHIs);
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}
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// Helper for spilling all live virtual registers currently unified under preg
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// that interfere with the most recently queried lvr. Return true if spilling
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// was successful, and append any new spilled/split intervals to splitLVRs.
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bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
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SmallVectorImpl<unsigned> &SplitVRegs);
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static char ID;
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};
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char RABasic::ID = 0;
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} // end anonymous namespace
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char &llvm::RABasicID = RABasic::ID;
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INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
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INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
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INITIALIZE_PASS_DEPENDENCY(LiveStacks)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
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INITIALIZE_PASS_END(RABasic, "regallocbasic", "Basic Register Allocator", false,
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false)
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bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) {
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LiveInterval &LI = LIS->getInterval(VirtReg);
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if (VRM->hasPhys(VirtReg)) {
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Matrix->unassign(LI);
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aboutToRemoveInterval(LI);
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return true;
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}
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// Unassigned virtreg is probably in the priority queue.
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// RegAllocBase will erase it after dequeueing.
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// Nonetheless, clear the live-range so that the debug
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// dump will show the right state for that VirtReg.
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LI.clear();
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return false;
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}
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void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) {
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if (!VRM->hasPhys(VirtReg))
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return;
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// Register is assigned, put it back on the queue for reassignment.
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LiveInterval &LI = LIS->getInterval(VirtReg);
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Matrix->unassign(LI);
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enqueue(&LI);
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}
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RABasic::RABasic(): MachineFunctionPass(ID) {
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}
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void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AAResultsWrapperPass>();
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AU.addPreserved<AAResultsWrapperPass>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveDebugVariables>();
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AU.addPreserved<LiveDebugVariables>();
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AU.addRequired<LiveStacks>();
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AU.addPreserved<LiveStacks>();
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AU.addRequired<MachineBlockFrequencyInfo>();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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AU.addRequiredID(MachineDominatorsID);
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AU.addPreservedID(MachineDominatorsID);
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addRequired<VirtRegMap>();
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AU.addPreserved<VirtRegMap>();
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AU.addRequired<LiveRegMatrix>();
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AU.addPreserved<LiveRegMatrix>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void RABasic::releaseMemory() {
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SpillerInstance.reset();
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}
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// Spill or split all live virtual registers currently unified under PhysReg
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// that interfere with VirtReg. The newly spilled or split live intervals are
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// returned by appending them to SplitVRegs.
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bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
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SmallVectorImpl<unsigned> &SplitVRegs) {
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// Record each interference and determine if all are spillable before mutating
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// either the union or live intervals.
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SmallVector<LiveInterval*, 8> Intfs;
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// Collect interferences assigned to any alias of the physical register.
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for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
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LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
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Q.collectInterferingVRegs();
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for (unsigned i = Q.interferingVRegs().size(); i; --i) {
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LiveInterval *Intf = Q.interferingVRegs()[i - 1];
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if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
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return false;
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Intfs.push_back(Intf);
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}
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}
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DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
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<< " interferences with " << VirtReg << "\n");
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assert(!Intfs.empty() && "expected interference");
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// Spill each interfering vreg allocated to PhysReg or an alias.
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for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
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LiveInterval &Spill = *Intfs[i];
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// Skip duplicates.
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if (!VRM->hasPhys(Spill.reg))
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continue;
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// Deallocate the interfering vreg by removing it from the union.
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// A LiveInterval instance may not be in a union during modification!
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Matrix->unassign(Spill);
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// Spill the extracted interval.
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LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
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spiller().spill(LRE);
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}
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return true;
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}
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// Driver for the register assignment and splitting heuristics.
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// Manages iteration over the LiveIntervalUnions.
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//
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// This is a minimal implementation of register assignment and splitting that
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// spills whenever we run out of registers.
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//
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// selectOrSplit can only be called once per live virtual register. We then do a
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// single interference test for each register the correct class until we find an
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// available register. So, the number of interference tests in the worst case is
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// |vregs| * |machineregs|. And since the number of interference tests is
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// minimal, there is no value in caching them outside the scope of
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// selectOrSplit().
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unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<unsigned> &SplitVRegs) {
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// Populate a list of physical register spill candidates.
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SmallVector<unsigned, 8> PhysRegSpillCands;
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// Check for an available register in this class.
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AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
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while (unsigned PhysReg = Order.next()) {
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// Check for interference in PhysReg
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switch (Matrix->checkInterference(VirtReg, PhysReg)) {
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case LiveRegMatrix::IK_Free:
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// PhysReg is available, allocate it.
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return PhysReg;
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case LiveRegMatrix::IK_VirtReg:
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// Only virtual registers in the way, we may be able to spill them.
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PhysRegSpillCands.push_back(PhysReg);
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continue;
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default:
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// RegMask or RegUnit interference.
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continue;
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}
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}
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// Try to spill another interfering reg with less spill weight.
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for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
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PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
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if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
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continue;
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assert(!Matrix->checkInterference(VirtReg, *PhysRegI) &&
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"Interference after spill.");
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// Tell the caller to allocate to this newly freed physical register.
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return *PhysRegI;
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}
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// No other spill candidates were found, so spill the current VirtReg.
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DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
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if (!VirtReg.isSpillable())
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return ~0u;
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LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
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spiller().spill(LRE);
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// The live virtual register requesting allocation was spilled, so tell
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// the caller not to allocate anything during this round.
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return 0;
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}
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bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
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<< "********** Function: "
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<< mf.getName() << '\n');
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MF = &mf;
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RegAllocBase::init(getAnalysis<VirtRegMap>(),
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getAnalysis<LiveIntervals>(),
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getAnalysis<LiveRegMatrix>());
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calculateSpillWeightsAndHints(*LIS, *MF, VRM,
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getAnalysis<MachineLoopInfo>(),
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getAnalysis<MachineBlockFrequencyInfo>());
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SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
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allocatePhysRegs();
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postOptimization();
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// Diagnostic output before rewriting
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DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
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releaseMemory();
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return true;
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}
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FunctionPass* llvm::createBasicRegisterAllocator()
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{
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return new RABasic();
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}
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