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Imported Upstream version 5.18.0.182

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Former-commit-id: f9d55cf82631bfd710c387739687e5845296aea1
This commit is contained in:
Xamarin Public Jenkins (auto-signing)
2018-10-26 08:32:15 +00:00
parent 8625704ad8
commit b716dc8d12
28490 changed files with 76 additions and 3866845 deletions
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31
external/llvm/test/TableGen/AsmPredicateCondsEmission.td vendored
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@@ -1,31 +0,0 @@
// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
// Check that we don't generate invalid code of the form "( && Cond2)" when
// emitting AssemblerPredicate conditions. In the example below, the invalid
// code would be: "return ( && (Bits & arch::AssemblerCondition2));".
include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { }
def arch : Target {
let InstructionSet = archInstrInfo;
}
def Pred1 : Predicate<"Condition1">;
def Pred2 : Predicate<"Condition2">,
AssemblerPredicate<"AssemblerCondition2">;
def foo : Instruction {
let Size = 2;
let OutOperandList = (outs);
let InOperandList = (ins);
field bits<16> Inst;
let Inst = 0xAAAA;
let AsmString = "foo";
field bits<16> SoftFail = 0;
// This is the important bit:
let Predicates = [Pred1, Pred2];
}
// CHECK: return (Bits[arch::AssemblerCondition2]);