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Imported Upstream version 5.18.0.182

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Former-commit-id: f9d55cf82631bfd710c387739687e5845296aea1
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Xamarin Public Jenkins (auto-signing)
2018-10-26 08:32:15 +00:00
parent 8625704ad8
commit b716dc8d12
28490 changed files with 76 additions and 3866845 deletions
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18
external/llvm/test/CodeGen/SystemZ/regalloc-GR128.ll vendored
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@@ -1,18 +0,0 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -O3 -o /dev/null
;
; Test that regalloc does not run out of registers
; This test will include a GR128 virtual reg.
define void @test0(i64 %dividend, i64 %divisor) {
%rem = urem i64 %dividend, %divisor
call void asm sideeffect "", "{r0},{r1},{r2},{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14}"(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 %rem)
ret void
}
; This test will include an ADDR128 virtual reg.
define i64 @test1(i64 %dividend, i64 %divisor) {
%rem = urem i64 %dividend, %divisor
call void asm sideeffect "", "{r2},{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14}"(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 %rem)
%ret = add i64 %rem, 1
ret i64 %ret
}