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Imported Upstream version 5.18.0.182

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Former-commit-id: f9d55cf82631bfd710c387739687e5845296aea1
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Xamarin Public Jenkins (auto-signing)
2018-10-26 08:32:15 +00:00
parent 8625704ad8
commit b716dc8d12
28490 changed files with 76 additions and 3866845 deletions
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23
external/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll vendored
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@@ -1,23 +0,0 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
; We need second, post-ra scheduling to have VSTM instruction combined from single-stores
; CHECK: ********** MI Scheduling **********
; CHECK: schedule starting
; CHECK: VSTMDIA
; CHECK: rdefs left
; CHECK-NEXT: Latency : 2
%bigVec = type [2 x double]
@var = global %bigVec zeroinitializer
define void @bar(%bigVec* %ptr) {
%tmp = load %bigVec, %bigVec* %ptr
store %bigVec %tmp, %bigVec* @var
ret void
}