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//===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MipsAsmBackend class.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "MCTargetDesc/MipsAsmBackend.h"
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#include "MCTargetDesc/MipsFixupKinds.h"
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#include "MCTargetDesc/MipsMCExpr.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Prepare value for the target space for it
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static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext &Ctx) {
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unsigned Kind = Fixup.getKind();
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// Add/subtract and shift
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switch (Kind) {
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default:
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return 0;
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case FK_Data_2:
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case Mips::fixup_Mips_LO16:
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case Mips::fixup_Mips_GPREL16:
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case Mips::fixup_Mips_GPOFF_HI:
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case Mips::fixup_Mips_GPOFF_LO:
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case Mips::fixup_Mips_GOT_PAGE:
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case Mips::fixup_Mips_GOT_OFST:
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case Mips::fixup_Mips_GOT_DISP:
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case Mips::fixup_Mips_GOT_LO16:
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case Mips::fixup_Mips_CALL_LO16:
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case Mips::fixup_MICROMIPS_LO16:
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case Mips::fixup_MICROMIPS_GOT_PAGE:
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case Mips::fixup_MICROMIPS_GOT_OFST:
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case Mips::fixup_MICROMIPS_GOT_DISP:
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case Mips::fixup_MIPS_PCLO16:
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Value &= 0xffff;
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break;
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case FK_DTPRel_4:
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case FK_DTPRel_8:
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case FK_TPRel_4:
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case FK_TPRel_8:
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case FK_GPRel_4:
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case FK_Data_4:
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case FK_Data_8:
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case Mips::fixup_Mips_SUB:
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case Mips::fixup_MICROMIPS_SUB:
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break;
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case Mips::fixup_Mips_PC16:
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// The displacement is then divided by 4 to give us an 18 bit
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// address range. Forcing a signed division because Value can be negative.
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Value = (int64_t)Value / 4;
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// We now check if Value can be encoded as a 16-bit signed immediate.
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if (!isInt<16>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");
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return 0;
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}
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break;
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case Mips::fixup_MIPS_PC19_S2:
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case Mips::fixup_MICROMIPS_PC19_S2:
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// Forcing a signed division because Value can be negative.
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Value = (int64_t)Value / 4;
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// We now check if Value can be encoded as a 19-bit signed immediate.
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if (!isInt<19>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup");
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return 0;
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}
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break;
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case Mips::fixup_Mips_26:
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// So far we are only using this type for jumps.
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// The displacement is then divided by 4 to give us an 28 bit
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// address range.
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Value >>= 2;
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break;
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case Mips::fixup_Mips_HI16:
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case Mips::fixup_Mips_GOT:
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case Mips::fixup_MICROMIPS_GOT16:
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case Mips::fixup_Mips_GOT_HI16:
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case Mips::fixup_Mips_CALL_HI16:
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case Mips::fixup_MICROMIPS_HI16:
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case Mips::fixup_MIPS_PCHI16:
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// Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
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Value = ((Value + 0x8000) >> 16) & 0xffff;
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break;
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case Mips::fixup_Mips_HIGHER:
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// Get the 3rd 16-bits.
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Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
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break;
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case Mips::fixup_Mips_HIGHEST:
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// Get the 4th 16-bits.
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Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
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break;
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case Mips::fixup_MICROMIPS_26_S1:
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Value >>= 1;
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break;
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case Mips::fixup_MICROMIPS_PC7_S1:
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Value -= 4;
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// Forcing a signed division because Value can be negative.
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Value = (int64_t) Value / 2;
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// We now check if Value can be encoded as a 7-bit signed immediate.
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if (!isInt<7>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup");
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return 0;
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}
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break;
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case Mips::fixup_MICROMIPS_PC10_S1:
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Value -= 2;
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// Forcing a signed division because Value can be negative.
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Value = (int64_t) Value / 2;
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// We now check if Value can be encoded as a 10-bit signed immediate.
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if (!isInt<10>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup");
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return 0;
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}
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break;
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case Mips::fixup_MICROMIPS_PC16_S1:
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Value -= 4;
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// Forcing a signed division because Value can be negative.
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Value = (int64_t)Value / 2;
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// We now check if Value can be encoded as a 16-bit signed immediate.
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if (!isInt<16>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");
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return 0;
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}
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break;
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case Mips::fixup_MIPS_PC18_S3:
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// Forcing a signed division because Value can be negative.
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Value = (int64_t)Value / 8;
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// We now check if Value can be encoded as a 18-bit signed immediate.
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if (!isInt<18>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
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return 0;
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}
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break;
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case Mips::fixup_MICROMIPS_PC18_S3:
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// Check alignment.
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if ((Value & 7)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
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}
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// Forcing a signed division because Value can be negative.
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Value = (int64_t)Value / 8;
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// We now check if Value can be encoded as a 18-bit signed immediate.
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if (!isInt<18>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
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return 0;
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}
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break;
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case Mips::fixup_MIPS_PC21_S2:
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// Forcing a signed division because Value can be negative.
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Value = (int64_t) Value / 4;
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// We now check if Value can be encoded as a 21-bit signed immediate.
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if (!isInt<21>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");
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return 0;
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}
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break;
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case Mips::fixup_MIPS_PC26_S2:
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// Forcing a signed division because Value can be negative.
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Value = (int64_t) Value / 4;
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// We now check if Value can be encoded as a 26-bit signed immediate.
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if (!isInt<26>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup");
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return 0;
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}
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break;
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case Mips::fixup_MICROMIPS_PC26_S1:
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// Forcing a signed division because Value can be negative.
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Value = (int64_t)Value / 2;
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// We now check if Value can be encoded as a 26-bit signed immediate.
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if (!isInt<26>(Value)) {
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Ctx.reportFatalError(Fixup.getLoc(), "out of range PC26 fixup");
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return 0;
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}
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break;
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case Mips::fixup_MICROMIPS_PC21_S1:
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// Forcing a signed division because Value can be negative.
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Value = (int64_t)Value / 2;
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// We now check if Value can be encoded as a 21-bit signed immediate.
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if (!isInt<21>(Value)) {
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Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");
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return 0;
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}
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break;
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}
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return Value;
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}
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std::unique_ptr<MCObjectWriter>
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MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
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return createMipsELFObjectWriter(OS, TheTriple, IsN32);
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}
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// Little-endian fixup data byte ordering:
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// mips32r2: a | b | x | x
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// microMIPS: x | x | a | b
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static bool needsMMLEByteOrder(unsigned Kind) {
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return Kind != Mips::fixup_MICROMIPS_PC10_S1 &&
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Kind >= Mips::fixup_MICROMIPS_26_S1 &&
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Kind < Mips::LastTargetFixupKind;
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}
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// Calculate index for microMIPS specific little endian byte order
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static unsigned calculateMMLEIndex(unsigned i) {
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assert(i <= 3 && "Index out of range!");
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return (1 - i / 2) * 2 + i % 2;
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}
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/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
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/// data fragment, at the offset specified by the fixup and following the
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/// fixup kind as appropriate.
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void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target,
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MutableArrayRef<char> Data, uint64_t Value,
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bool IsResolved) const {
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MCFixupKind Kind = Fixup.getKind();
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MCContext &Ctx = Asm.getContext();
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Value = adjustFixupValue(Fixup, Value, Ctx);
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if (!Value)
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return; // Doesn't change encoding.
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// Where do we start in the object
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unsigned Offset = Fixup.getOffset();
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// Number of bytes we need to fixup
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unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
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// Used to point to big endian bytes
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unsigned FullSize;
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switch ((unsigned)Kind) {
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case FK_Data_2:
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case Mips::fixup_Mips_16:
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case Mips::fixup_MICROMIPS_PC10_S1:
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FullSize = 2;
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break;
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case FK_Data_8:
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case Mips::fixup_Mips_64:
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FullSize = 8;
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break;
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case FK_Data_4:
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default:
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FullSize = 4;
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break;
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}
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// Grab current value, if any, from bits.
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uint64_t CurVal = 0;
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bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
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: i)
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: (FullSize - 1 - i);
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CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
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}
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uint64_t Mask = ((uint64_t)(-1) >>
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(64 - getFixupKindInfo(Kind).TargetSize));
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CurVal |= Value & Mask;
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// Write out the fixed up bytes back to the code/data bits.
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
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: i)
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: (FullSize - 1 - i);
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Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
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}
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}
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Optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const {
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return StringSwitch<Optional<MCFixupKind>>(Name)
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.Case("R_MIPS_NONE", (MCFixupKind)Mips::fixup_Mips_NONE)
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.Case("R_MIPS_32", FK_Data_4)
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.Default(MCAsmBackend::getFixupKind(Name));
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}
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const MCFixupKindInfo &MipsAsmBackend::
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getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// MipsFixupKinds.h.
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//
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// name offset bits flags
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{ "fixup_Mips_NONE", 0, 0, 0 },
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{ "fixup_Mips_16", 0, 16, 0 },
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{ "fixup_Mips_32", 0, 32, 0 },
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{ "fixup_Mips_REL32", 0, 32, 0 },
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{ "fixup_Mips_26", 0, 26, 0 },
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{ "fixup_Mips_HI16", 0, 16, 0 },
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{ "fixup_Mips_LO16", 0, 16, 0 },
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{ "fixup_Mips_GPREL16", 0, 16, 0 },
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{ "fixup_Mips_LITERAL", 0, 16, 0 },
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{ "fixup_Mips_GOT", 0, 16, 0 },
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{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_CALL16", 0, 16, 0 },
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{ "fixup_Mips_GPREL32", 0, 32, 0 },
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{ "fixup_Mips_SHIFT5", 6, 5, 0 },
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{ "fixup_Mips_SHIFT6", 6, 5, 0 },
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{ "fixup_Mips_64", 0, 64, 0 },
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{ "fixup_Mips_TLSGD", 0, 16, 0 },
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{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
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{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_TLSLDM", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_GPOFF_HI", 0, 16, 0 },
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{ "fixup_Mips_GPOFF_LO", 0, 16, 0 },
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{ "fixup_Mips_GOT_PAGE", 0, 16, 0 },
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{ "fixup_Mips_GOT_OFST", 0, 16, 0 },
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{ "fixup_Mips_GOT_DISP", 0, 16, 0 },
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{ "fixup_Mips_HIGHER", 0, 16, 0 },
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{ "fixup_Mips_HIGHEST", 0, 16, 0 },
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{ "fixup_Mips_GOT_HI16", 0, 16, 0 },
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{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
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{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
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{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
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{ "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
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{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
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{ "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOTTPREL", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 },
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{ "fixup_Mips_SUB", 0, 64, 0 },
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{ "fixup_MICROMIPS_SUB", 0, 64, 0 }
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};
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const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// MipsFixupKinds.h.
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//
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// name offset bits flags
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{ "fixup_Mips_NONE", 0, 0, 0 },
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{ "fixup_Mips_16", 16, 16, 0 },
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{ "fixup_Mips_32", 0, 32, 0 },
|
||||
{ "fixup_Mips_REL32", 0, 32, 0 },
|
||||
{ "fixup_Mips_26", 6, 26, 0 },
|
||||
{ "fixup_Mips_HI16", 16, 16, 0 },
|
||||
{ "fixup_Mips_LO16", 16, 16, 0 },
|
||||
{ "fixup_Mips_GPREL16", 16, 16, 0 },
|
||||
{ "fixup_Mips_LITERAL", 16, 16, 0 },
|
||||
{ "fixup_Mips_GOT", 16, 16, 0 },
|
||||
{ "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_Mips_CALL16", 16, 16, 0 },
|
||||
{ "fixup_Mips_GPREL32", 0, 32, 0 },
|
||||
{ "fixup_Mips_SHIFT5", 21, 5, 0 },
|
||||
{ "fixup_Mips_SHIFT6", 21, 5, 0 },
|
||||
{ "fixup_Mips_64", 0, 64, 0 },
|
||||
{ "fixup_Mips_TLSGD", 16, 16, 0 },
|
||||
{ "fixup_Mips_GOTTPREL", 16, 16, 0 },
|
||||
{ "fixup_Mips_TPREL_HI", 16, 16, 0 },
|
||||
{ "fixup_Mips_TPREL_LO", 16, 16, 0 },
|
||||
{ "fixup_Mips_TLSLDM", 16, 16, 0 },
|
||||
{ "fixup_Mips_DTPREL_HI", 16, 16, 0 },
|
||||
{ "fixup_Mips_DTPREL_LO", 16, 16, 0 },
|
||||
{ "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_Mips_GPOFF_HI", 16, 16, 0 },
|
||||
{ "fixup_Mips_GPOFF_LO", 16, 16, 0 },
|
||||
{ "fixup_Mips_GOT_PAGE", 16, 16, 0 },
|
||||
{ "fixup_Mips_GOT_OFST", 16, 16, 0 },
|
||||
{ "fixup_Mips_GOT_DISP", 16, 16, 0 },
|
||||
{ "fixup_Mips_HIGHER", 16, 16, 0 },
|
||||
{ "fixup_Mips_HIGHEST", 16, 16, 0 },
|
||||
{ "fixup_Mips_GOT_HI16", 16, 16, 0 },
|
||||
{ "fixup_Mips_GOT_LO16", 16, 16, 0 },
|
||||
{ "fixup_Mips_CALL_HI16", 16, 16, 0 },
|
||||
{ "fixup_Mips_CALL_LO16", 16, 16, 0 },
|
||||
{ "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MICROMIPS_26_S1", 6, 26, 0 },
|
||||
{ "fixup_MICROMIPS_HI16", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_LO16", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_GOT16", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel },
|
||||
{ "fixup_MICROMIPS_CALL16", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_TLS_GD", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_GOTTPREL", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 },
|
||||
{ "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 },
|
||||
{ "fixup_Mips_SUB", 0, 64, 0 },
|
||||
{ "fixup_MICROMIPS_SUB", 0, 64, 0 }
|
||||
};
|
||||
|
||||
if (Kind < FirstTargetFixupKind)
|
||||
return MCAsmBackend::getFixupKindInfo(Kind);
|
||||
|
||||
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
|
||||
"Invalid kind!");
|
||||
|
||||
if (IsLittle)
|
||||
return LittleEndianInfos[Kind - FirstTargetFixupKind];
|
||||
return BigEndianInfos[Kind - FirstTargetFixupKind];
|
||||
}
|
||||
|
||||
/// WriteNopData - Write an (optimal) nop sequence of Count bytes
|
||||
/// to the given output. If the target cannot generate such a sequence,
|
||||
/// it should return an error.
|
||||
///
|
||||
/// \return - True on success.
|
||||
bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
|
||||
// Check for a less than instruction size number of bytes
|
||||
// FIXME: 16 bit instructions are not handled yet here.
|
||||
// We shouldn't be using a hard coded number for instruction size.
|
||||
|
||||
// If the count is not 4-byte aligned, we must be writing data into the text
|
||||
// section (otherwise we have unaligned instructions, and thus have far
|
||||
// bigger problems), so just write zeros instead.
|
||||
OW->WriteZeros(Count);
|
||||
return true;
|
||||
}
|
||||
|
||||
MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
|
||||
const MCSubtargetInfo &STI,
|
||||
const MCRegisterInfo &MRI,
|
||||
const MCTargetOptions &Options) {
|
||||
return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
|
||||
Options.ABIName == "n32");
|
||||
}
|
||||
Reference in New Issue
Block a user