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Imported Upstream version 5.18.0.167
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//===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
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/// compression tables.
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///
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//===----------------------------------------------------------------------===//
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#include "CodeGenDAGPatterns.h"
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#include "CodeGenTarget.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/TableGenBackend.h"
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using namespace llvm;
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namespace {
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class X86EVEX2VEXTablesEmitter {
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CodeGenTarget Target;
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// Hold all non-masked & non-broadcasted EVEX encoded instructions
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std::vector<const CodeGenInstruction *> EVEXInsts;
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// Hold all VEX encoded instructions. Divided into groups with same opcodes
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// to make the search more efficient
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std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
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typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
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// Represent both compress tables
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std::vector<Entry> EVEX2VEX128;
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std::vector<Entry> EVEX2VEX256;
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// Represents a manually added entry to the tables
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struct ManualEntry {
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const char *EVEXInstStr;
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const char *VEXInstStr;
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bool Is128Bit;
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};
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public:
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X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Target(R) {}
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// run - Output X86 EVEX2VEX tables.
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void run(raw_ostream &OS);
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private:
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// Prints the given table as a C++ array of type
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// X86EvexToVexCompressTableEntry
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void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
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bool inExceptionList(const CodeGenInstruction *Inst) {
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// List of EVEX instructions that match VEX instructions by the encoding
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// but do not perform the same operation.
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static constexpr const char *ExceptionList[] = {
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"VCVTQQ2PD",
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"VCVTQQ2PS",
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"VPMAXSQ",
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"VPMAXUQ",
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"VPMINSQ",
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"VPMINUQ",
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"VPMULLQ",
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"VPSRAQ",
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"VDBPSADBW",
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"VRNDSCALE",
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"VSCALEFPS"
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};
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// Instruction's name starts with one of the entries in the exception list
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for (StringRef InstStr : ExceptionList) {
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if (Inst->TheDef->getName().startswith(InstStr))
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return true;
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}
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return false;
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}
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};
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void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
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raw_ostream &OS) {
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std::string Size = (Table == EVEX2VEX128) ? "128" : "256";
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OS << "// X86 EVEX encoded instructions that have a VEX " << Size
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<< " encoding\n"
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<< "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
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<< "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
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<< "CompressTable[] = {\n"
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<< " // EVEX scalar with corresponding VEX.\n";
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// Print all entries added to the table
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for (auto Pair : Table) {
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OS << " { X86::" << Pair.first->TheDef->getName()
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<< ", X86::" << Pair.second->TheDef->getName() << " },\n";
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}
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// Some VEX instructions were duplicated to multiple EVEX versions due the
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// introduction of mask variants, and thus some of the EVEX versions have
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// different encoding than the VEX instruction. In order to maximize the
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// compression we add these entries manually.
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static constexpr ManualEntry ManuallyAddedEntries[] = {
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// EVEX-Inst VEX-Inst Is128-bit
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{"VMOVDQU8Z128mr", "VMOVDQUmr", true},
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{"VMOVDQU8Z128rm", "VMOVDQUrm", true},
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{"VMOVDQU8Z128rr", "VMOVDQUrr", true},
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{"VMOVDQU8Z128rr_REV", "VMOVDQUrr_REV", true},
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{"VMOVDQU16Z128mr", "VMOVDQUmr", true},
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{"VMOVDQU16Z128rm", "VMOVDQUrm", true},
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{"VMOVDQU16Z128rr", "VMOVDQUrr", true},
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{"VMOVDQU16Z128rr_REV", "VMOVDQUrr_REV", true},
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{"VMOVDQU8Z256mr", "VMOVDQUYmr", false},
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{"VMOVDQU8Z256rm", "VMOVDQUYrm", false},
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{"VMOVDQU8Z256rr", "VMOVDQUYrr", false},
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{"VMOVDQU8Z256rr_REV", "VMOVDQUYrr_REV", false},
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{"VMOVDQU16Z256mr", "VMOVDQUYmr", false},
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{"VMOVDQU16Z256rm", "VMOVDQUYrm", false},
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{"VMOVDQU16Z256rr", "VMOVDQUYrr", false},
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{"VMOVDQU16Z256rr_REV", "VMOVDQUYrr_REV", false},
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{"VPERMILPDZ128mi", "VPERMILPDmi", true},
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{"VPERMILPDZ128ri", "VPERMILPDri", true},
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{"VPERMILPDZ128rm", "VPERMILPDrm", true},
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{"VPERMILPDZ128rr", "VPERMILPDrr", true},
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{"VPERMILPDZ256mi", "VPERMILPDYmi", false},
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{"VPERMILPDZ256ri", "VPERMILPDYri", false},
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{"VPERMILPDZ256rm", "VPERMILPDYrm", false},
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{"VPERMILPDZ256rr", "VPERMILPDYrr", false},
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{"VPBROADCASTQZ128m", "VPBROADCASTQrm", true},
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{"VPBROADCASTQZ128r", "VPBROADCASTQrr", true},
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{"VPBROADCASTQZ256m", "VPBROADCASTQYrm", false},
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{"VPBROADCASTQZ256r", "VPBROADCASTQYrr", false},
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{"VBROADCASTSDZ256m", "VBROADCASTSDYrm", false},
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{"VBROADCASTSDZ256r", "VBROADCASTSDYrr", false},
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{"VBROADCASTF64X2Z128rm", "VBROADCASTF128", false},
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{"VBROADCASTI64X2Z128rm", "VBROADCASTI128", false},
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{"VEXTRACTF64x2Z256mr", "VEXTRACTF128mr", false},
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{"VEXTRACTF64x2Z256rr", "VEXTRACTF128rr", false},
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{"VEXTRACTI64x2Z256mr", "VEXTRACTI128mr", false},
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{"VEXTRACTI64x2Z256rr", "VEXTRACTI128rr", false},
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{"VINSERTF64x2Z256rm", "VINSERTF128rm", false},
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{"VINSERTF64x2Z256rr", "VINSERTF128rr", false},
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{"VINSERTI64x2Z256rm", "VINSERTI128rm", false},
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{"VINSERTI64x2Z256rr", "VINSERTI128rr", false},
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// These will require some custom adjustment in the conversion pass.
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{"VALIGNDZ128rri", "VPALIGNRrri", true},
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{"VALIGNQZ128rri", "VPALIGNRrri", true},
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{"VALIGNDZ128rmi", "VPALIGNRrmi", true},
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{"VALIGNQZ128rmi", "VPALIGNRrmi", true},
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{"VSHUFF32X4Z256rmi", "VPERM2F128rm", false},
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{"VSHUFF32X4Z256rri", "VPERM2F128rr", false},
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{"VSHUFF64X2Z256rmi", "VPERM2F128rm", false},
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{"VSHUFF64X2Z256rri", "VPERM2F128rr", false},
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{"VSHUFI32X4Z256rmi", "VPERM2I128rm", false},
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{"VSHUFI32X4Z256rri", "VPERM2I128rr", false},
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{"VSHUFI64X2Z256rmi", "VPERM2I128rm", false},
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{"VSHUFI64X2Z256rri", "VPERM2I128rr", false},
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};
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// Print the manually added entries
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for (const ManualEntry &Entry : ManuallyAddedEntries) {
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if ((Table == EVEX2VEX128 && Entry.Is128Bit) ||
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(Table == EVEX2VEX256 && !Entry.Is128Bit)) {
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OS << " { X86::" << Entry.EVEXInstStr << ", X86::" << Entry.VEXInstStr
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<< " },\n";
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}
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}
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OS << "};\n\n";
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}
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// Return true if the 2 BitsInits are equal
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static inline bool equalBitsInits(const BitsInit *B1, const BitsInit *B2) {
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if (B1->getNumBits() != B2->getNumBits())
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PrintFatalError("Comparing two BitsInits with different sizes!");
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for (unsigned i = 0, e = B1->getNumBits(); i != e; ++i) {
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if (BitInit *Bit1 = dyn_cast<BitInit>(B1->getBit(i))) {
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if (BitInit *Bit2 = dyn_cast<BitInit>(B2->getBit(i))) {
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if (Bit1->getValue() != Bit2->getValue())
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return false;
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} else
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PrintFatalError("Invalid BitsInit bit");
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} else
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PrintFatalError("Invalid BitsInit bit");
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}
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return true;
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}
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// Calculates the integer value residing BitsInit object
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static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
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uint64_t Value = 0;
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for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
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if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
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Value |= uint64_t(Bit->getValue()) << i;
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else
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PrintFatalError("Invalid VectSize bit");
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}
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return Value;
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}
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// Function object - Operator() returns true if the given VEX instruction
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// matches the EVEX instruction of this object.
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class IsMatch {
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const CodeGenInstruction *Inst;
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public:
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IsMatch(const CodeGenInstruction *Inst) : Inst(Inst) {}
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bool operator()(const CodeGenInstruction *Inst2) {
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Record *Rec1 = Inst->TheDef;
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Record *Rec2 = Inst2->TheDef;
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uint64_t Rec1WVEX =
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getValueFromBitsInit(Rec1->getValueAsBitsInit("VEX_WPrefix"));
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uint64_t Rec2WVEX =
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getValueFromBitsInit(Rec2->getValueAsBitsInit("VEX_WPrefix"));
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if (Rec2->getValueAsDef("OpEnc")->getName().str() != "EncVEX" ||
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// VEX/EVEX fields
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Rec2->getValueAsDef("OpPrefix") != Rec1->getValueAsDef("OpPrefix") ||
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Rec2->getValueAsDef("OpMap") != Rec1->getValueAsDef("OpMap") ||
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Rec2->getValueAsBit("hasVEX_4V") != Rec1->getValueAsBit("hasVEX_4V") ||
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!equalBitsInits(Rec2->getValueAsBitsInit("EVEX_LL"),
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Rec1->getValueAsBitsInit("EVEX_LL")) ||
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(Rec1WVEX != 2 && Rec2WVEX != 2 && Rec1WVEX != Rec2WVEX) ||
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// Instruction's format
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Rec2->getValueAsDef("Form") != Rec1->getValueAsDef("Form") ||
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Rec2->getValueAsBit("isAsmParserOnly") !=
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Rec1->getValueAsBit("isAsmParserOnly"))
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return false;
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// This is needed for instructions with intrinsic version (_Int).
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// Where the only difference is the size of the operands.
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// For example: VUCOMISDZrm and Int_VUCOMISDrm
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// Also for instructions that their EVEX version was upgraded to work with
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// k-registers. For example VPCMPEQBrm (xmm output register) and
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// VPCMPEQBZ128rm (k register output register).
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for (unsigned i = 0; i < Inst->Operands.size(); i++) {
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Record *OpRec1 = Inst->Operands[i].Rec;
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Record *OpRec2 = Inst2->Operands[i].Rec;
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if (OpRec1 == OpRec2)
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continue;
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if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
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if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
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return false;
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} else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
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return false;
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} else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
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if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type"))
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return false;
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} else
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return false;
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}
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return true;
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}
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private:
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static inline bool isRegisterOperand(const Record *Rec) {
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return Rec->isSubClassOf("RegisterClass") ||
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Rec->isSubClassOf("RegisterOperand");
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}
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static inline bool isMemoryOperand(const Record *Rec) {
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return Rec->isSubClassOf("Operand") &&
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Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
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}
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static inline bool isImmediateOperand(const Record *Rec) {
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return Rec->isSubClassOf("Operand") &&
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Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
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}
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static inline unsigned int getRegOperandSize(const Record *RegRec) {
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if (RegRec->isSubClassOf("RegisterClass"))
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return RegRec->getValueAsInt("Alignment");
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if (RegRec->isSubClassOf("RegisterOperand"))
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return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
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llvm_unreachable("Register operand's size not known!");
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}
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};
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void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
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emitSourceFileHeader("X86 EVEX2VEX tables", OS);
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ArrayRef<const CodeGenInstruction *> NumberedInstructions =
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Target.getInstructionsByEnumValue();
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for (const CodeGenInstruction *Inst : NumberedInstructions) {
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// Filter non-X86 instructions.
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if (!Inst->TheDef->isSubClassOf("X86Inst"))
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continue;
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// Add VEX encoded instructions to one of VEXInsts vectors according to
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// it's opcode.
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if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
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uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
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getValueAsBitsInit("Opcode"));
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VEXInsts[Opcode].push_back(Inst);
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}
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// Add relevant EVEX encoded instructions to EVEXInsts
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else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
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!Inst->TheDef->getValueAsBit("hasEVEX_K") &&
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!Inst->TheDef->getValueAsBit("hasEVEX_B") &&
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getValueFromBitsInit(Inst->TheDef->
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getValueAsBitsInit("EVEX_LL")) != 2 &&
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!inExceptionList(Inst))
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EVEXInsts.push_back(Inst);
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}
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for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
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uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
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getValueAsBitsInit("Opcode"));
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// For each EVEX instruction look for a VEX match in the appropriate vector
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// (instructions with the same opcode) using function object IsMatch.
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auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
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if (Match != VEXInsts[Opcode].end()) {
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const CodeGenInstruction *VEXInst = *Match;
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// In case a match is found add new entry to the appropriate table
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switch (getValueFromBitsInit(
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EVEXInst->TheDef->getValueAsBitsInit("EVEX_LL"))) {
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case 0:
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EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
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break;
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case 1:
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EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
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break;
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default:
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llvm_unreachable("Instruction's size not fit for the mapping!");
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}
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}
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}
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// Print both tables
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printTable(EVEX2VEX128, OS);
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printTable(EVEX2VEX256, OS);
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}
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}
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namespace llvm {
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void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
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X86EVEX2VEXTablesEmitter(RK).run(OS);
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}
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}
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