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external/llvm/utils/TableGen/InstrDocsEmitter.cpp
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external/llvm/utils/TableGen/InstrDocsEmitter.cpp
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//===- InstrDocsEmitter.cpp - Opcode Documentation Generator --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// InstrDocsEmitter generates restructured text documentation for the opcodes
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// that can be used by MachineInstr. For each opcode, the documentation lists:
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// * Opcode name
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// * Assembly string
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// * Flags (e.g. mayLoad, isBranch, ...)
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// * Operands, including type and name
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// * Operand constraints
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// * Implicit register uses & defs
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// * Predicates
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenDAGPatterns.h"
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "TableGenBackends.h"
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#include "llvm/TableGen/Record.h"
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#include <string>
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#include <vector>
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using namespace llvm;
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namespace llvm {
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void writeTitle(StringRef Str, raw_ostream &OS, char Kind = '-') {
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OS << std::string(Str.size(), Kind) << "\n" << Str << "\n"
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<< std::string(Str.size(), Kind) << "\n";
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}
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void writeHeader(StringRef Str, raw_ostream &OS, char Kind = '-') {
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OS << Str << "\n" << std::string(Str.size(), Kind) << "\n";
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}
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std::string escapeForRST(StringRef Str) {
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std::string Result;
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Result.reserve(Str.size() + 4);
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for (char C : Str) {
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switch (C) {
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// We want special characters to be shown as their C escape codes.
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case '\n': Result += "\\n"; break;
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case '\t': Result += "\\t"; break;
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// Underscore at the end of a line has a special meaning in rst.
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case '_': Result += "\\_"; break;
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default: Result += C;
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}
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}
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return Result;
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}
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void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
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CodeGenDAGPatterns CDP(RK);
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CodeGenTarget &Target = CDP.getTargetInfo();
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unsigned VariantCount = Target.getAsmParserVariantCount();
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// Page title.
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std::string Title = Target.getName();
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Title += " Instructions";
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writeTitle(Title, OS);
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OS << "\n";
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for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
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Record *Inst = II->TheDef;
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// Don't print the target-independent instructions.
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if (II->Namespace == "TargetOpcode")
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continue;
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// Heading (instruction name).
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writeHeader(escapeForRST(Inst->getName()), OS, '=');
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OS << "\n";
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// Assembly string(s).
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if (!II->AsmString.empty()) {
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for (unsigned VarNum = 0; VarNum < VariantCount; ++VarNum) {
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Record *AsmVariant = Target.getAsmParserVariant(VarNum);
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OS << "Assembly string";
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if (VariantCount != 1)
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OS << " (" << AsmVariant->getValueAsString("Name") << ")";
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std::string AsmString =
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CodeGenInstruction::FlattenAsmStringVariants(II->AsmString, VarNum);
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// We trim spaces at each end of the asm string because rst needs the
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// formatting backticks to be next to a non-whitespace character.
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OS << ": ``" << escapeForRST(StringRef(AsmString).trim(" "))
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<< "``\n\n";
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}
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}
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// Boolean flags.
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std::vector<const char *> FlagStrings;
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#define xstr(s) str(s)
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#define str(s) #s
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#define FLAG(f) if (II->f) { FlagStrings.push_back(str(f)); }
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FLAG(isReturn)
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FLAG(isBranch)
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FLAG(isIndirectBranch)
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FLAG(isCompare)
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FLAG(isMoveImm)
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FLAG(isBitcast)
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FLAG(isSelect)
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FLAG(isBarrier)
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FLAG(isCall)
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FLAG(isAdd)
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FLAG(canFoldAsLoad)
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FLAG(mayLoad)
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//FLAG(mayLoad_Unset) // Deliberately omitted.
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FLAG(mayStore)
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//FLAG(mayStore_Unset) // Deliberately omitted.
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FLAG(isPredicable)
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FLAG(isConvertibleToThreeAddress)
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FLAG(isCommutable)
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FLAG(isTerminator)
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FLAG(isReMaterializable)
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FLAG(hasDelaySlot)
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FLAG(usesCustomInserter)
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FLAG(hasPostISelHook)
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FLAG(hasCtrlDep)
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FLAG(isNotDuplicable)
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FLAG(hasSideEffects)
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//FLAG(hasSideEffects_Unset) // Deliberately omitted.
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FLAG(isAsCheapAsAMove)
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FLAG(hasExtraSrcRegAllocReq)
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FLAG(hasExtraDefRegAllocReq)
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FLAG(isCodeGenOnly)
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FLAG(isPseudo)
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FLAG(isRegSequence)
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FLAG(isExtractSubreg)
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FLAG(isInsertSubreg)
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FLAG(isConvergent)
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FLAG(hasNoSchedulingInfo)
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if (!FlagStrings.empty()) {
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OS << "Flags: ";
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bool IsFirst = true;
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for (auto FlagString : FlagStrings) {
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if (!IsFirst)
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OS << ", ";
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OS << "``" << FlagString << "``";
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IsFirst = false;
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}
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OS << "\n\n";
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}
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// Operands.
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for (unsigned i = 0; i < II->Operands.size(); ++i) {
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bool IsDef = i < II->Operands.NumDefs;
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auto Op = II->Operands[i];
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if (Op.MINumOperands > 1) {
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// This operand corresponds to multiple operands on the
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// MachineInstruction, so print all of them, showing the types and
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// names of both the compound operand and the basic operands it
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// contains.
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for (unsigned SubOpIdx = 0; SubOpIdx < Op.MINumOperands; ++SubOpIdx) {
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Record *SubRec =
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cast<DefInit>(Op.MIOperandInfo->getArg(SubOpIdx))->getDef();
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StringRef SubOpName = Op.MIOperandInfo->getArgNameStr(SubOpIdx);
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StringRef SubOpTypeName = SubRec->getName();
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OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName()
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<< "/" << SubOpTypeName << ":$" << Op.Name << ".";
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// Not all sub-operands are named, make up a name for these.
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if (SubOpName.empty())
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OS << "anon" << SubOpIdx;
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else
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OS << SubOpName;
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OS << "``\n\n";
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}
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} else {
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// The operand corresponds to only one MachineInstruction operand.
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OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName()
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<< ":$" << Op.Name << "``\n\n";
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}
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}
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// Constraints.
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StringRef Constraints = Inst->getValueAsString("Constraints");
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if (!Constraints.empty()) {
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OS << "Constraints: ``" << Constraints << "``\n\n";
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}
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// Implicit definitions.
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if (!II->ImplicitDefs.empty()) {
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OS << "Implicit defs: ";
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bool IsFirst = true;
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for (Record *Def : II->ImplicitDefs) {
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if (!IsFirst)
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OS << ", ";
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OS << "``" << Def->getName() << "``";
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IsFirst = false;
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}
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OS << "\n\n";
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}
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// Implicit uses.
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if (!II->ImplicitUses.empty()) {
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OS << "Implicit uses: ";
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bool IsFirst = true;
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for (Record *Use : II->ImplicitUses) {
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if (!IsFirst)
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OS << ", ";
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OS << "``" << Use->getName() << "``";
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IsFirst = false;
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}
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OS << "\n\n";
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}
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// Predicates.
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std::vector<Record *> Predicates =
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II->TheDef->getValueAsListOfDefs("Predicates");
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if (!Predicates.empty()) {
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OS << "Predicates: ";
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bool IsFirst = true;
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for (Record *P : Predicates) {
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if (!IsFirst)
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OS << ", ";
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OS << "``" << P->getName() << "``";
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IsFirst = false;
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}
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OS << "\n\n";
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}
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}
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}
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} // end llvm namespace
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