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external/llvm/utils/TableGen/InfoByHwMode.cpp
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206
external/llvm/utils/TableGen/InfoByHwMode.cpp
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//===--- InfoByHwMode.cpp -------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Classes that implement data parameterized by HW modes for instruction
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// selection. Currently it is ValueTypeByHwMode (parameterized ValueType),
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// and RegSizeInfoByHwMode (parameterized register/spill size and alignment
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// data).
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "InfoByHwMode.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <set>
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#include <string>
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using namespace llvm;
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std::string llvm::getModeName(unsigned Mode) {
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if (Mode == DefaultMode)
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return "*";
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return (Twine('m') + Twine(Mode)).str();
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}
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ValueTypeByHwMode::ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH) {
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const HwModeSelect &MS = CGH.getHwModeSelect(R);
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for (const HwModeSelect::PairType &P : MS.Items) {
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auto I = Map.insert({P.first, MVT(llvm::getValueType(P.second))});
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assert(I.second && "Duplicate entry?");
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(void)I;
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}
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}
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bool ValueTypeByHwMode::operator== (const ValueTypeByHwMode &T) const {
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assert(isValid() && T.isValid() && "Invalid type in assignment");
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bool Simple = isSimple();
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if (Simple != T.isSimple())
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return false;
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if (Simple)
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return getSimple() == T.getSimple();
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return Map == T.Map;
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}
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bool ValueTypeByHwMode::operator< (const ValueTypeByHwMode &T) const {
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assert(isValid() && T.isValid() && "Invalid type in comparison");
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// Default order for maps.
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return Map < T.Map;
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}
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MVT &ValueTypeByHwMode::getOrCreateTypeForMode(unsigned Mode, MVT Type) {
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auto F = Map.find(Mode);
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if (F != Map.end())
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return F->second;
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// If Mode is not in the map, look up the default mode. If it exists,
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// make a copy of it for Mode and return it.
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auto D = Map.find(DefaultMode);
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if (D != Map.end())
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return Map.insert(std::make_pair(Mode, D->second)).first->second;
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// If default mode is not present either, use provided Type.
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return Map.insert(std::make_pair(Mode, Type)).first->second;
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}
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StringRef ValueTypeByHwMode::getMVTName(MVT T) {
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StringRef N = llvm::getEnumName(T.SimpleTy);
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N.consume_front("MVT::");
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return N;
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}
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void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const {
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if (isSimple()) {
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OS << getMVTName(getSimple());
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return;
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}
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std::vector<const PairType*> Pairs;
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for (const auto &P : Map)
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Pairs.push_back(&P);
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std::sort(Pairs.begin(), Pairs.end(), deref<std::less<PairType>>());
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OS << '{';
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for (unsigned i = 0, e = Pairs.size(); i != e; ++i) {
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const PairType *P = Pairs[i];
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OS << '(' << getModeName(P->first)
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<< ':' << getMVTName(P->second).str() << ')';
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if (i != e-1)
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OS << ',';
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}
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OS << '}';
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}
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LLVM_DUMP_METHOD
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void ValueTypeByHwMode::dump() const {
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dbgs() << *this << '\n';
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}
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ValueTypeByHwMode llvm::getValueTypeByHwMode(Record *Rec,
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const CodeGenHwModes &CGH) {
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#ifndef NDEBUG
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if (!Rec->isSubClassOf("ValueType"))
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Rec->dump();
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#endif
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assert(Rec->isSubClassOf("ValueType") &&
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"Record must be derived from ValueType");
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if (Rec->isSubClassOf("HwModeSelect"))
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return ValueTypeByHwMode(Rec, CGH);
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return ValueTypeByHwMode(llvm::getValueType(Rec));
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}
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RegSizeInfo::RegSizeInfo(Record *R, const CodeGenHwModes &CGH) {
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RegSize = R->getValueAsInt("RegSize");
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SpillSize = R->getValueAsInt("SpillSize");
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SpillAlignment = R->getValueAsInt("SpillAlignment");
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}
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bool RegSizeInfo::operator< (const RegSizeInfo &I) const {
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return std::tie(RegSize, SpillSize, SpillAlignment) <
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std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
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}
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bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const {
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return RegSize <= I.RegSize &&
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SpillAlignment && I.SpillAlignment % SpillAlignment == 0 &&
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SpillSize <= I.SpillSize;
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}
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void RegSizeInfo::writeToStream(raw_ostream &OS) const {
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OS << "[R=" << RegSize << ",S=" << SpillSize
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<< ",A=" << SpillAlignment << ']';
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}
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RegSizeInfoByHwMode::RegSizeInfoByHwMode(Record *R,
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const CodeGenHwModes &CGH) {
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const HwModeSelect &MS = CGH.getHwModeSelect(R);
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for (const HwModeSelect::PairType &P : MS.Items) {
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auto I = Map.insert({P.first, RegSizeInfo(P.second, CGH)});
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assert(I.second && "Duplicate entry?");
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(void)I;
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}
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}
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bool RegSizeInfoByHwMode::operator< (const RegSizeInfoByHwMode &I) const {
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unsigned M0 = Map.begin()->first;
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return get(M0) < I.get(M0);
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}
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bool RegSizeInfoByHwMode::operator== (const RegSizeInfoByHwMode &I) const {
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unsigned M0 = Map.begin()->first;
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return get(M0) == I.get(M0);
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}
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bool RegSizeInfoByHwMode::isSubClassOf(const RegSizeInfoByHwMode &I) const {
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unsigned M0 = Map.begin()->first;
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return get(M0).isSubClassOf(I.get(M0));
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}
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bool RegSizeInfoByHwMode::hasStricterSpillThan(const RegSizeInfoByHwMode &I)
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const {
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unsigned M0 = Map.begin()->first;
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const RegSizeInfo &A0 = get(M0);
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const RegSizeInfo &B0 = I.get(M0);
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return std::tie(A0.SpillSize, A0.SpillAlignment) >
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std::tie(B0.SpillSize, B0.SpillAlignment);
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}
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void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const {
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typedef typename decltype(Map)::value_type PairType;
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std::vector<const PairType*> Pairs;
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for (const auto &P : Map)
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Pairs.push_back(&P);
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std::sort(Pairs.begin(), Pairs.end(), deref<std::less<PairType>>());
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OS << '{';
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for (unsigned i = 0, e = Pairs.size(); i != e; ++i) {
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const PairType *P = Pairs[i];
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OS << '(' << getModeName(P->first) << ':' << P->second << ')';
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if (i != e-1)
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OS << ',';
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}
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OS << '}';
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}
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namespace llvm {
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raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) {
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T.writeToStream(OS);
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return OS;
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}
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raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T) {
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T.writeToStream(OS);
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return OS;
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}
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raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) {
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T.writeToStream(OS);
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return OS;
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}
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}
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