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Imported Upstream version 5.18.0.167
Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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@ -1,77 +0,0 @@
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; XFAIL: *
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg -verify-region-info %s
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; FIXME: Merge into backedge-id-bug
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; Variant which has an issue with region construction
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define amdgpu_kernel void @loop_backedge_misidentified_alt(i32 addrspace(1)* %arg0) #0 {
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entry:
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%tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16
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%load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid
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%i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4
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br label %LOOP.HEADER
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LOOP.HEADER:
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%i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ]
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call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0
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%tmp12 = zext i32 %i to i64
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%tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12
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%tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16
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%tmp15 = extractelement <4 x i32> %tmp14, i64 0
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%tmp16 = and i32 %tmp15, 65535
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%tmp17 = icmp eq i32 %tmp16, 1
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br i1 %tmp17, label %bb18, label %bb62
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bb18:
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%tmp19 = extractelement <2 x i32> %tmp, i64 0
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%tmp22 = lshr i32 %tmp19, 16
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%tmp24 = urem i32 %tmp22, 52
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%tmp25 = mul nuw nsw i32 %tmp24, 52
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br label %INNER_LOOP
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INNER_LOOP:
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%inner.loop.j = phi i32 [ %tmp25, %bb18 ], [ %inner.loop.j.inc, %INNER_LOOP ]
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call void asm sideeffect "; inner loop body", ""() #0
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%inner.loop.j.inc = add nsw i32 %inner.loop.j, 1
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%inner.loop.cmp = icmp eq i32 %inner.loop.j, 0
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br i1 %inner.loop.cmp, label %INNER_LOOP_BREAK, label %INNER_LOOP
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INNER_LOOP_BREAK:
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%tmp59 = extractelement <4 x i32> %tmp14, i64 2
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call void asm sideeffect "s_nop 23 ", "~{memory}"() #0
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br label %END_ELSE_BLOCK
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bb62:
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%load13 = icmp ult i32 %tmp16, 271
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;br i1 %load13, label %bb64, label %INCREMENT_I
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; branching directly to the return avoids the bug
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br i1 %load13, label %RETURN, label %INCREMENT_I
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bb64:
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call void asm sideeffect "s_nop 42", "~{memory}"() #0
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br label %RETURN
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INCREMENT_I:
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%inc.i = add i32 %i, 1
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call void asm sideeffect "s_nop 0x1336 ; increment $0", "v,~{memory}"(i32 %inc.i) #0
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br label %END_ELSE_BLOCK
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END_ELSE_BLOCK:
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%i.final = phi i32 [ %tmp59, %INNER_LOOP_BREAK ], [ %inc.i, %INCREMENT_I ]
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call void asm sideeffect "s_nop 0x1337 ; end else block $0", "v,~{memory}"(i32 %i.final) #0
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%cmp.end.else.block = icmp eq i32 %i.final, -1
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br i1 %cmp.end.else.block, label %RETURN, label %LOOP.HEADER
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RETURN:
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call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0
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store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { convergent nounwind }
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attributes #1 = { convergent nounwind readnone }
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@ -1,164 +0,0 @@
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; XFAIL: *
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg %s | FileCheck %s
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; StructurizeCFG::orderNodes used an arbitrary and nonsensical sorting
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; function which broke the basic backedge identification algorithm. It
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; would use RPO order, but then do a weird partial sort by the loop
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; depth assuming blocks are sorted by loop. However a block can appear
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; in between blocks of a loop that is not part of a loop, breaking the
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; assumption of the sort.
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;
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; The collectInfos must be done in RPO order. The actual
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; structurization order I think is less important, but unless the loop
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; headers are identified in RPO order, it finds the wrong set of back
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; edges.
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define amdgpu_kernel void @loop_backedge_misidentified(i32 addrspace(1)* %arg0) #0 {
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; CHECK-LABEL: @loop_backedge_misidentified(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP:%.*]] = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16
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; CHECK-NEXT: [[LOAD1:%.*]] = load volatile <2 x float>, <2 x float> addrspace(1)* undef
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; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG0:%.*]], i32 [[TID]]
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; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, i32 addrspace(1)* [[GEP]], align 4
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: LOOP.HEADER:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INITIAL]], [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[FLOW4:%.*]] ]
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; CHECK-NEXT: call void asm sideeffect "s_nop 0x100b
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; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[I]] to i64
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 [[TMP12]]
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; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* [[TMP13]], align 16
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; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP14]], i64 0
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; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 65535
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; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[TMP17]], true
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; CHECK-NEXT: br i1 [[TMP0]], label [[BB62:%.*]], label [[FLOW:%.*]]
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; CHECK: Flow2:
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; CHECK-NEXT: br label [[FLOW]]
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; CHECK: bb18:
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; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP]], i64 0
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; CHECK-NEXT: [[TMP22:%.*]] = lshr i32 [[TMP19]], 16
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; CHECK-NEXT: [[TMP24:%.*]] = urem i32 [[TMP22]], 52
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; CHECK-NEXT: [[TMP25:%.*]] = mul nuw nsw i32 [[TMP24]], 52
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; CHECK-NEXT: br label [[INNER_LOOP:%.*]]
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; CHECK: Flow3:
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; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[TMP59:%.*]], [[INNER_LOOP_BREAK:%.*]] ], [ [[TMP7:%.*]], [[FLOW]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ true, [[INNER_LOOP_BREAK]] ], [ [[TMP8:%.*]], [[FLOW]] ]
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; CHECK-NEXT: br i1 [[TMP2]], label [[END_ELSE_BLOCK:%.*]], label [[FLOW4]]
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; CHECK: INNER_LOOP:
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; CHECK-NEXT: [[INNER_LOOP_J:%.*]] = phi i32 [ [[INNER_LOOP_J_INC:%.*]], [[INNER_LOOP]] ], [ [[TMP25]], [[BB18:%.*]] ]
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: [[INNER_LOOP_J_INC]] = add nsw i32 [[INNER_LOOP_J]], 1
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; CHECK-NEXT: [[INNER_LOOP_CMP:%.*]] = icmp eq i32 [[INNER_LOOP_J]], 0
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; CHECK-NEXT: br i1 [[INNER_LOOP_CMP]], label [[INNER_LOOP_BREAK]], label [[INNER_LOOP]]
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; CHECK: INNER_LOOP_BREAK:
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; CHECK-NEXT: [[TMP59]] = extractelement <4 x i32> [[TMP14]], i64 2
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; CHECK-NEXT: call void asm sideeffect "s_nop 23 ", "~{memory}"() #0
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; CHECK-NEXT: br label [[FLOW3:%.*]]
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; CHECK: bb62:
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; CHECK-NEXT: [[LOAD13:%.*]] = icmp ult i32 [[TMP16]], 271
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; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[LOAD13]], true
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; CHECK-NEXT: br i1 [[TMP3]], label [[INCREMENT_I:%.*]], label [[FLOW1:%.*]]
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; CHECK: Flow1:
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; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[INC_I:%.*]], [[INCREMENT_I]] ], [ undef, [[BB62]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ true, [[INCREMENT_I]] ], [ false, [[BB62]] ]
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; CHECK-NEXT: [[TMP6:%.*]] = phi i1 [ false, [[INCREMENT_I]] ], [ true, [[BB62]] ]
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; CHECK-NEXT: br i1 [[TMP6]], label [[BB64:%.*]], label [[FLOW2:%.*]]
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; CHECK: bb64:
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; CHECK-NEXT: call void asm sideeffect "s_nop 42", "~{memory}"() #0
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; CHECK-NEXT: br label [[FLOW2]]
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; CHECK: Flow:
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; CHECK-NEXT: [[TMP7]] = phi i32 [ [[TMP4]], [[FLOW2]] ], [ undef, [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP8]] = phi i1 [ [[TMP5]], [[FLOW2]] ], [ false, [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP9:%.*]] = phi i1 [ false, [[FLOW2]] ], [ true, [[LOOP_HEADER]] ]
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; CHECK-NEXT: br i1 [[TMP9]], label [[BB18]], label [[FLOW3]]
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; CHECK: INCREMENT_I:
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; CHECK-NEXT: [[INC_I]] = add i32 [[I]], 1
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; CHECK-NEXT: call void asm sideeffect "s_nop 0x1336
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; CHECK-NEXT: br label [[FLOW1]]
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; CHECK: END_ELSE_BLOCK:
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; CHECK-NEXT: [[I_FINAL:%.*]] = phi i32 [ [[TMP1]], [[FLOW3]] ]
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; CHECK-NEXT: call void asm sideeffect "s_nop 0x1337
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; CHECK-NEXT: [[CMP_END_ELSE_BLOCK:%.*]] = icmp eq i32 [[I_FINAL]], -1
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; CHECK-NEXT: br label [[FLOW4]]
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; CHECK: Flow4:
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; CHECK-NEXT: [[TMP10]] = phi i32 [ [[I_FINAL]], [[END_ELSE_BLOCK]] ], [ undef, [[FLOW3]] ]
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; CHECK-NEXT: [[TMP11:%.*]] = phi i1 [ [[CMP_END_ELSE_BLOCK]], [[END_ELSE_BLOCK]] ], [ true, [[FLOW3]] ]
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; CHECK-NEXT: br i1 [[TMP11]], label [[RETURN:%.*]], label [[LOOP_HEADER]]
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; CHECK: RETURN:
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; CHECK-NEXT: call void asm sideeffect "s_nop 0x99
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; CHECK-NEXT: store volatile <2 x float> [[LOAD1]], <2 x float> addrspace(1)* undef, align 8
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; CHECK-NEXT: ret void
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;
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entry:
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%tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16
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%load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid
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%i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4
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br label %LOOP.HEADER
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LOOP.HEADER:
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%i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ]
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call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0
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%tmp12 = zext i32 %i to i64
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%tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12
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%tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16
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%tmp15 = extractelement <4 x i32> %tmp14, i64 0
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%tmp16 = and i32 %tmp15, 65535
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%tmp17 = icmp eq i32 %tmp16, 1
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br i1 %tmp17, label %bb18, label %bb62
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bb18:
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%tmp19 = extractelement <2 x i32> %tmp, i64 0
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%tmp22 = lshr i32 %tmp19, 16
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%tmp24 = urem i32 %tmp22, 52
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%tmp25 = mul nuw nsw i32 %tmp24, 52
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br label %INNER_LOOP
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INNER_LOOP:
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%inner.loop.j = phi i32 [ %tmp25, %bb18 ], [ %inner.loop.j.inc, %INNER_LOOP ]
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call void asm sideeffect "; inner loop body", ""() #0
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%inner.loop.j.inc = add nsw i32 %inner.loop.j, 1
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%inner.loop.cmp = icmp eq i32 %inner.loop.j, 0
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br i1 %inner.loop.cmp, label %INNER_LOOP_BREAK, label %INNER_LOOP
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INNER_LOOP_BREAK:
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%tmp59 = extractelement <4 x i32> %tmp14, i64 2
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call void asm sideeffect "s_nop 23 ", "~{memory}"() #0
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br label %END_ELSE_BLOCK
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bb62:
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%load13 = icmp ult i32 %tmp16, 271
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br i1 %load13, label %bb64, label %INCREMENT_I
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bb64:
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call void asm sideeffect "s_nop 42", "~{memory}"() #0
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br label %RETURN
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INCREMENT_I:
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%inc.i = add i32 %i, 1
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call void asm sideeffect "s_nop 0x1336 ; increment $0", "v,~{memory}"(i32 %inc.i) #0
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br label %END_ELSE_BLOCK
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END_ELSE_BLOCK:
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%i.final = phi i32 [ %tmp59, %INNER_LOOP_BREAK ], [ %inc.i, %INCREMENT_I ]
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call void asm sideeffect "s_nop 0x1337 ; end else block $0", "v,~{memory}"(i32 %i.final) #0
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%cmp.end.else.block = icmp eq i32 %i.final, -1
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br i1 %cmp.end.else.block, label %RETURN, label %LOOP.HEADER
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RETURN:
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call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0
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store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8
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ret void
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}
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; The same function, except break to return block goes directly to the
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; return, which managed to hide the bug.
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; FIXME: Merge variant from backedge-id-bug-xfail
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { convergent nounwind }
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attributes #1 = { convergent nounwind readnone }
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@ -1,2 +0,0 @@
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if not 'AMDGPU' in config.root.targets:
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config.unsupported = True
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@ -1,50 +0,0 @@
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; RUN: opt -S -o - -structurizecfg < %s | FileCheck %s
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; CHECK-LABEL: @invert_branch_on_arg_inf_loop(
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; CHECK: entry:
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; CHECK: %arg.inv = xor i1 %arg, true
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define void @invert_branch_on_arg_inf_loop(i32 addrspace(1)* %out, i1 %arg) {
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entry:
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br i1 %arg, label %for.end, label %sesestart
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sesestart:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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store i32 999, i32 addrspace(1)* %out, align 4
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br i1 %arg, label %for.body, label %seseend
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seseend:
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ret void
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for.end: ; preds = %Flow
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ret void
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}
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; CHECK-LABEL: @invert_branch_on_arg_jump_into_loop(
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; CHECK: entry:
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; CHECK: %arg.inv = xor i1 %arg, true
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; CHECK: Flow:
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; CHECK: Flow1:
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define void @invert_branch_on_arg_jump_into_loop(i32 addrspace(1)* %out, i32 %n, i1 %arg) {
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entry:
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br label %for.body
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for.body:
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%i = phi i32 [0, %entry], [%i.inc, %end.loop]
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%ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %i
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store i32 %i, i32 addrspace(1)* %ptr, align 4
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br i1 %arg, label %mid.loop, label %end.loop
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mid.loop:
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store i32 333, i32 addrspace(1)* %out, align 4
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br label %for.end
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end.loop:
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%i.inc = add i32 %i, 1
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%cmp = icmp ne i32 %i.inc, %n
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret void
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}
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@ -1,53 +0,0 @@
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; RUN: opt -S -structurizecfg %s | FileCheck %s
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; r321751 introduced a bug where control flow branching from if to exit was
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; not handled properly and instead ended up in an infinite loop.
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define void @bug36015(i32 %cmp0, i32 %count) {
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entry:
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br label %loop.outer
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loop.outer:
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%ctr.loop.outer = phi i32 [ 0, %entry ], [ %ctr.else, %else ]
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call void @foo(i32 0)
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br label %loop.inner
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loop.inner:
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%ctr.loop.inner = phi i32 [ %ctr.loop.outer, %loop.outer ], [ %ctr.if, %if ]
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call void @foo(i32 1)
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%cond.inner = icmp eq i32 %cmp0, %ctr.loop.inner
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br i1 %cond.inner, label %if, label %else
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; CHECK: if:
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; CHECK: %0 = xor i1 %cond.if, true
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; CHECK: br label %Flow
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if:
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%ctr.if = add i32 %ctr.loop.inner, 1
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call void @foo(i32 2)
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%cond.if = icmp slt i32 %ctr.if, %count
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br i1 %cond.if, label %loop.inner, label %exit
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; CHECK: Flow:
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; CHECK: %2 = phi i1 [ %0, %if ], [ true, %loop.inner ]
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; CHECK: %3 = phi i1 [ false, %if ], [ true, %loop.inner ]
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; CHECK: br i1 %2, label %Flow1, label %loop.inner
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; CHECK: Flow1:
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; CHECK: br i1 %3, label %else, label %Flow2
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; CHECK: else:
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; CHECK: br label %Flow2
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else:
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%ctr.else = add i32 %ctr.loop.inner, 1
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call void @foo(i32 3)
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%cond.else = icmp slt i32 %ctr.else, %count
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br i1 %cond.else, label %loop.outer, label %exit
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; CHECK: Flow2:
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; CHECK: %6 = phi i1 [ %4, %else ], [ true, %Flow1 ]
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||||
; CHECK: br i1 %6, label %exit, label %loop.outer
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @foo(i32)
|
||||
@ -1,30 +0,0 @@
|
||||
; RUN: opt -S -o - -structurizecfg < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: @invert_constantexpr_condition(
|
||||
; CHECK: %tmp5 = or i1 %tmp4, icmp eq (i32 bitcast (float fadd (float undef, float undef) to i32), i32 0)
|
||||
; CHECK: [ icmp ne (i32 bitcast (float fadd (float undef, float undef) to i32), i32 0), %bb ]
|
||||
define void @invert_constantexpr_condition(i32 %arg, i32 %arg1) #0 {
|
||||
bb:
|
||||
%tmp = icmp eq i32 %arg, 0
|
||||
br i1 icmp eq (i32 bitcast (float fadd (float undef, float undef) to i32), i32 0), label %bb2, label %bb6
|
||||
|
||||
bb2:
|
||||
br i1 %tmp, label %bb3, label %bb6
|
||||
|
||||
bb3:
|
||||
%tmp4 = phi i1 [ %tmp7, %bb6 ], [ undef, %bb2 ]
|
||||
%tmp5 = or i1 %tmp4, icmp eq (i32 bitcast (float fadd (float undef, float undef) to i32), i32 0)
|
||||
br i1 %tmp5, label %bb8, label %bb8
|
||||
|
||||
bb6:
|
||||
%tmp7 = icmp slt i32 %arg, %arg1
|
||||
br label %bb3
|
||||
|
||||
bb8:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
@ -1,50 +0,0 @@
|
||||
; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
|
||||
;
|
||||
; void loop(int *out, int cond_a, int cond_b) {
|
||||
;
|
||||
; unsigned i;
|
||||
; for (i = 0; i < cond_a; i++) {
|
||||
; out[i] = i;
|
||||
; if (i > cond_b) {
|
||||
; break;
|
||||
; }
|
||||
; out[i + cond_a] = i;
|
||||
; }
|
||||
; }
|
||||
|
||||
define void @loop(i32 addrspace(1)* %out, i32 %cond_a, i32 %cond_b) nounwind uwtable {
|
||||
entry:
|
||||
br label %for.cond
|
||||
|
||||
for.cond: ; preds = %for.inc, %entry
|
||||
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
|
||||
%cmp = icmp ult i32 %i.0, %cond_a
|
||||
br i1 %cmp, label %for.body, label %for.end
|
||||
|
||||
; CHECK: for.body:
|
||||
for.body: ; preds = %for.cond
|
||||
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %i.0
|
||||
store i32 %i.0, i32 addrspace(1)* %arrayidx, align 4
|
||||
%cmp1 = icmp ugt i32 %i.0, %cond_b
|
||||
; CHECK: br i1 %{{[0-9a-zA-Z_]+}}, label %for.inc, label %[[FLOW1:[0-9a-zA-Z_]+]]
|
||||
br i1 %cmp1, label %for.end, label %for.inc
|
||||
|
||||
; CHECK: [[FLOW:[0-9a-zA-Z]+]]:
|
||||
; CHECK: br i1 %{{[0-9a-zA-Z_]+}}, label %for.end, label %for.cond
|
||||
|
||||
; CHECK: for.inc:
|
||||
; CHECK: br label %[[FLOW1]]
|
||||
|
||||
for.inc: ; preds = %for.body
|
||||
%0 = add i32 %cond_a, %i.0
|
||||
%arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %0
|
||||
store i32 %i.0, i32 addrspace(1)* %arrayidx3, align 4
|
||||
%inc = add i32 %i.0, 1
|
||||
br label %for.cond
|
||||
|
||||
; CHECK: [[FLOW1]]
|
||||
; CHECK: br label %[[FLOW]]
|
||||
|
||||
for.end: ; preds = %for.cond, %for.body
|
||||
ret void
|
||||
}
|
||||
@ -1,68 +0,0 @@
|
||||
; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
|
||||
|
||||
define void @main(float addrspace(1)* %out) {
|
||||
|
||||
; CHECK: main_body:
|
||||
; CHECK: br label %LOOP.outer
|
||||
main_body:
|
||||
br label %LOOP.outer
|
||||
|
||||
; CHECK: LOOP.outer:
|
||||
; CHECK: br label %LOOP
|
||||
LOOP.outer: ; preds = %ENDIF28, %main_body
|
||||
%temp8.0.ph = phi float [ 0.000000e+00, %main_body ], [ %tmp35, %ENDIF28 ]
|
||||
%temp4.0.ph = phi i32 [ 0, %main_body ], [ %tmp20, %ENDIF28 ]
|
||||
br label %LOOP
|
||||
|
||||
; CHECK: LOOP:
|
||||
; br i1 %{{[0-9]+}}, label %ENDIF, label %Flow
|
||||
LOOP: ; preds = %IF29, %LOOP.outer
|
||||
%temp4.0 = phi i32 [ %temp4.0.ph, %LOOP.outer ], [ %tmp20, %IF29 ]
|
||||
%tmp20 = add i32 %temp4.0, 1
|
||||
%tmp22 = icmp sgt i32 %tmp20, 3
|
||||
br i1 %tmp22, label %ENDLOOP, label %ENDIF
|
||||
|
||||
; CHECK: Flow3
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %ENDLOOP, label %LOOP.outer
|
||||
|
||||
; CHECK: ENDLOOP:
|
||||
; CHECK: ret void
|
||||
ENDLOOP: ; preds = %ENDIF28, %IF29, %LOOP
|
||||
%temp8.1 = phi float [ %temp8.0.ph, %LOOP ], [ %temp8.0.ph, %IF29 ], [ %tmp35, %ENDIF28 ]
|
||||
%tmp23 = icmp eq i32 %tmp20, 3
|
||||
%.45 = select i1 %tmp23, float 0.000000e+00, float 1.000000e+00
|
||||
store float %.45, float addrspace(1)* %out
|
||||
ret void
|
||||
|
||||
; CHECK: ENDIF:
|
||||
; CHECK: br i1 %tmp31, label %IF29, label %Flow1
|
||||
ENDIF: ; preds = %LOOP
|
||||
%tmp31 = icmp sgt i32 %tmp20, 1
|
||||
br i1 %tmp31, label %IF29, label %ENDIF28
|
||||
|
||||
; CHECK: Flow:
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %Flow2, label %LOOP
|
||||
|
||||
; CHECK: IF29:
|
||||
; CHECK: br label %Flow1
|
||||
IF29: ; preds = %ENDIF
|
||||
%tmp32 = icmp sgt i32 %tmp20, 2
|
||||
br i1 %tmp32, label %ENDLOOP, label %LOOP
|
||||
|
||||
; CHECK: Flow1:
|
||||
; CHECK: br label %Flow
|
||||
|
||||
; CHECK: Flow2:
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %ENDIF28, label %Flow3
|
||||
|
||||
; CHECK: ENDIF28:
|
||||
; CHECK: br label %Flow3
|
||||
ENDIF28: ; preds = %ENDIF
|
||||
%tmp35 = fadd float %temp8.0.ph, 1.0
|
||||
%tmp36 = icmp sgt i32 %tmp20, 2
|
||||
br i1 %tmp36, label %ENDLOOP, label %LOOP.outer
|
||||
}
|
||||
|
||||
attributes #0 = { "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
attributes #2 = { readnone }
|
||||
@ -1,38 +0,0 @@
|
||||
; XFAIL: *
|
||||
|
||||
; This test used to generate a region that caused it to delete the entry block,
|
||||
; but it does not anymore after the changes to handling of infinite loops in the
|
||||
; PostDominatorTree.
|
||||
; TODO: This should be either replaced with another IR or deleted completely.
|
||||
|
||||
; RUN: opt -S -o - -structurizecfg -verify-dom-info < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: @no_branch_to_entry_undef(
|
||||
; CHECK: entry:
|
||||
; CHECK-NEXT: br label %entry.orig
|
||||
define void @no_branch_to_entry_undef(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
br i1 undef, label %for.end, label %for.body
|
||||
|
||||
for.body: ; preds = %entry, %for.body
|
||||
store i32 999, i32 addrspace(1)* %out, align 4
|
||||
br label %for.body
|
||||
|
||||
for.end: ; preds = %Flow
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @no_branch_to_entry_true(
|
||||
; CHECK: entry:
|
||||
; CHECK-NEXT: br label %entry.orig
|
||||
define void @no_branch_to_entry_true(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
br i1 true, label %for.end, label %for.body
|
||||
|
||||
for.body: ; preds = %entry, %for.body
|
||||
store i32 999, i32 addrspace(1)* %out, align 4
|
||||
br label %for.body
|
||||
|
||||
for.end: ; preds = %Flow
|
||||
ret void
|
||||
}
|
||||
@ -1,42 +0,0 @@
|
||||
; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
|
||||
|
||||
; CHECK-NOT: br i1 true
|
||||
|
||||
define void @blam(i32 addrspace(1)* nocapture %arg, float %arg1, float %arg2) {
|
||||
; CHECK: bb:
|
||||
bb:
|
||||
br label %bb3
|
||||
|
||||
; CHECK: bb3:
|
||||
bb3: ; preds = %bb7, %bb
|
||||
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb7 ]
|
||||
%tmp4 = fcmp ult float %arg1, 3.500000e+00
|
||||
; CHECK: %0 = xor i1 %tmp4, true
|
||||
; CHECK: br i1 %0, label %bb5, label %Flow
|
||||
br i1 %tmp4, label %bb7, label %bb5
|
||||
|
||||
; CHECK: bb5:
|
||||
bb5: ; preds = %bb3
|
||||
%tmp6 = fcmp olt float 0.000000e+00, %arg2
|
||||
; CHECK: br label %Flow
|
||||
br i1 %tmp6, label %bb10, label %bb7
|
||||
|
||||
; CHECK: Flow:
|
||||
; CHECK: br i1 %3, label %bb7, label %Flow1
|
||||
|
||||
; CHECK: bb7
|
||||
bb7: ; preds = %bb5, %bb3
|
||||
%tmp8 = add nuw nsw i64 %tmp, 1
|
||||
%tmp9 = icmp slt i64 %tmp8, 5
|
||||
; CHECK: br label %Flow1
|
||||
br i1 %tmp9, label %bb3, label %bb10
|
||||
|
||||
; CHECK: Flow1:
|
||||
; CHECK: br i1 %7, label %bb10, label %bb3
|
||||
|
||||
; CHECK: bb10
|
||||
bb10: ; preds = %bb7, %bb5
|
||||
%tmp11 = phi i32 [ 15, %bb5 ], [ 255, %bb7 ]
|
||||
store i32 %tmp11, i32 addrspace(1)* %arg, align 4
|
||||
ret void
|
||||
}
|
||||
@ -1,100 +0,0 @@
|
||||
; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
|
||||
|
||||
; The structurize cfg pass used to do a post-order traversal to generate a list
|
||||
; of ; basic blocks and then operate on the list in reverse. This led to bugs,
|
||||
; because sometimes successors would be visited before their predecessors.
|
||||
; The fix for this was to do a reverse post-order traversal which is what the
|
||||
; algorithm requires.
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @test(float* nocapture %out, i32 %K1, float* nocapture readonly %nr) {
|
||||
|
||||
; CHECK: entry:
|
||||
; CHECK: br label %for.body
|
||||
entry:
|
||||
br label %for.body
|
||||
|
||||
; CHECK: for.body:
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %lor.lhs.false, label %Flow
|
||||
for.body: ; preds = %for.body.backedge, %entry
|
||||
%indvars.iv = phi i64 [ %indvars.iv.be, %for.body.backedge ], [ 1, %entry ]
|
||||
%best_val.027 = phi float [ %best_val.027.be, %for.body.backedge ], [ 5.000000e+01, %entry ]
|
||||
%prev_start.026 = phi i32 [ %tmp26, %for.body.backedge ], [ 0, %entry ]
|
||||
%best_count.025 = phi i32 [ %best_count.025.be, %for.body.backedge ], [ 0, %entry ]
|
||||
%tmp0 = trunc i64 %indvars.iv to i32
|
||||
%cmp1 = icmp eq i32 %tmp0, %K1
|
||||
br i1 %cmp1, label %if.then, label %lor.lhs.false
|
||||
|
||||
; CHECK: lor.lhs.false:
|
||||
; CHECK: br label %Flow
|
||||
lor.lhs.false: ; preds = %for.body
|
||||
%arrayidx = getelementptr inbounds float, float* %nr, i64 %indvars.iv
|
||||
%tmp1 = load float, float* %arrayidx, align 4
|
||||
%tmp2 = add nsw i64 %indvars.iv, -1
|
||||
%arrayidx2 = getelementptr inbounds float, float* %nr, i64 %tmp2
|
||||
%tmp3 = load float, float* %arrayidx2, align 4
|
||||
%cmp3 = fcmp une float %tmp1, %tmp3
|
||||
br i1 %cmp3, label %if.then, label %for.body.1
|
||||
|
||||
; CHECK: Flow:
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %if.then, label %Flow1
|
||||
|
||||
; CHECK: if.then:
|
||||
; CHECK: br label %Flow1
|
||||
if.then: ; preds = %lor.lhs.false, %for.body
|
||||
%sub4 = sub nsw i32 %tmp0, %prev_start.026
|
||||
%tmp4 = add nsw i64 %indvars.iv, -1
|
||||
%arrayidx8 = getelementptr inbounds float, float* %nr, i64 %tmp4
|
||||
%tmp5 = load float, float* %arrayidx8, align 4
|
||||
br i1 %cmp1, label %for.end, label %for.body.1
|
||||
|
||||
; CHECK: for.end:
|
||||
; CHECK: ret void
|
||||
for.end: ; preds = %for.body.1, %if.then
|
||||
%best_val.0.lcssa = phi float [ %best_val.233, %for.body.1 ], [ %tmp5, %if.then ]
|
||||
store float %best_val.0.lcssa, float* %out, align 4
|
||||
ret void
|
||||
|
||||
; CHECK: Flow1
|
||||
; CHECK: br i1 %{{[0-9]}}, label %for.body.1, label %Flow2
|
||||
|
||||
; CHECK: for.body.1:
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %for.body.6, label %Flow3
|
||||
for.body.1: ; preds = %if.then, %lor.lhs.false
|
||||
%best_val.233 = phi float [ %tmp5, %if.then ], [ %best_val.027, %lor.lhs.false ]
|
||||
%best_count.231 = phi i32 [ %sub4, %if.then ], [ %best_count.025, %lor.lhs.false ]
|
||||
%indvars.iv.next.454 = add nsw i64 %indvars.iv, 5
|
||||
%tmp22 = trunc i64 %indvars.iv.next.454 to i32
|
||||
%cmp1.5 = icmp eq i32 %tmp22, %K1
|
||||
br i1 %cmp1.5, label %for.end, label %for.body.6
|
||||
|
||||
; CHECK: Flow2:
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %for.end, label %for.body
|
||||
|
||||
; CHECK: for.body.6:
|
||||
; CHECK: br i1 %cmp5.6, label %if.then6.6, label %for.body.backedge
|
||||
for.body.6: ; preds = %for.body.1
|
||||
%indvars.iv.next.559 = add nsw i64 %indvars.iv, 6
|
||||
%tmp26 = trunc i64 %indvars.iv.next.559 to i32
|
||||
%sub4.6 = sub nsw i32 %tmp26, %tmp22
|
||||
%cmp5.6 = icmp slt i32 %best_count.231, %sub4.6
|
||||
br i1 %cmp5.6, label %if.then6.6, label %for.body.backedge
|
||||
|
||||
; CHECK: if.then6.6
|
||||
; CHECK: br label %for.body.backedge
|
||||
if.then6.6: ; preds = %for.body.6
|
||||
%arrayidx8.6 = getelementptr inbounds float, float* %nr, i64 %indvars.iv.next.454
|
||||
%tmp29 = load float, float* %arrayidx8.6, align 4
|
||||
br label %for.body.backedge
|
||||
|
||||
; CHECK: Flow3:
|
||||
; CHECK: br label %Flow2
|
||||
|
||||
; CHECK: for.body.backedge:
|
||||
; CHECK: br label %Flow3
|
||||
for.body.backedge: ; preds = %if.then6.6, %for.body.6
|
||||
%best_val.027.be = phi float [ %tmp29, %if.then6.6 ], [ %best_val.233, %for.body.6 ]
|
||||
%best_count.025.be = phi i32 [ %sub4.6, %if.then6.6 ], [ %best_count.231, %for.body.6 ]
|
||||
%indvars.iv.be = add nsw i64 %indvars.iv, 7
|
||||
br label %for.body
|
||||
}
|
||||
@ -1,56 +0,0 @@
|
||||
; RUN: opt -o /dev/null -structurizecfg %s
|
||||
|
||||
; The following function caused an infinite loop inside the structurizer's
|
||||
; rebuildSSA routine, where we were iterating over an instruction's uses while
|
||||
; modifying the use list, without taking care to do this safely.
|
||||
|
||||
target triple = "amdgcn--"
|
||||
|
||||
define amdgpu_vs void @wrapper(i32 inreg %arg, i32 %arg1) {
|
||||
main_body:
|
||||
%tmp = add i32 %arg1, %arg
|
||||
%tmp2 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %tmp, i32 0, i1 false, i1 false)
|
||||
%tmp3 = extractelement <4 x float> %tmp2, i32 1
|
||||
%tmp4 = fptosi float %tmp3 to i32
|
||||
%tmp5 = insertelement <2 x i32> undef, i32 %tmp4, i32 1
|
||||
br label %loop11.i
|
||||
|
||||
loop11.i: ; preds = %endif46.i, %main_body
|
||||
%tmp6 = phi i32 [ 0, %main_body ], [ %tmp14, %endif46.i ]
|
||||
%tmp7 = icmp sgt i32 %tmp6, 999
|
||||
br i1 %tmp7, label %main.exit, label %if16.i
|
||||
|
||||
if16.i: ; preds = %loop11.i
|
||||
%tmp8 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp5, <8 x i32> undef, i32 15, i1 true, i1 false, i1 false, i1 false)
|
||||
%tmp9 = extractelement <4 x float> %tmp8, i32 0
|
||||
%tmp10 = fcmp ult float 0.000000e+00, %tmp9
|
||||
br i1 %tmp10, label %if28.i, label %endif46.i
|
||||
|
||||
if28.i: ; preds = %if16.i
|
||||
%tmp11 = bitcast float %tmp9 to i32
|
||||
%tmp12 = shl i32 %tmp11, 16
|
||||
%tmp13 = bitcast i32 %tmp12 to float
|
||||
br label %main.exit
|
||||
|
||||
endif46.i: ; preds = %if16.i
|
||||
%tmp14 = add i32 %tmp6, 1
|
||||
br label %loop11.i
|
||||
|
||||
main.exit: ; preds = %if28.i, %loop11.i
|
||||
%tmp15 = phi float [ %tmp13, %if28.i ], [ 0x36F0800000000000, %loop11.i ]
|
||||
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp15, float 0.000000e+00, float 0.000000e+00, float 0x36A0000000000000, i1 false, i1 false) #0
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
|
||||
|
||||
; Function Attrs: nounwind readonly
|
||||
declare <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
attributes #2 = { nounwind readonly }
|
||||
@ -1,23 +0,0 @@
|
||||
; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
|
||||
|
||||
; The structurizecfg pass cannot handle switch instructions, so we need to
|
||||
; make sure the lower switch pass is always run before structurizecfg.
|
||||
|
||||
; CHECK-LABEL: @switch
|
||||
define void @switch(i32 addrspace(1)* %out, i32 %cond) nounwind {
|
||||
entry:
|
||||
; CHECK: icmp
|
||||
switch i32 %cond, label %done [ i32 0, label %zero]
|
||||
|
||||
; CHECK: zero:
|
||||
zero:
|
||||
; CHECK: store i32 7, i32 addrspace(1)* %out
|
||||
store i32 7, i32 addrspace(1)* %out
|
||||
; CHECK: br label %done
|
||||
br label %done
|
||||
|
||||
; CHECK: done:
|
||||
done:
|
||||
; CHECK: ret void
|
||||
ret void
|
||||
}
|
||||
Reference in New Issue
Block a user