Imported Upstream version 5.18.0.167

Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a

external/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/lit.local.cfg

@@ -1,2 +0,0 @@
-if not 'NVPTX' in config.root.targets:
-    config.unsupported = True

external/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll

@@ -1,74 +0,0 @@
-; RUN: opt < %s -separate-const-offset-from-gep -slsr -gvn -S | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
-
-target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
-target triple = "nvptx64-unknown-unknown"
-
-; arr[i + 5]
-; arr[i * 2 + 5]
-; arr[i * 3 + 5]
-; arr[i * 4 + 5]
-;
-;   => reassociate-geps
-;
-; *(&arr[i] + 5)
-; *(&arr[i * 2] + 5)
-; *(&arr[i * 3] + 5)
-; *(&arr[i * 4] + 5)
-;
-;   => slsr
-;
-; p1 = &arr[i]
-; *(p1 + 5)
-; p2 = p1 + i
-; *(p2 + 5)
-; p3 = p2 + i
-; *(p3 + 5)
-; p4 = p3 + i
-; *(p4 + 5)
-define void @slsr_after_reassociate_geps(float* %arr, i32 %i) {
-; CHECK-LABEL: @slsr_after_reassociate_geps(
-; PTX-LABEL: .visible .func slsr_after_reassociate_geps(
-; PTX: ld.param.u64 [[arr:%rd[0-9]+]], [slsr_after_reassociate_geps_param_0];
-; PTX: ld.param.u32 [[i:%r[0-9]+]], [slsr_after_reassociate_geps_param_1];
-  %i2 = shl nsw i32 %i, 1
-  %i3 = mul nsw i32 %i, 3
-  %i4 = shl nsw i32 %i, 2
-
-  %j1 = add nsw i32 %i, 5
-  %p1 = getelementptr inbounds float, float* %arr, i32 %j1
-; CHECK: [[b1:%[0-9]+]] = getelementptr float, float* %arr, i64 [[bump:%[0-9]+]]
-; PTX: mul.wide.s32 [[i4:%rd[0-9]+]], [[i]], 4;
-; PTX: add.s64 [[base1:%rd[0-9]+]], [[arr]], [[i4]];
-  %v1 = load float, float* %p1, align 4
-; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base1]]+20];
-  call void @foo(float %v1)
-
-  %j2 = add nsw i32 %i2, 5
-  %p2 = getelementptr inbounds float, float* %arr, i32 %j2
-; CHECK: [[b2:%[0-9]+]] = getelementptr float, float* [[b1]], i64 [[bump]]
-; PTX: add.s64 [[base2:%rd[0-9]+]], [[base1]], [[i4]];
-  %v2 = load float, float* %p2, align 4
-; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base2]]+20];
-  call void @foo(float %v2)
-
-  %j3 = add nsw i32 %i3, 5
-  %p3 = getelementptr inbounds float, float* %arr, i32 %j3
-; CHECK: [[b3:%[0-9]+]] = getelementptr float, float* [[b2]], i64 [[bump]]
-; PTX: add.s64 [[base3:%rd[0-9]+]], [[base2]], [[i4]];
-  %v3 = load float, float* %p3, align 4
-; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base3]]+20];
-  call void @foo(float %v3)
-
-  %j4 = add nsw i32 %i4, 5
-  %p4 = getelementptr inbounds float, float* %arr, i32 %j4
-; CHECK: [[b4:%[0-9]+]] = getelementptr float, float* [[b3]], i64 [[bump]]
-; PTX: add.s64 [[base4:%rd[0-9]+]], [[base3]], [[i4]];
-  %v4 = load float, float* %p4, align 4
-; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base4]]+20];
-  call void @foo(float %v4)
-
-  ret void
-}
-
-declare void @foo(float)

external/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll

@@ -1,71 +0,0 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
-
-target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
-target triple = "nvptx64-nvidia-cuda"
-
-; CUDA code
-; __global__ void foo(int b, int s) {
-;   #pragma unroll
-;   for (int i = 0; i < 4; ++i) {
-;     if (cond(i))
-;       use((b + i) * s);
-;   }
-; }
-define void @foo(i32 %b, i32 %s) {
-; CHECK-LABEL: .visible .entry foo(
-entry:
-; CHECK: ld.param.u32 [[s:%r[0-9]+]], [foo_param_1];
-; CHECK: ld.param.u32 [[b:%r[0-9]+]], [foo_param_0];
-  %call = tail call zeroext i1 @cond(i32 0)
-  br i1 %call, label %if.then, label %for.inc
-
-if.then:                                          ; preds = %entry
-  %mul = mul nsw i32 %b, %s
-; CHECK: mul.lo.s32 [[a0:%r[0-9]+]], [[b]], [[s]]
-  tail call void @use(i32 %mul)
-  br label %for.inc
-
-for.inc:                                          ; preds = %entry, %if.then
-  %call.1 = tail call zeroext i1 @cond(i32 1)
-  br i1 %call.1, label %if.then.1, label %for.inc.1
-
-if.then.1:                                        ; preds = %for.inc
-  %add.1 = add nsw i32 %b, 1
-  %mul.1 = mul nsw i32 %add.1, %s
-; CHECK: add.s32 [[a1:%r[0-9]+]], [[a0]], [[s]]
-  tail call void @use(i32 %mul.1)
-  br label %for.inc.1
-
-for.inc.1:                                        ; preds = %if.then.1, %for.inc
-  %call.2 = tail call zeroext i1 @cond(i32 2)
-  br i1 %call.2, label %if.then.2, label %for.inc.2
-
-if.then.2:                                        ; preds = %for.inc.1
-  %add.2 = add nsw i32 %b, 2
-  %mul.2 = mul nsw i32 %add.2, %s
-; CHECK: add.s32 [[a2:%r[0-9]+]], [[a1]], [[s]]
-  tail call void @use(i32 %mul.2)
-  br label %for.inc.2
-
-for.inc.2:                                        ; preds = %if.then.2, %for.inc.1
-  %call.3 = tail call zeroext i1 @cond(i32 3)
-  br i1 %call.3, label %if.then.3, label %for.inc.3
-
-if.then.3:                                        ; preds = %for.inc.2
-  %add.3 = add nsw i32 %b, 3
-  %mul.3 = mul nsw i32 %add.3, %s
-; CHECK: add.s32 [[a3:%r[0-9]+]], [[a2]], [[s]]
-  tail call void @use(i32 %mul.3)
-  br label %for.inc.3
-
-for.inc.3:                                        ; preds = %if.then.3, %for.inc.2
-  ret void
-}
-
-declare zeroext i1 @cond(i32)
-
-declare void @use(i32)
-
-!nvvm.annotations = !{!0}
-
-!0 = !{void (i32, i32)* @foo, !"kernel", i32 1}