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Imported Upstream version 5.18.0.167
Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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@ -1,2 +0,0 @@
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if not 'AMDGPU' in config.root.targets:
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config.unsupported = True
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@ -1,20 +0,0 @@
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; RUN: opt < %s -slsr -S | FileCheck %s
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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target triple = "amdgcn--"
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%struct.Matrix4x4 = type { [4 x [4 x float]] }
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; Function Attrs: nounwind
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define fastcc void @Accelerator_Intersect(%struct.Matrix4x4 addrspace(1)* nocapture readonly %leafTransformations) #0 {
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; CHECK-LABEL: @Accelerator_Intersect(
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entry:
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%tmp = sext i32 undef to i64
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%arrayidx114 = getelementptr inbounds %struct.Matrix4x4, %struct.Matrix4x4 addrspace(1)* %leafTransformations, i64 %tmp
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%tmp1 = getelementptr %struct.Matrix4x4, %struct.Matrix4x4 addrspace(1)* %leafTransformations, i64 %tmp, i32 0, i64 0, i64 0
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; CHECK: %tmp1 = getelementptr %struct.Matrix4x4, %struct.Matrix4x4 addrspace(1)* %leafTransformations, i64 %tmp, i32 0, i64 0, i64 0
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%tmp2 = load <4 x float>, <4 x float> addrspace(1)* undef, align 4
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ret void
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}
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attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "target-cpu"="tahiti" "unsafe-fp-math"="false" "use-soft-float"="false" }
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@ -1,107 +0,0 @@
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; RUN: opt -S -mtriple=amdgcn-- -separate-const-offset-from-gep -slsr -gvn < %s | FileCheck %s
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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; CHECK-LABEL: @slsr_after_reassociate_global_geps_mubuf_max_offset(
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; CHECK: [[b1:%[0-9]+]] = getelementptr float, float addrspace(1)* %arr, i64 [[bump:%[0-9]+]]
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; CHECK: [[b2:%[0-9]+]] = getelementptr float, float addrspace(1)* [[b1]], i64 [[bump]]
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define amdgpu_kernel void @slsr_after_reassociate_global_geps_mubuf_max_offset(float addrspace(1)* %out, float addrspace(1)* noalias %arr, i32 %i) {
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bb:
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%i2 = shl nsw i32 %i, 1
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%j1 = add nsw i32 %i, 1023
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%tmp = sext i32 %j1 to i64
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%p1 = getelementptr inbounds float, float addrspace(1)* %arr, i64 %tmp
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%tmp3 = bitcast float addrspace(1)* %p1 to i32 addrspace(1)*
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%v11 = load i32, i32 addrspace(1)* %tmp3, align 4
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%tmp4 = bitcast float addrspace(1)* %out to i32 addrspace(1)*
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store i32 %v11, i32 addrspace(1)* %tmp4, align 4
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%j2 = add nsw i32 %i2, 1023
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%tmp5 = sext i32 %j2 to i64
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%p2 = getelementptr inbounds float, float addrspace(1)* %arr, i64 %tmp5
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%tmp6 = bitcast float addrspace(1)* %p2 to i32 addrspace(1)*
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%v22 = load i32, i32 addrspace(1)* %tmp6, align 4
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%tmp7 = bitcast float addrspace(1)* %out to i32 addrspace(1)*
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store i32 %v22, i32 addrspace(1)* %tmp7, align 4
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ret void
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}
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; CHECK-LABEL: @slsr_after_reassociate_global_geps_over_mubuf_max_offset(
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; CHECK: %j1 = add nsw i32 %i, 1024
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; CHECK: %tmp = sext i32 %j1 to i64
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; CHECK: getelementptr inbounds float, float addrspace(1)* %arr, i64 %tmp
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; CHECK: getelementptr inbounds float, float addrspace(1)* %arr, i64 %tmp5
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define amdgpu_kernel void @slsr_after_reassociate_global_geps_over_mubuf_max_offset(float addrspace(1)* %out, float addrspace(1)* noalias %arr, i32 %i) {
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bb:
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%i2 = shl nsw i32 %i, 1
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%j1 = add nsw i32 %i, 1024
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%tmp = sext i32 %j1 to i64
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%p1 = getelementptr inbounds float, float addrspace(1)* %arr, i64 %tmp
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%tmp3 = bitcast float addrspace(1)* %p1 to i32 addrspace(1)*
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%v11 = load i32, i32 addrspace(1)* %tmp3, align 4
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%tmp4 = bitcast float addrspace(1)* %out to i32 addrspace(1)*
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store i32 %v11, i32 addrspace(1)* %tmp4, align 4
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%j2 = add nsw i32 %i2, 1024
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%tmp5 = sext i32 %j2 to i64
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%p2 = getelementptr inbounds float, float addrspace(1)* %arr, i64 %tmp5
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%tmp6 = bitcast float addrspace(1)* %p2 to i32 addrspace(1)*
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%v22 = load i32, i32 addrspace(1)* %tmp6, align 4
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%tmp7 = bitcast float addrspace(1)* %out to i32 addrspace(1)*
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store i32 %v22, i32 addrspace(1)* %tmp7, align 4
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ret void
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}
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; CHECK-LABEL: @slsr_after_reassociate_lds_geps_ds_max_offset(
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; CHECK: [[B1:%[0-9]+]] = getelementptr float, float addrspace(3)* %arr, i32 %i
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; CHECK: getelementptr inbounds float, float addrspace(3)* [[B1]], i32 16383
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; CHECK: [[B2:%[0-9]+]] = getelementptr float, float addrspace(3)* [[B1]], i32 %i
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; CHECK: getelementptr inbounds float, float addrspace(3)* [[B2]], i32 16383
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define amdgpu_kernel void @slsr_after_reassociate_lds_geps_ds_max_offset(float addrspace(1)* %out, float addrspace(3)* noalias %arr, i32 %i) {
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bb:
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%i2 = shl nsw i32 %i, 1
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%j1 = add nsw i32 %i, 16383
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%p1 = getelementptr inbounds float, float addrspace(3)* %arr, i32 %j1
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%tmp3 = bitcast float addrspace(3)* %p1 to i32 addrspace(3)*
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%v11 = load i32, i32 addrspace(3)* %tmp3, align 4
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%tmp4 = bitcast float addrspace(1)* %out to i32 addrspace(1)*
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store i32 %v11, i32 addrspace(1)* %tmp4, align 4
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%j2 = add nsw i32 %i2, 16383
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%p2 = getelementptr inbounds float, float addrspace(3)* %arr, i32 %j2
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%tmp6 = bitcast float addrspace(3)* %p2 to i32 addrspace(3)*
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%v22 = load i32, i32 addrspace(3)* %tmp6, align 4
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%tmp7 = bitcast float addrspace(1)* %out to i32 addrspace(1)*
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store i32 %v22, i32 addrspace(1)* %tmp7, align 4
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ret void
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}
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; CHECK-LABEL: @slsr_after_reassociate_lds_geps_over_ds_max_offset(
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; CHECK: %j1 = add nsw i32 %i, 16384
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; CHECK: getelementptr inbounds float, float addrspace(3)* %arr, i32 %j1
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; CHECK: %j2 = add i32 %j1, %i
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; CHECK: getelementptr inbounds float, float addrspace(3)* %arr, i32 %j2
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define amdgpu_kernel void @slsr_after_reassociate_lds_geps_over_ds_max_offset(float addrspace(1)* %out, float addrspace(3)* noalias %arr, i32 %i) {
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bb:
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%i2 = shl nsw i32 %i, 1
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%j1 = add nsw i32 %i, 16384
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%p1 = getelementptr inbounds float, float addrspace(3)* %arr, i32 %j1
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%tmp3 = bitcast float addrspace(3)* %p1 to i32 addrspace(3)*
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%v11 = load i32, i32 addrspace(3)* %tmp3, align 4
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%tmp4 = bitcast float addrspace(1)* %out to i32 addrspace(1)*
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store i32 %v11, i32 addrspace(1)* %tmp4, align 4
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%j2 = add nsw i32 %i2, 16384
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%p2 = getelementptr inbounds float, float addrspace(3)* %arr, i32 %j2
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%tmp6 = bitcast float addrspace(3)* %p2 to i32 addrspace(3)*
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%v22 = load i32, i32 addrspace(3)* %tmp6, align 4
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%tmp7 = bitcast float addrspace(1)* %out to i32 addrspace(1)*
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store i32 %v22, i32 addrspace(1)* %tmp7, align 4
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ret void
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}
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