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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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4
external/llvm/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg vendored
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config.suffixes = ['.ll']
if not 'AArch64' in config.root.targets:
config.unsupported = True

33
external/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll vendored
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@ -1,33 +0,0 @@
; RUN: llc -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s
; rdar://10232252
; Prevent LSR of doing poor choice that cannot be folded in addressing mode
; Remove the -pre-RA-sched=list-hybrid option after fixing:
; <rdar://problem/12702735> [ARM64][coalescer] need better register
; coalescing for simple unit tests.
; CHECK: testCase
; CHECK: %while.body{{$}}
; CHECK: ldr [[STREG:x[0-9]+]], [{{x[0-9]+}}], #8
; CHECK-NEXT: str [[STREG]], [{{x[0-9]+}}], #8
; CHECK: %while.end
define i32 @testCase() nounwind ssp {
entry:
br label %while.body
while.body: ; preds = %while.body, %entry
%len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ]
%pDst.05 = phi i64* [ inttoptr (i64 6442450944 to i64*), %entry ], [ %incdec.ptr1, %while.body ]
%pSrc.04 = phi i64* [ inttoptr (i64 4294967296 to i64*), %entry ], [ %incdec.ptr, %while.body ]
%incdec.ptr = getelementptr inbounds i64, i64* %pSrc.04, i64 1
%tmp = load volatile i64, i64* %pSrc.04, align 8
%incdec.ptr1 = getelementptr inbounds i64, i64* %pDst.05, i64 1
store volatile i64 %tmp, i64* %pDst.05, align 8
%sub = add i64 %len.06, -8
%cmp = icmp sgt i64 %sub, -1
br i1 %cmp, label %while.body, label %while.end
while.end: ; preds = %while.body
tail call void inttoptr (i64 6442450944 to void ()*)() nounwind
ret i32 0
}

101
external/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll vendored
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@ -1,101 +0,0 @@
; RUN: llc < %s -O3 -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid | FileCheck %s
; <rdar://problem/11635990> [arm64] [lsr] Inefficient EA/loop-exit calc in bzero_phys
;
; LSR on loop %while.cond should reassociate non-address mode
; expressions at use %cmp16 to avoid sinking computation into %while.body18.
;
; Remove the -pre-RA-sched=list-hybrid option after fixing:
; <rdar://problem/12702735> [ARM64][coalescer] need better register
; coalescing for simple unit tests.
; CHECK: @memset
; CHECK: %while.body18{{$}}
; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #8
; First set the IVREG variable, then use it
; CHECK-NEXT: sub [[IVREG:x[0-9]+]],
; CHECK: [[IVREG]], #8
; CHECK-NEXT: cmp [[IVREG]], #7
; CHECK-NEXT: b.hi
define i8* @memset(i8* %dest, i32 %val, i64 %len) nounwind ssp noimplicitfloat {
entry:
%cmp = icmp eq i64 %len, 0
br i1 %cmp, label %done, label %while.cond.preheader
while.cond.preheader: ; preds = %entry
%conv = trunc i32 %val to i8
br label %while.cond
while.cond: ; preds = %while.body, %while.cond.preheader
%ptr.0 = phi i8* [ %incdec.ptr, %while.body ], [ %dest, %while.cond.preheader ]
%len.addr.0 = phi i64 [ %dec, %while.body ], [ %len, %while.cond.preheader ]
%cond = icmp eq i64 %len.addr.0, 0
br i1 %cond, label %done, label %land.rhs
land.rhs: ; preds = %while.cond
%0 = ptrtoint i8* %ptr.0 to i64
%and = and i64 %0, 7
%cmp5 = icmp eq i64 %and, 0
br i1 %cmp5, label %if.end9, label %while.body
while.body: ; preds = %land.rhs
%incdec.ptr = getelementptr inbounds i8, i8* %ptr.0, i64 1
store i8 %conv, i8* %ptr.0, align 1, !tbaa !0
%dec = add i64 %len.addr.0, -1
br label %while.cond
if.end9: ; preds = %land.rhs
%conv.mask = and i32 %val, 255
%1 = zext i32 %conv.mask to i64
%2 = shl nuw nsw i64 %1, 8
%ins18 = or i64 %2, %1
%3 = shl nuw nsw i64 %1, 16
%ins15 = or i64 %ins18, %3
%4 = shl nuw nsw i64 %1, 24
%5 = shl nuw nsw i64 %1, 32
%mask8 = or i64 %ins15, %4
%6 = shl nuw nsw i64 %1, 40
%mask5 = or i64 %mask8, %5
%7 = shl nuw nsw i64 %1, 48
%8 = shl nuw i64 %1, 56
%mask2.masked = or i64 %mask5, %6
%mask = or i64 %mask2.masked, %7
%ins = or i64 %mask, %8
%9 = bitcast i8* %ptr.0 to i64*
%cmp1636 = icmp ugt i64 %len.addr.0, 7
br i1 %cmp1636, label %while.body18, label %while.body29.lr.ph
while.body18: ; preds = %if.end9, %while.body18
%wideptr.038 = phi i64* [ %incdec.ptr19, %while.body18 ], [ %9, %if.end9 ]
%len.addr.137 = phi i64 [ %sub, %while.body18 ], [ %len.addr.0, %if.end9 ]
%incdec.ptr19 = getelementptr inbounds i64, i64* %wideptr.038, i64 1
store i64 %ins, i64* %wideptr.038, align 8, !tbaa !2
%sub = add i64 %len.addr.137, -8
%cmp16 = icmp ugt i64 %sub, 7
br i1 %cmp16, label %while.body18, label %while.end20
while.end20: ; preds = %while.body18
%cmp21 = icmp eq i64 %sub, 0
br i1 %cmp21, label %done, label %while.body29.lr.ph
while.body29.lr.ph: ; preds = %while.end20, %if.end9
%len.addr.1.lcssa49 = phi i64 [ %sub, %while.end20 ], [ %len.addr.0, %if.end9 ]
%wideptr.0.lcssa48 = phi i64* [ %incdec.ptr19, %while.end20 ], [ %9, %if.end9 ]
%10 = bitcast i64* %wideptr.0.lcssa48 to i8*
br label %while.body29
while.body29: ; preds = %while.body29, %while.body29.lr.ph
%len.addr.235 = phi i64 [ %len.addr.1.lcssa49, %while.body29.lr.ph ], [ %dec26, %while.body29 ]
%ptr.134 = phi i8* [ %10, %while.body29.lr.ph ], [ %incdec.ptr31, %while.body29 ]
%dec26 = add i64 %len.addr.235, -1
%incdec.ptr31 = getelementptr inbounds i8, i8* %ptr.134, i64 1
store i8 %conv, i8* %ptr.134, align 1, !tbaa !0
%cmp27 = icmp eq i64 %dec26, 0
br i1 %cmp27, label %done, label %while.body29
done: ; preds = %while.cond, %while.body29, %while.end20, %entry
ret i8* %dest
}
!0 = !{!"omnipotent char", !1}
!1 = !{!"Simple C/C++ TBAA"}
!2 = !{!"long long", !0}

34
external/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-reuse.ll vendored
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@ -1,34 +0,0 @@
; RUN: llc -mtriple=arm64-unknown-unknown -print-lsr-output < %s 2>&1 | FileCheck %s
declare void @foo(i64)
; Verify that redundant adds aren't inserted by LSR.
; CHECK-LABEL: @bar(
define void @bar(double* %A) {
entry:
br label %while.cond
while.cond:
; CHECK-LABEL: while.cond:
; CHECK: add i64 %lsr.iv, 1
; CHECK-NOT: add i64 %lsr.iv, 1
; CHECK-LABEL: land.rhs:
%indvars.iv28 = phi i64 [ %indvars.iv.next29, %land.rhs ], [ 50, %entry ]
%cmp = icmp sgt i64 %indvars.iv28, 0
br i1 %cmp, label %land.rhs, label %while.end
land.rhs:
%indvars.iv.next29 = add nsw i64 %indvars.iv28, -1
%arrayidx = getelementptr inbounds double, double* %A, i64 %indvars.iv.next29
%Aload = load double, double* %arrayidx, align 8
%cmp1 = fcmp oeq double %Aload, 0.000000e+00
br i1 %cmp1, label %while.cond, label %if.end
while.end:
%indvars.iv28.lcssa = phi i64 [ %indvars.iv28, %while.cond ]
tail call void @foo(i64 %indvars.iv28.lcssa)
br label %if.end
if.end:
ret void
}

70
external/llvm/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll vendored
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@ -1,70 +0,0 @@
; RUN: llc -mcpu=cyclone -debug-only=loop-reduce < %s 2>&1 | FileCheck %s
; REQUIRES: asserts
; LSR used to fail here due to a bug in the ReqRegs test.
; CHECK: The chosen solution requires
; CHECK-NOT: No Satisfactory Solution
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios"
define void @do_integer_add(i64 %iterations, i8* nocapture readonly %cookie) {
entry:
%N = bitcast i8* %cookie to i32*
%0 = load i32, i32* %N, align 4
%add = add nsw i32 %0, 57
%cmp56 = icmp eq i64 %iterations, 0
br i1 %cmp56, label %while.end, label %for.cond.preheader.preheader
for.cond.preheader.preheader: ; preds = %entry
br label %for.cond.preheader
while.cond.loopexit: ; preds = %for.body
%add21.lcssa = phi i32 [ %add21, %for.body ]
%dec58 = add i64 %dec58.in, -1
%cmp = icmp eq i64 %dec58, 0
br i1 %cmp, label %while.end.loopexit, label %for.cond.preheader
for.cond.preheader: ; preds = %for.cond.preheader.preheader, %while.cond.loopexit
%dec58.in = phi i64 [ %dec58, %while.cond.loopexit ], [ %iterations, %for.cond.preheader.preheader ]
%a.057 = phi i32 [ %add21.lcssa, %while.cond.loopexit ], [ %add, %for.cond.preheader.preheader ]
br label %for.body
for.body: ; preds = %for.body, %for.cond.preheader
%a.154 = phi i32 [ %a.057, %for.cond.preheader ], [ %add21, %for.body ]
%i.053 = phi i32 [ 1, %for.cond.preheader ], [ %inc, %for.body ]
%inc = add nsw i32 %i.053, 1
%add2 = shl i32 %a.154, 1
%add3 = add nsw i32 %add2, %i.053
%add4 = shl i32 %add3, 1
%add5 = add nsw i32 %add4, %i.053
%add6 = shl i32 %add5, 1
%add7 = add nsw i32 %add6, %i.053
%add8 = shl i32 %add7, 1
%add9 = add nsw i32 %add8, %i.053
%add10 = shl i32 %add9, 1
%add11 = add nsw i32 %add10, %i.053
%add12 = shl i32 %add11, 1
%add13 = add nsw i32 %add12, %i.053
%add14 = shl i32 %add13, 1
%add15 = add nsw i32 %add14, %i.053
%add16 = shl i32 %add15, 1
%add17 = add nsw i32 %add16, %i.053
%add18 = shl i32 %add17, 1
%add19 = add nsw i32 %add18, %i.053
%add20 = shl i32 %add19, 1
%add21 = add nsw i32 %add20, %i.053
%exitcond = icmp eq i32 %inc, 1001
br i1 %exitcond, label %while.cond.loopexit, label %for.body
while.end.loopexit: ; preds = %while.cond.loopexit
%add21.lcssa.lcssa = phi i32 [ %add21.lcssa, %while.cond.loopexit ]
br label %while.end
while.end: ; preds = %while.end.loopexit, %entry
%a.0.lcssa = phi i32 [ %add, %entry ], [ %add21.lcssa.lcssa, %while.end.loopexit ]
tail call void @use_int(i32 %a.0.lcssa)
ret void
}
declare void @use_int(i32)