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Imported Upstream version 5.18.0.167
Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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@ -1,35 +0,0 @@
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; RUN: opt -S -codegenprepare < %s | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; When we bypass slow div with a constant numerator which fits into the bypass
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; width, we still emit the bypass code, but we don't 'or' the numerator with
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; the denominator.
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; CHECK-LABEL: @small_constant_numer
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define i64 @small_constant_numer(i64 %a) {
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; CHECK: [[AND:%[0-9]+]] = and i64 %a, -4294967296
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; CHECK: icmp eq i64 [[AND]], 0
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; CHECK: [[TRUNC:%[0-9]+]] = trunc i64 %a to i32
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; CHECK: udiv i32 -1, [[TRUNC]]
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%d = sdiv i64 4294967295, %a ; 0xffff'ffff
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ret i64 %d
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}
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; When we try to bypass slow div with a constant numerator which *doesn't* fit
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; into the bypass width, leave it as a plain 64-bit div with no bypass.
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; CHECK-LABEL: @large_constant_numer
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define i64 @large_constant_numer(i64 %a) {
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; CHECK-NOT: udiv i32
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%d = sdiv i64 4294967296, %a ; 0x1'0000'0000
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ret i64 %d
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}
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; For good measure, try a value larger than 2^32.
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; CHECK-LABEL: @larger_constant_numer
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define i64 @larger_constant_numer(i64 %a) {
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; CHECK-NOT: udiv i32
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%d = sdiv i64 5000000000, %a
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ret i64 %d
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}
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@ -1,16 +0,0 @@
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; RUN: opt -S -codegenprepare < %s | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; Check that the smaller-width division that the BypassSlowDivision pass
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; creates is not marked as "exact" (that is, it doesn't claim that the
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; numerator is a multiple of the denominator).
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;
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; CHECK-LABEL: @test
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define void @test(i64 %a, i64 %b, i64* %retptr) {
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; CHECK: udiv i32
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%d = sdiv i64 %a, %b
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store i64 %d, i64* %retptr
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ret void
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}
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@ -1,216 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -codegenprepare < %s | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; No bypassing should be done in apparently unsuitable cases.
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define void @Test_no_bypassing(i32 %a, i64 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_no_bypassing(
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; CHECK-NEXT: [[A_1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[A_2:%.*]] = sub i64 -1, [[A_1]]
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; CHECK-NEXT: [[RES:%.*]] = srem i64 [[A_2]], [[B:%.*]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%a.1 = zext i32 %a to i64
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; %a.2 is always negative so the division cannot be bypassed.
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%a.2 = sub i64 -1, %a.1
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%res = srem i64 %a.2, %b
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store i64 %res, i64* %retptr
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ret void
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}
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; No OR instruction is needed if one of the operands (divisor) is known
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; to fit into 32 bits.
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define void @Test_check_one_operand(i64 %a, i32 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_check_one_operand(
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; CHECK-NEXT: [[B_1:%.*]] = zext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A:%.*]], -4294967296
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP8:%.*]]
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; CHECK: [[TMP4:%.*]] = trunc i64 [[B_1]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[A]] to i32
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; CHECK-NEXT: [[TMP6:%.*]] = udiv i32 [[TMP5]], [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
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; CHECK-NEXT: br label [[TMP10:%.*]]
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; CHECK: [[TMP9:%.*]] = sdiv i64 [[A]], [[B_1]]
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; CHECK-NEXT: br label [[TMP10]]
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; CHECK: [[TMP11:%.*]] = phi i64 [ [[TMP7]], [[TMP3]] ], [ [[TMP9]], [[TMP8]] ]
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; CHECK-NEXT: store i64 [[TMP11]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%b.1 = zext i32 %b to i64
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%res = sdiv i64 %a, %b.1
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store i64 %res, i64* %retptr
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ret void
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}
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; If both operands are known to fit into 32 bits, then replace the division
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; in-place without CFG modification.
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define void @Test_check_none(i64 %a, i32 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_check_none(
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; CHECK-NEXT: [[A_1:%.*]] = and i64 [[A:%.*]], 4294967295
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; CHECK-NEXT: [[B_1:%.*]] = zext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A_1]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[B_1]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = udiv i32 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: store i64 [[TMP4]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%a.1 = and i64 %a, 4294967295
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%b.1 = zext i32 %b to i64
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%res = udiv i64 %a.1, %b.1
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store i64 %res, i64* %retptr
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ret void
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}
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; In case of unsigned long division with a short dividend,
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; the long division is not needed any more.
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define void @Test_special_case(i32 %a, i64 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_special_case(
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; CHECK-NEXT: [[A_1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[A_1]], [[B:%.*]]
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; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP9:%.*]]
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; CHECK: [[TMP3:%.*]] = trunc i64 [[B]] to i32
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[A_1]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = udiv i32 [[TMP4]], [[TMP3]]
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; CHECK-NEXT: [[TMP6:%.*]] = urem i32 [[TMP4]], [[TMP3]]
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; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP5]] to i64
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; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP6]] to i64
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; CHECK-NEXT: br label [[TMP9]]
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; CHECK: [[TMP10:%.*]] = phi i64 [ [[TMP7]], [[TMP2]] ], [ 0, [[TMP0:%.*]] ]
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; CHECK-NEXT: [[TMP11:%.*]] = phi i64 [ [[TMP8]], [[TMP2]] ], [ [[A_1]], [[TMP0]] ]
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; CHECK-NEXT: [[RES:%.*]] = add i64 [[TMP10]], [[TMP11]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%a.1 = zext i32 %a to i64
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%div = udiv i64 %a.1, %b
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%rem = urem i64 %a.1, %b
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%res = add i64 %div, %rem
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store i64 %res, i64* %retptr
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ret void
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}
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; Do not bypass a division if one of the operands looks like a hash value.
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define void @Test_dont_bypass_xor(i64 %a, i64 %b, i64 %l, i64* %retptr) {
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; CHECK-LABEL: @Test_dont_bypass_xor(
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; CHECK-NEXT: [[C:%.*]] = xor i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[RES:%.*]] = udiv i64 [[C]], [[L:%.*]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%c = xor i64 %a, %b
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%res = udiv i64 %c, %l
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store i64 %res, i64* %retptr
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ret void
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}
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define void @Test_dont_bypass_phi_xor(i64 %a, i64 %b, i64 %l, i64* %retptr) {
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; CHECK-LABEL: @Test_dont_bypass_phi_xor(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[B:%.*]], 0
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; CHECK-NEXT: br i1 [[CMP]], label [[MERGE:%.*]], label [[XORPATH:%.*]]
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; CHECK: xorpath:
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; CHECK-NEXT: [[C:%.*]] = xor i64 [[A:%.*]], [[B]]
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; CHECK-NEXT: br label [[MERGE]]
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; CHECK: merge:
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; CHECK-NEXT: [[E:%.*]] = phi i64 [ undef, [[ENTRY:%.*]] ], [ [[C]], [[XORPATH]] ]
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; CHECK-NEXT: [[RES:%.*]] = sdiv i64 [[E]], [[L:%.*]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp = icmp eq i64 %b, 0
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br i1 %cmp, label %merge, label %xorpath
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xorpath:
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%c = xor i64 %a, %b
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br label %merge
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merge:
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%e = phi i64 [ undef, %entry ], [ %c, %xorpath ]
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%res = sdiv i64 %e, %l
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store i64 %res, i64* %retptr
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ret void
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}
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define void @Test_dont_bypass_mul_long_const(i64 %a, i64 %l, i64* %retptr) {
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; CHECK-LABEL: @Test_dont_bypass_mul_long_const(
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; CHECK-NEXT: [[C:%.*]] = mul i64 [[A:%.*]], 5229553307
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; CHECK-NEXT: [[RES:%.*]] = urem i64 [[C]], [[L:%.*]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%c = mul i64 %a, 5229553307 ; the constant doesn't fit 32 bits
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%res = urem i64 %c, %l
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store i64 %res, i64* %retptr
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ret void
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}
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define void @Test_bypass_phi_mul_const(i64 %a, i64 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_bypass_phi_mul_const(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A_MUL:%.*]] = mul nsw i64 [[A:%.*]], 34806414968801
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; CHECK-NEXT: [[P:%.*]] = icmp sgt i64 [[A]], [[B:%.*]]
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; CHECK-NEXT: br i1 [[P]], label [[BRANCH:%.*]], label [[MERGE:%.*]]
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; CHECK: branch:
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; CHECK-NEXT: br label [[MERGE]]
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; CHECK: merge:
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; CHECK-NEXT: [[LHS:%.*]] = phi i64 [ 42, [[BRANCH]] ], [ [[A_MUL]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = or i64 [[LHS]], [[B]]
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; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], -4294967296
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP8:%.*]]
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; CHECK: [[TMP4:%.*]] = trunc i64 [[B]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[LHS]] to i32
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; CHECK-NEXT: [[TMP6:%.*]] = udiv i32 [[TMP5]], [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
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; CHECK-NEXT: br label [[TMP10:%.*]]
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; CHECK: [[TMP9:%.*]] = sdiv i64 [[LHS]], [[B]]
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; CHECK-NEXT: br label [[TMP10]]
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; CHECK: [[TMP11:%.*]] = phi i64 [ [[TMP7]], [[TMP3]] ], [ [[TMP9]], [[TMP8]] ]
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; CHECK-NEXT: store i64 [[TMP11]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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entry:
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%a.mul = mul nsw i64 %a, 34806414968801
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%p = icmp sgt i64 %a, %b
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br i1 %p, label %branch, label %merge
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branch:
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br label %merge
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merge:
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%lhs = phi i64 [ 42, %branch ], [ %a.mul, %entry ]
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%res = sdiv i64 %lhs, %b
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store i64 %res, i64* %retptr
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ret void
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}
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define void @Test_bypass_mul_short_const(i64 %a, i64 %l, i64* %retptr) {
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; CHECK-LABEL: @Test_bypass_mul_short_const(
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; CHECK-NEXT: [[C:%.*]] = mul i64 [[A:%.*]], -42
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; CHECK-NEXT: [[TMP1:%.*]] = or i64 [[C]], [[L:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], -4294967296
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], 0
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; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP9:%.*]]
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; CHECK: [[TMP5:%.*]] = trunc i64 [[L]] to i32
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[C]] to i32
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; CHECK-NEXT: [[TMP7:%.*]] = urem i32 [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
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; CHECK-NEXT: br label [[TMP11:%.*]]
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; CHECK: [[TMP10:%.*]] = urem i64 [[C]], [[L]]
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; CHECK-NEXT: br label [[TMP11]]
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; CHECK: [[TMP12:%.*]] = phi i64 [ [[TMP8]], [[TMP4]] ], [ [[TMP10]], [[TMP9]] ]
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; CHECK-NEXT: store i64 [[TMP12]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%c = mul i64 %a, -42
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%res = urem i64 %c, %l
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store i64 %res, i64* %retptr
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ret void
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}
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@ -1,106 +0,0 @@
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; RUN: opt -S -codegenprepare < %s | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; We only use the div instruction -- the rem should be DCE'ed.
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; CHECK-LABEL: @div_only
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define void @div_only(i64 %a, i64 %b, i64* %retptr) {
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; CHECK: udiv i32
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; CHECK-NOT: urem
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; CHECK: sdiv i64
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; CHECK-NOT: rem
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%d = sdiv i64 %a, %b
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store i64 %d, i64* %retptr
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ret void
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}
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; We only use the rem instruction -- the div should be DCE'ed.
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; CHECK-LABEL: @rem_only
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define void @rem_only(i64 %a, i64 %b, i64* %retptr) {
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; CHECK-NOT: div
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; CHECK: urem i32
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; CHECK-NOT: div
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; CHECK: rem i64
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; CHECK-NOT: div
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%d = srem i64 %a, %b
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store i64 %d, i64* %retptr
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ret void
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}
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; CHECK-LABEL: @udiv_by_constant(
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define i64 @udiv_by_constant(i32 %a) {
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; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A_ZEXT]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 50
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: ret i64 [[TMP3]]
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%a.zext = zext i32 %a to i64
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%wide.div = udiv i64 %a.zext, 50
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ret i64 %wide.div
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}
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; CHECK-LABEL: @urem_by_constant(
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define i64 @urem_by_constant(i32 %a) {
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; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A_ZEXT]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[TMP1]], 50
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: ret i64 [[TMP3]]
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%a.zext = zext i32 %a to i64
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%wide.div = urem i64 %a.zext, 50
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ret i64 %wide.div
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}
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; Negative test: instead of emitting a runtime check on %a, we prefer to let the
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; DAGCombiner transform this division by constant into a multiplication (with a
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; "magic constant").
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;
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; CHECK-LABEL: @udiv_by_constant_negative_0(
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define i64 @udiv_by_constant_negative_0(i64 %a) {
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; CHECK-NEXT: [[WIDE_DIV:%.*]] = udiv i64 [[A:%.*]], 50
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; CHECK-NEXT: ret i64 [[WIDE_DIV]]
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%wide.div = udiv i64 %a, 50
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ret i64 %wide.div
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}
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; Negative test: while we know the dividend is short, the divisor isn't. This
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; test is here for completeness, but instcombine will optimize this to return 0.
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;
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; CHECK-LABEL: @udiv_by_constant_negative_1(
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define i64 @udiv_by_constant_negative_1(i32 %a) {
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; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[WIDE_DIV:%.*]] = udiv i64 [[A_ZEXT]], 8589934592
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; CHECK-NEXT: ret i64 [[WIDE_DIV]]
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%a.zext = zext i32 %a to i64
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%wide.div = udiv i64 %a.zext, 8589934592 ;; == 1 << 33
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ret i64 %wide.div
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}
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; URem version of udiv_by_constant_negative_0
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;
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; CHECK-LABEL: @urem_by_constant_negative_0(
|
||||
define i64 @urem_by_constant_negative_0(i64 %a) {
|
||||
; CHECK-NEXT: [[WIDE_DIV:%.*]] = urem i64 [[A:%.*]], 50
|
||||
; CHECK-NEXT: ret i64 [[WIDE_DIV]]
|
||||
|
||||
%wide.div = urem i64 %a, 50
|
||||
ret i64 %wide.div
|
||||
}
|
||||
|
||||
; URem version of udiv_by_constant_negative_1
|
||||
;
|
||||
; CHECK-LABEL: @urem_by_constant_negative_1(
|
||||
define i64 @urem_by_constant_negative_1(i32 %a) {
|
||||
; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
|
||||
; CHECK-NEXT: [[WIDE_DIV:%.*]] = urem i64 [[A_ZEXT]], 8589934592
|
||||
; CHECK-NEXT: ret i64 [[WIDE_DIV]]
|
||||
|
||||
%a.zext = zext i32 %a to i64
|
||||
%wide.div = urem i64 %a.zext, 8589934592 ;; == 1 << 33
|
||||
ret i64 %wide.div
|
||||
}
|
||||
@ -1,21 +0,0 @@
|
||||
; RUN: opt -S -codegenprepare < %s | FileCheck %s
|
||||
|
||||
target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
|
||||
target triple = "nvptx64-nvidia-cuda"
|
||||
|
||||
; CHECK-LABEL: @test
|
||||
define i64 @test(i1 %pred, i64* %ptr) {
|
||||
; CHECK: addrspacecast
|
||||
%ptr_as1 = addrspacecast i64* %ptr to i64 addrspace(1)*
|
||||
br i1 %pred, label %l1, label %l2
|
||||
l1:
|
||||
; CHECK-LABEL: l1:
|
||||
; CHECK-NOT: addrspacecast
|
||||
%v1 = load i64, i64* %ptr
|
||||
ret i64 %v1
|
||||
l2:
|
||||
; CHECK-LABEL: l2:
|
||||
; CHECK-NOT: addrspacecast
|
||||
%v2 = load i64, i64 addrspace(1)* %ptr_as1
|
||||
ret i64 %v2
|
||||
}
|
||||
@ -1,2 +0,0 @@
|
||||
if not 'NVPTX' in config.root.targets:
|
||||
config.unsupported = True
|
||||
Reference in New Issue
Block a user