Imported Upstream version 5.18.0.167

Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a

external/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll

@@ -1,82 +0,0 @@
-; RUN: opt -S -codegenprepare -mtriple=aarch64-linux %s | FileCheck -enable-var-scope %s
-
-; Test for CodeGenPrepare::optimizeLoadExt(): simple case: two loads
-; feeding a phi that zext's each loaded value.
-define i32 @test_free_zext(i32* %ptr, i32* %ptr2, i32 %c) {
-; CHECK-LABEL: @test_free_zext(
-bb1:
-; CHECK: bb1:
-; CHECK: %[[T1:.*]] = load
-; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535
-  %load1 = load i32, i32* %ptr, align 4
-  %cmp = icmp ne i32 %c, 0
-  br i1 %cmp, label %bb2, label %bb3
-bb2:
-; CHECK: bb2:
-; CHECK: %[[T2:.*]] = load
-; CHECK: %[[A2:.*]] = and i32 %[[T2]], 65535
-  %load2 = load i32, i32* %ptr2, align 4
-  br label %bb3
-bb3:
-; CHECK: bb3:
-; CHECK: phi i32 [ %[[A1]], %bb1 ], [ %[[A2]], %bb2 ]
-  %phi = phi i32 [ %load1, %bb1 ], [ %load2, %bb2 ]
-  %and = and i32 %phi, 65535
-  ret i32 %and
-}
-
-; Test for CodeGenPrepare::optimizeLoadExt(): exercise all opcode
-; cases of active bit calculation.
-define i32 @test_free_zext2(i32* %ptr, i16* %dst16, i32* %dst32, i32 %c) {
-; CHECK-LABEL: @test_free_zext2(
-bb1:
-; CHECK: bb1:
-; CHECK: %[[T1:.*]] = load
-; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535
-  %load1 = load i32, i32* %ptr, align 4
-  %cmp = icmp ne i32 %c, 0
-  br i1 %cmp, label %bb2, label %bb4
-bb2:
-; CHECK: bb2:
-  %trunc = trunc i32 %load1 to i16
-  store i16 %trunc, i16* %dst16, align 2
-  br i1 %cmp, label %bb3, label %bb4
-bb3:
-; CHECK: bb3:
-  %shl = shl i32 %load1, 16
-  store i32 %shl, i32* %dst32, align 4
-  br label %bb4
-bb4:
-; CHECK: bb4:
-; CHECK-NOT: and
-; CHECK: ret i32 %[[A1]]
-  %and = and i32 %load1, 65535
-  ret i32 %and
-}
-
-; Test for CodeGenPrepare::optimizeLoadExt(): check case of zext-able
-; load feeding a phi in the same block.
-define void @test_free_zext3(i32* %ptr, i32* %ptr2, i32* %dst, i64* %c) {
-; CHECK-LABEL: @test_free_zext3(
-bb1:
-; CHECK: bb1:
-; CHECK: %[[T1:.*]] = load
-; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535
-  %load1 = load i32, i32* %ptr, align 4
-  br label %loop
-loop:
-; CHECK: loop:
-; CHECK: phi i32 [ %[[A1]], %bb1 ], [ %[[A2:.*]], %loop ]
-  %phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ]
-  %and = and i32 %phi, 65535
-  store i32 %and, i32* %dst, align 4
-  %idx = load volatile i64, i64* %c, align 4
-  %addr = getelementptr inbounds i32, i32* %ptr2, i64 %idx
-; CHECK: %[[T2:.*]] = load i32
-; CHECK: %[[A2]] = and i32 %[[T2]], 65535
-  %load2 = load i32, i32* %addr, align 4
-  %cmp = icmp ne i64 %idx, 0
-  br i1 %cmp, label %loop, label %end
-end:
-  ret void
-}

external/llvm/test/Transforms/CodeGenPrepare/AArch64/lit.local.cfg

@@ -1,3 +0,0 @@
-if not 'AArch64' in config.root.targets:
-    config.unsupported = True
-

external/llvm/test/Transforms/CodeGenPrepare/AArch64/trunc-weird-user.ll

@@ -1,36 +0,0 @@
-; RUN: opt -S -codegenprepare -mtriple=arm64-apple-ios7.0 %s | FileCheck %s
-
-%foo = type { i8 }
-
-define %foo @test_merge(i32 %in) {
-; CHECK-LABEL: @test_merge
-
-  ; CodeGenPrepare was requesting the EVT for { i8 } to determine
-  ; whether the insertvalue user of the trunc was legal. This
-  ; asserted.
-
-; CHECK: insertvalue %foo undef, i8 %byte, 0
-  %lobit = lshr i32 %in, 31
-  %byte = trunc i32 %lobit to i8
-  %struct = insertvalue %foo undef, i8 %byte, 0
-  ret %"foo" %struct
-}
-
-define i64* @test_merge_PR21548(i32 %a, i64* %p1, i64* %p2, i64* %p3) {
-; CHECK-LABEL: @test_merge_PR21548
-  %as = lshr i32 %a, 3
-  %Tr = trunc i32 %as to i1
-  br i1 %Tr, label %BB2, label %BB3
-
-BB2:
-  ; Similarly to above:
-  ; CodeGenPrepare was requesting the EVT for i8* to determine
-  ; whether the select user of the trunc was legal. This asserted.
-
-; CHECK: select i1 {{%.*}}, i64* %p1, i64* %p2
-  %p = select i1 %Tr, i64* %p1, i64* %p2
-  ret i64* %p
-
-BB3:
-  ret i64* %p3
-}

external/llvm/test/Transforms/CodeGenPrepare/AArch64/widen_switch.ll

@@ -1,95 +0,0 @@
-;; AArch64 is arbitralily chosen as a 32/64-bit RISC representative to show the transform in all tests.
-
-; RUN: opt < %s -codegenprepare -S -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefix=ARM64
-
-; AArch64 widens to 32-bit.
-
-define i32 @widen_switch_i16(i32 %a)  {
-entry:
-  %trunc = trunc i32 %a to i16
-  switch i16 %trunc, label %sw.default [
-    i16 1, label %sw.bb0
-    i16 -1, label %sw.bb1
-  ]
-
-sw.bb0:
-  br label %return
-
-sw.bb1:
-  br label %return
-
-sw.default:
-  br label %return
-
-return:
-  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
-  ret i32 %retval
-
-; ARM64-LABEL: @widen_switch_i16(
-; ARM64:       %0 = zext i16 %trunc to i32
-; ARM64-NEXT:  switch i32 %0, label %sw.default [
-; ARM64-NEXT:    i32 1, label %sw.bb0
-; ARM64-NEXT:    i32 65535, label %sw.bb1
-}
-
-; Widen to 32-bit from a smaller, non-native type.
-
-define i32 @widen_switch_i17(i32 %a)  {
-entry:
-  %trunc = trunc i32 %a to i17
-  switch i17 %trunc, label %sw.default [
-    i17 10, label %sw.bb0
-    i17 -1, label %sw.bb1
-  ]
-
-sw.bb0:
-  br label %return
-
-sw.bb1:
-  br label %return
-
-sw.default:
-  br label %return
-
-return:
-  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
-  ret i32 %retval
-
-; ARM64-LABEL: @widen_switch_i17(
-; ARM64:       %0 = zext i17 %trunc to i32
-; ARM64-NEXT:  switch i32 %0, label %sw.default [
-; ARM64-NEXT:    i32 10, label %sw.bb0
-; ARM64-NEXT:    i32 131071, label %sw.bb1
-}
-
-; If the switch condition is a sign-extended function argument, then the
-; condition and cases should be sign-extended rather than zero-extended
-; because the sign-extension can be optimized away.
-
-define i32 @widen_switch_i16_sext(i2 signext %a)  {
-entry:
-  switch i2 %a, label %sw.default [
-    i2 1, label %sw.bb0
-    i2 -1, label %sw.bb1
-  ]
-
-sw.bb0:
-  br label %return
-
-sw.bb1:
-  br label %return
-
-sw.default:
-  br label %return
-
-return:
-  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
-  ret i32 %retval
-
-; ARM64-LABEL: @widen_switch_i16_sext(
-; ARM64:       %0 = sext i2 %a to i32
-; ARM64-NEXT:  switch i32 %0, label %sw.default [
-; ARM64-NEXT:    i32 1, label %sw.bb0
-; ARM64-NEXT:    i32 -1, label %sw.bb1
-}
-