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Imported Upstream version 5.18.0.167
Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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@ -1,9 +0,0 @@
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# RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s
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# RUN: llvm-mc -triple=arm64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s
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# The "Rm" bits are ignored, but the canonical representation has them filled
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# with 0s. This is what we should produce even if the input bit-pattern had
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# something else there.
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# CHECK: fcmp s31, #0.0 // encoding: [0xe8,0x23,0x20,0x1e]
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0xe8 0x23 0x33 0x1e
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,31 +0,0 @@
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# These spawn another process so they're rather expensive. Not many.
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# LDR/STR: undefined if option field is 10x or 00x.
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# RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
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# Instructions notionally in the add/sub (extended register) sheet, but with
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# invalid shift amount or "opt" field.
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# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# MOVK with sf == 0 and hw<1> == 1 is unallocated.
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# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
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# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
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# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# EXT on vectors of i8 must have imm<3> = 0.
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# RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# SCVTF on fixed point W-registers is undefined if scale<5> == 0.
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# Same with FCVTZS and FCVTZU.
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# RUN: echo "0x00 0x00 0x02 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x00 0x18 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# CHECK: invalid instruction encoding
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@ -1,29 +0,0 @@
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# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
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#==---------------------------------------------------------------------------==
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# 5.4.4 Bitfield Operations
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#==---------------------------------------------------------------------------==
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0x41 0x3c 0x01 0x33
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0x41 0x3c 0x41 0xb3
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0x41 0x3c 0x01 0x13
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0x41 0x3c 0x41 0x93
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0x41 0x3c 0x01 0x53
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0x41 0x3c 0x41 0xd3
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# CHECK: bfxil w1, w2, #1, #15
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# CHECK: bfxil x1, x2, #1, #15
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# CHECK: sbfx w1, w2, #1, #15
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# CHECK: sbfx x1, x2, #1, #15
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# CHECK: ubfx w1, w2, #1, #15
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# CHECK: ubfx x1, x2, #1, #15
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#==---------------------------------------------------------------------------==
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# 5.4.5 Extract (immediate)
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#==---------------------------------------------------------------------------==
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0x41 0x3c 0x83 0x13
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0x62 0x04 0xc4 0x93
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# CHECK: extr w1, w2, w3, #15
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# CHECK: extr x2, x3, x4, #1
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@ -1,75 +0,0 @@
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# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
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#-----------------------------------------------------------------------------
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# Unconditional branch (register) instructions.
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#-----------------------------------------------------------------------------
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0xc0 0x03 0x5f 0xd6
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# CHECK: ret
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0x20 0x00 0x5f 0xd6
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# CHECK: ret x1
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0xe0 0x03 0xbf 0xd6
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# CHECK: drps
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0xe0 0x03 0x9f 0xd6
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# CHECK: eret
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0xa0 0x00 0x1f 0xd6
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# CHECK: br x5
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0x20 0x01 0x3f 0xd6
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# CHECK: blr x9
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0x0B 0x00 0x18 0x37
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# CHECK: tbnz w11, #3, #0
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#-----------------------------------------------------------------------------
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# Exception generation instructions.
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#-----------------------------------------------------------------------------
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0x20 0x00 0x20 0xd4
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# CHECK: brk #0x1
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0x41 0x00 0xa0 0xd4
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# CHECK: dcps1 #0x2
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0x62 0x00 0xa0 0xd4
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# CHECK: dcps2 #0x3
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0x83 0x00 0xa0 0xd4
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# CHECK: dcps3 #0x4
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0xa0 0x00 0x40 0xd4
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# CHECK: hlt #0x5
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0xc2 0x00 0x00 0xd4
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# CHECK: hvc #0x6
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0xe3 0x00 0x00 0xd4
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# CHECK: smc #0x7
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0x01 0x01 0x00 0xd4
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# CHECK: svc #0x8
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#-----------------------------------------------------------------------------
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# PC-relative branches (both positive and negative displacement)
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#-----------------------------------------------------------------------------
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0x07 0x00 0x00 0x14
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# CHECK: b #28
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0x06 0x00 0x00 0x94
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# CHECK: bl #24
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0xa1 0x00 0x00 0x54
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# CHECK: b.ne #20
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0x80 0x00 0x08 0x36
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# CHECK: tbz w0, #1, #16
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0xe1 0xff 0xf7 0x36
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# CHECK: tbz w1, #30, #-4
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0x60 0x00 0x08 0x37
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# CHECK: tbnz w0, #1, #12
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0x40 0x00 0x00 0xb4
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# CHECK: cbz x0, #8
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0x20 0x00 0x00 0xb5
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# CHECK: cbnz x0, #4
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0x1f 0x20 0x03 0xd5
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# CHECK: nop
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0xff 0xff 0xff 0x17
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# CHECK: b #-4
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0xc1 0xff 0xff 0x54
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# CHECK: b.ne #-8
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0xa0 0xff 0x0f 0x36
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# CHECK: tbz w0, #1, #-12
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0x80 0xff 0xff 0xb4
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# CHECK: cbz x0, #-16
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0x1f 0x20 0x03 0xd5
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# CHECK: nop
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@ -1,21 +0,0 @@
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# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble < %s | FileCheck %s
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0x00 0x08 0x00 0xc8
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# CHECK: stxr w0, x0, [x0]
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0x00 0x00 0x40 0x9b
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# CHECK: smulh x0, x0, x0
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0x08 0x20 0x21 0x1e
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# CHECK: fcmp s0, #0.0
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0x1f 0x00 0x00 0x11
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# CHECK: mov wsp, w0
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0x00 0x7c 0x00 0x13
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# CHECK: asr w0, w0, #0
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@ -1,18 +0,0 @@
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# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s
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# CHECK: crc32b w5, w7, w20
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# CHECK: crc32h w28, wzr, w30
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# CHECK: crc32w w0, w1, w2
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# CHECK: crc32x w7, w9, x20
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# CHECK: crc32cb w9, w5, w4
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# CHECK: crc32ch w13, w17, w25
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# CHECK: crc32cw wzr, w3, w5
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# CHECK: crc32cx w18, w16, xzr
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0xe5 0x40 0xd4 0x1a
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0xfc 0x47 0xde 0x1a
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0x20 0x48 0xc2 0x1a
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0x27 0x4d 0xd4 0x9a
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0xa9 0x50 0xc4 0x1a
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0x2d 0x56 0xd9 0x1a
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0x7f 0x58 0xc5 0x1a
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0x12 0x5e 0xdf 0x9a
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@ -1,47 +0,0 @@
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# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto --disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s --check-prefix=CHECK-APPLE
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0x20 0x48 0x28 0x4e
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0x20 0x58 0x28 0x4e
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0x20 0x68 0x28 0x4e
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0x20 0x78 0x28 0x4e
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0x20 0x00 0x02 0x5e
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0x20 0x10 0x02 0x5e
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0x20 0x20 0x02 0x5e
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0x20 0x30 0x02 0x5e
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0x20 0x40 0x02 0x5e
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0x20 0x50 0x02 0x5e
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0x20 0x60 0x02 0x5e
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0x20 0x08 0x28 0x5e
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0x20 0x18 0x28 0x5e
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0x20 0x28 0x28 0x5e
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# CHECK: aese v0.16b, v1.16b
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# CHECK: aesd v0.16b, v1.16b
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# CHECK: aesmc v0.16b, v1.16b
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# CHECK: aesimc v0.16b, v1.16b
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# CHECK: sha1c q0, s1, v2.4s
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# CHECK: sha1p q0, s1, v2.4s
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# CHECK: sha1m q0, s1, v2.4s
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# CHECK: sha1su0 v0.4s, v1.4s, v2
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# CHECK: sha256h q0, q1, v2.4s
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# CHECK: sha256h2 q0, q1, v2.4s
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# CHECK: sha256su1 v0.4s, v1.4s, v2.4s
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# CHECK: sha1h s0, s1
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# CHECK: sha1su1 v0.4s, v1.4s
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# CHECK: sha256su0 v0.4s, v1.4s
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# CHECK-APPLE: aese.16b v0, v1
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# CHECK-APPLE: aesd.16b v0, v1
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# CHECK-APPLE: aesmc.16b v0, v1
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# CHECK-APPLE: aesimc.16b v0, v1
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# CHECK-APPLE: sha1c.4s q0, s1, v2
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# CHECK-APPLE: sha1p.4s q0, s1, v2
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# CHECK-APPLE: sha1m.4s q0, s1, v2
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# CHECK-APPLE: sha1su0.4s v0, v1, v2
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# CHECK-APPLE: sha256h.4s q0, q1, v2
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# CHECK-APPLE: sha256h2.4s q0, q1, v2
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# CHECK-APPLE: sha256su1.4s v0, v1, v2
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# CHECK-APPLE: sha1h s0, s1
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# CHECK-APPLE: sha1su1.4s v0, v1
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# CHECK-APPLE: sha256su0.4s v0, v1
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@ -1,6 +0,0 @@
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# RUN: llvm-mc -triple arm64-apple-darwin -disassemble < %s 2>&1 | FileCheck %s
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# rdar://15226511
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0x7b 0xbf 0x25 0x72
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: 0x7b 0xbf 0x25 0x72
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@ -1,223 +0,0 @@
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# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
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#==---------------------------------------------------------------------------==
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# 5.4.2 Logical (immediate)
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#==---------------------------------------------------------------------------==
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0x00 0x00 0x00 0x12
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0x00 0x00 0x40 0x92
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0x41 0x0c 0x00 0x12
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0x41 0x0c 0x40 0x92
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0xbf 0xec 0x7c 0x92
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0x00 0x00 0x00 0x72
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0x00 0x00 0x40 0xf2
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0x41 0x0c 0x00 0x72
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0x41 0x0c 0x40 0xf2
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0x5f 0x0c 0x40 0xf2
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# CHECK: and w0, w0, #0x1
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# CHECK: and x0, x0, #0x1
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# CHECK: and w1, w2, #0xf
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# CHECK: and x1, x2, #0xf
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# CHECK: and sp, x5, #0xfffffffffffffff0
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# CHECK: ands w0, w0, #0x1
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# CHECK: ands x0, x0, #0x1
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# CHECK: ands w1, w2, #0xf
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# CHECK: ands x1, x2, #0xf
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# CHECK: tst x2, #0xf
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0x41 0x00 0x12 0x52
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0x41 0x00 0x71 0xd2
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0x5f 0x00 0x71 0xd2
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# CHECK: eor w1, w2, #0x4000
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# CHECK: eor x1, x2, #0x8000
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# CHECK: eor sp, x2, #0x8000
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0x41 0x00 0x12 0x32
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0x41 0x00 0x71 0xb2
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0x5f 0x00 0x71 0xb2
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# CHECK: orr w1, w2, #0x4000
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# CHECK: orr x1, x2, #0x8000
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# CHECK: orr sp, x2, #0x8000
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#==---------------------------------------------------------------------------==
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# 5.5.3 Logical (shifted register)
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#==---------------------------------------------------------------------------==
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0x41 0x00 0x03 0x0a
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0x41 0x00 0x03 0x8a
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0x41 0x08 0x03 0x0a
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0x41 0x08 0x03 0x8a
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0x41 0x08 0x43 0x0a
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0x41 0x08 0x43 0x8a
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0x41 0x08 0x83 0x0a
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0x41 0x08 0x83 0x8a
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0x41 0x08 0xc3 0x0a
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0x41 0x08 0xc3 0x8a
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# CHECK: and w1, w2, w3
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# CHECK: and x1, x2, x3
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# CHECK: and w1, w2, w3, lsl #2
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# CHECK: and x1, x2, x3, lsl #2
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# CHECK: and w1, w2, w3, lsr #2
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# CHECK: and x1, x2, x3, lsr #2
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# CHECK: and w1, w2, w3, asr #2
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# CHECK: and x1, x2, x3, asr #2
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# CHECK: and w1, w2, w3, ror #2
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# CHECK: and x1, x2, x3, ror #2
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0x41 0x00 0x03 0x6a
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0x41 0x00 0x03 0xea
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0x41 0x08 0x03 0x6a
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0x41 0x08 0x03 0xea
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0x41 0x08 0x43 0x6a
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0x41 0x08 0x43 0xea
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0x41 0x08 0x83 0x6a
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0x41 0x08 0x83 0xea
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0x41 0x08 0xc3 0x6a
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0x41 0x08 0xc3 0xea
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# CHECK: ands w1, w2, w3
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# CHECK: ands x1, x2, x3
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# CHECK: ands w1, w2, w3, lsl #2
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# CHECK: ands x1, x2, x3, lsl #2
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# CHECK: ands w1, w2, w3, lsr #2
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# CHECK: ands x1, x2, x3, lsr #2
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# CHECK: ands w1, w2, w3, asr #2
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# CHECK: ands x1, x2, x3, asr #2
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# CHECK: ands w1, w2, w3, ror #2
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# CHECK: ands x1, x2, x3, ror #2
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0x41 0x00 0x23 0x0a
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0x41 0x00 0x23 0x8a
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0x41 0x0c 0x23 0x0a
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0x41 0x0c 0x23 0x8a
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0x41 0x0c 0x63 0x0a
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0x41 0x0c 0x63 0x8a
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0x41 0x0c 0xa3 0x0a
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0x41 0x0c 0xa3 0x8a
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0x41 0x0c 0xe3 0x0a
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0x41 0x0c 0xe3 0x8a
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# CHECK: bic w1, w2, w3
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# CHECK: bic x1, x2, x3
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# CHECK: bic w1, w2, w3, lsl #3
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# CHECK: bic x1, x2, x3, lsl #3
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# CHECK: bic w1, w2, w3, lsr #3
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# CHECK: bic x1, x2, x3, lsr #3
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# CHECK: bic w1, w2, w3, asr #3
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# CHECK: bic x1, x2, x3, asr #3
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# CHECK: bic w1, w2, w3, ror #3
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# CHECK: bic x1, x2, x3, ror #3
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0x41 0x00 0x23 0x6a
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0x41 0x00 0x23 0xea
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0x41 0x0c 0x23 0x6a
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0x41 0x0c 0x23 0xea
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0x41 0x0c 0x63 0x6a
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0x41 0x0c 0x63 0xea
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0x41 0x0c 0xa3 0x6a
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0x41 0x0c 0xa3 0xea
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0x41 0x0c 0xe3 0x6a
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0x41 0x0c 0xe3 0xea
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# CHECK: bics w1, w2, w3
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# CHECK: bics x1, x2, x3
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# CHECK: bics w1, w2, w3, lsl #3
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# CHECK: bics x1, x2, x3, lsl #3
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# CHECK: bics w1, w2, w3, lsr #3
|
||||
# CHECK: bics x1, x2, x3, lsr #3
|
||||
# CHECK: bics w1, w2, w3, asr #3
|
||||
# CHECK: bics x1, x2, x3, asr #3
|
||||
# CHECK: bics w1, w2, w3, ror #3
|
||||
# CHECK: bics x1, x2, x3, ror #3
|
||||
|
||||
0x41 0x00 0x23 0x4a
|
||||
0x41 0x00 0x23 0xca
|
||||
0x41 0x10 0x23 0x4a
|
||||
0x41 0x10 0x23 0xca
|
||||
0x41 0x10 0x63 0x4a
|
||||
0x41 0x10 0x63 0xca
|
||||
0x41 0x10 0xa3 0x4a
|
||||
0x41 0x10 0xa3 0xca
|
||||
0x41 0x10 0xe3 0x4a
|
||||
0x41 0x10 0xe3 0xca
|
||||
|
||||
# CHECK: eon w1, w2, w3
|
||||
# CHECK: eon x1, x2, x3
|
||||
# CHECK: eon w1, w2, w3, lsl #4
|
||||
# CHECK: eon x1, x2, x3, lsl #4
|
||||
# CHECK: eon w1, w2, w3, lsr #4
|
||||
# CHECK: eon x1, x2, x3, lsr #4
|
||||
# CHECK: eon w1, w2, w3, asr #4
|
||||
# CHECK: eon x1, x2, x3, asr #4
|
||||
# CHECK: eon w1, w2, w3, ror #4
|
||||
# CHECK: eon x1, x2, x3, ror #4
|
||||
|
||||
0x41 0x00 0x03 0x4a
|
||||
0x41 0x00 0x03 0xca
|
||||
0x41 0x14 0x03 0x4a
|
||||
0x41 0x14 0x03 0xca
|
||||
0x41 0x14 0x43 0x4a
|
||||
0x41 0x14 0x43 0xca
|
||||
0x41 0x14 0x83 0x4a
|
||||
0x41 0x14 0x83 0xca
|
||||
0x41 0x14 0xc3 0x4a
|
||||
0x41 0x14 0xc3 0xca
|
||||
|
||||
# CHECK: eor w1, w2, w3
|
||||
# CHECK: eor x1, x2, x3
|
||||
# CHECK: eor w1, w2, w3, lsl #5
|
||||
# CHECK: eor x1, x2, x3, lsl #5
|
||||
# CHECK: eor w1, w2, w3, lsr #5
|
||||
# CHECK: eor x1, x2, x3, lsr #5
|
||||
# CHECK: eor w1, w2, w3, asr #5
|
||||
# CHECK: eor x1, x2, x3, asr #5
|
||||
# CHECK: eor w1, w2, w3, ror #5
|
||||
# CHECK: eor x1, x2, x3, ror #5
|
||||
|
||||
0x41 0x00 0x03 0x2a
|
||||
0x41 0x00 0x03 0xaa
|
||||
0x41 0x18 0x03 0x2a
|
||||
0x41 0x18 0x03 0xaa
|
||||
0x41 0x18 0x43 0x2a
|
||||
0x41 0x18 0x43 0xaa
|
||||
0x41 0x18 0x83 0x2a
|
||||
0x41 0x18 0x83 0xaa
|
||||
0x41 0x18 0xc3 0x2a
|
||||
0x41 0x18 0xc3 0xaa
|
||||
|
||||
# CHECK: orr w1, w2, w3
|
||||
# CHECK: orr x1, x2, x3
|
||||
# CHECK: orr w1, w2, w3, lsl #6
|
||||
# CHECK: orr x1, x2, x3, lsl #6
|
||||
# CHECK: orr w1, w2, w3, lsr #6
|
||||
# CHECK: orr x1, x2, x3, lsr #6
|
||||
# CHECK: orr w1, w2, w3, asr #6
|
||||
# CHECK: orr x1, x2, x3, asr #6
|
||||
# CHECK: orr w1, w2, w3, ror #6
|
||||
# CHECK: orr x1, x2, x3, ror #6
|
||||
|
||||
0x41 0x00 0x23 0x2a
|
||||
0x41 0x00 0x23 0xaa
|
||||
0x41 0x1c 0x23 0x2a
|
||||
0x41 0x1c 0x23 0xaa
|
||||
0x41 0x1c 0x63 0x2a
|
||||
0x41 0x1c 0x63 0xaa
|
||||
0x41 0x1c 0xa3 0x2a
|
||||
0x41 0x1c 0xa3 0xaa
|
||||
0x41 0x1c 0xe3 0x2a
|
||||
0x41 0x1c 0xe3 0xaa
|
||||
|
||||
# CHECK: orn w1, w2, w3
|
||||
# CHECK: orn x1, x2, x3
|
||||
# CHECK: orn w1, w2, w3, lsl #7
|
||||
# CHECK: orn x1, x2, x3, lsl #7
|
||||
# CHECK: orn w1, w2, w3, lsr #7
|
||||
# CHECK: orn x1, x2, x3, lsr #7
|
||||
# CHECK: orn w1, w2, w3, asr #7
|
||||
# CHECK: orn x1, x2, x3, asr #7
|
||||
# CHECK: orn w1, w2, w3, ror #7
|
||||
# CHECK: orn x1, x2, x3, ror #7
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,7 +0,0 @@
|
||||
# RUN: llvm-mc -triple arm64 -mattr=neon -disassemble < %s | FileCheck %s
|
||||
|
||||
0x00 0x00 0xae 0x9e
|
||||
0x00 0x00 0xaf 0x9e
|
||||
|
||||
# CHECK: fmov x0, v0.d[1]
|
||||
# CHECK: fmov v0.d[1], x0
|
||||
@ -1,324 +0,0 @@
|
||||
# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble -output-asm-variant=1 < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon,v8.2a,fullfp16 --disassemble -output-asm-variant=1 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Floating-point arithmetic
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
0x41 0xc0 0xe0 0x1e
|
||||
0x41 0xc0 0x20 0x1e
|
||||
0x41 0xc0 0x60 0x1e
|
||||
|
||||
# FP16: fabs h1, h2
|
||||
# CHECK: fabs s1, s2
|
||||
# CHECK: fabs d1, d2
|
||||
|
||||
0x41 0x28 0xe3 0x1e
|
||||
0x41 0x28 0x23 0x1e
|
||||
0x41 0x28 0x63 0x1e
|
||||
|
||||
# FP16: fadd h1, h2, h3
|
||||
# CHECK: fadd s1, s2, s3
|
||||
# CHECK: fadd d1, d2, d3
|
||||
|
||||
0x41 0x18 0xe3 0x1e
|
||||
0x41 0x18 0x23 0x1e
|
||||
0x41 0x18 0x63 0x1e
|
||||
|
||||
# FP16: fdiv h1, h2, h3
|
||||
# CHECK: fdiv s1, s2, s3
|
||||
# CHECK: fdiv d1, d2, d3
|
||||
|
||||
0x41 0x10 0xc3 0x1f
|
||||
0x41 0x10 0x03 0x1f
|
||||
0x41 0x10 0x43 0x1f
|
||||
|
||||
# FP16: fmadd h1, h2, h3, h4
|
||||
# CHECK: fmadd s1, s2, s3, s4
|
||||
# CHECK: fmadd d1, d2, d3, d4
|
||||
|
||||
0x41 0x48 0xe3 0x1e
|
||||
0x41 0x48 0x23 0x1e
|
||||
0x41 0x48 0x63 0x1e
|
||||
0x41 0x68 0xe3 0x1e
|
||||
0x41 0x68 0x23 0x1e
|
||||
0x41 0x68 0x63 0x1e
|
||||
|
||||
# FP16: fmax h1, h2, h3
|
||||
# CHECK: fmax s1, s2, s3
|
||||
# CHECK: fmax d1, d2, d3
|
||||
# FP16: fmaxnm h1, h2, h3
|
||||
# CHECK: fmaxnm s1, s2, s3
|
||||
# CHECK: fmaxnm d1, d2, d3
|
||||
|
||||
0x41 0x58 0xe3 0x1e
|
||||
0x41 0x58 0x23 0x1e
|
||||
0x41 0x58 0x63 0x1e
|
||||
0x41 0x78 0xe3 0x1e
|
||||
0x41 0x78 0x23 0x1e
|
||||
0x41 0x78 0x63 0x1e
|
||||
|
||||
# FP16: fmin h1, h2, h3
|
||||
# CHECK: fmin s1, s2, s3
|
||||
# CHECK: fmin d1, d2, d3
|
||||
# FP16: fminnm h1, h2, h3
|
||||
# CHECK: fminnm s1, s2, s3
|
||||
# CHECK: fminnm d1, d2, d3
|
||||
|
||||
0x41 0x90 0xc3 0x1f
|
||||
0x41 0x90 0x03 0x1f
|
||||
0x41 0x90 0x43 0x1f
|
||||
|
||||
# FP16: fmsub h1, h2, h3, h4
|
||||
# CHECK: fmsub s1, s2, s3, s4
|
||||
# CHECK: fmsub d1, d2, d3, d4
|
||||
|
||||
0x41 0x08 0xe3 0x1e
|
||||
0x41 0x08 0x23 0x1e
|
||||
0x41 0x08 0x63 0x1e
|
||||
|
||||
# FP16: fmul h1, h2, h3
|
||||
# CHECK: fmul s1, s2, s3
|
||||
# CHECK: fmul d1, d2, d3
|
||||
|
||||
0x41 0x40 0xe1 0x1e
|
||||
0x41 0x40 0x21 0x1e
|
||||
0x41 0x40 0x61 0x1e
|
||||
|
||||
# FP16: fneg h1, h2
|
||||
# CHECK: fneg s1, s2
|
||||
# CHECK: fneg d1, d2
|
||||
|
||||
0x41 0x10 0xe3 0x1f
|
||||
0x41 0x10 0x23 0x1f
|
||||
0x41 0x10 0x63 0x1f
|
||||
|
||||
# FP16: fnmadd h1, h2, h3, h4
|
||||
# CHECK: fnmadd s1, s2, s3, s4
|
||||
# CHECK: fnmadd d1, d2, d3, d4
|
||||
|
||||
0x41 0x90 0xe3 0x1f
|
||||
0x41 0x90 0x23 0x1f
|
||||
0x41 0x90 0x63 0x1f
|
||||
|
||||
# FP16: fnmsub h1, h2, h3, h4
|
||||
# CHECK: fnmsub s1, s2, s3, s4
|
||||
# CHECK: fnmsub d1, d2, d3, d4
|
||||
|
||||
0x41 0x88 0xe3 0x1e
|
||||
0x41 0x88 0x23 0x1e
|
||||
0x41 0x88 0x63 0x1e
|
||||
|
||||
# FP16: fnmul h1, h2, h3
|
||||
# CHECK: fnmul s1, s2, s3
|
||||
# CHECK: fnmul d1, d2, d3
|
||||
|
||||
0x41 0xc0 0xe1 0x1e
|
||||
0x41 0xc0 0x21 0x1e
|
||||
0x41 0xc0 0x61 0x1e
|
||||
|
||||
# FP16: fsqrt h1, h2
|
||||
# CHECK: fsqrt s1, s2
|
||||
# CHECK: fsqrt d1, d2
|
||||
|
||||
0x41 0x38 0xe3 0x1e
|
||||
0x41 0x38 0x23 0x1e
|
||||
0x41 0x38 0x63 0x1e
|
||||
|
||||
# FP16: fsub h1, h2, h3
|
||||
# CHECK: fsub s1, s2, s3
|
||||
# CHECK: fsub d1, d2, d3
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Floating-point comparison
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
0x20 0x04 0xe2 0x1e
|
||||
0x20 0x04 0x22 0x1e
|
||||
0x20 0x04 0x62 0x1e
|
||||
0x30 0x04 0xe2 0x1e
|
||||
0x30 0x04 0x22 0x1e
|
||||
0x30 0x04 0x62 0x1e
|
||||
|
||||
# FP16: fccmp h1, h2, #0, eq
|
||||
# CHECK: fccmp s1, s2, #0, eq
|
||||
# CHECK: fccmp d1, d2, #0, eq
|
||||
# FP16: fccmpe h1, h2, #0, eq
|
||||
# CHECK: fccmpe s1, s2, #0, eq
|
||||
# CHECK: fccmpe d1, d2, #0, eq
|
||||
|
||||
0x20 0x20 0xe2 0x1e
|
||||
0x20 0x20 0x22 0x1e
|
||||
0x20 0x20 0x62 0x1e
|
||||
0x28 0x20 0xe0 0x1e
|
||||
0x28 0x20 0x20 0x1e
|
||||
0x28 0x20 0x60 0x1e
|
||||
0x30 0x20 0xe2 0x1e
|
||||
0x30 0x20 0x22 0x1e
|
||||
0x30 0x20 0x62 0x1e
|
||||
0x38 0x20 0xe0 0x1e
|
||||
0x38 0x20 0x20 0x1e
|
||||
0x38 0x20 0x60 0x1e
|
||||
|
||||
# FP16: fcmp h1, h2
|
||||
# CHECK: fcmp s1, s2
|
||||
# CHECK: fcmp d1, d2
|
||||
# FP16: fcmp h1, #0.0
|
||||
# CHECK: fcmp s1, #0.0
|
||||
# CHECK: fcmp d1, #0.0
|
||||
# FP16: fcmpe h1, h2
|
||||
# CHECK: fcmpe s1, s2
|
||||
# CHECK: fcmpe d1, d2
|
||||
# FP16: fcmpe h1, #0.0
|
||||
# CHECK: fcmpe s1, #0.0
|
||||
# CHECK: fcmpe d1, #0.0
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Floating-point conditional select
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
0x41 0x0c 0xe3 0x1e
|
||||
0x41 0x0c 0x23 0x1e
|
||||
0x41 0x0c 0x63 0x1e
|
||||
|
||||
# FP16: fcsel h1, h2, h3, eq
|
||||
# CHECK: fcsel s1, s2, s3, eq
|
||||
# CHECK: fcsel d1, d2, d3, eq
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Floating-point convert
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
0x41 0xc0 0x63 0x1e
|
||||
0x41 0x40 0x62 0x1e
|
||||
0x41 0xc0 0xe2 0x1e
|
||||
0x41 0x40 0xe2 0x1e
|
||||
0x41 0xc0 0x22 0x1e
|
||||
0x41 0xc0 0x23 0x1e
|
||||
|
||||
# CHECK: fcvt h1, d2
|
||||
# CHECK: fcvt s1, d2
|
||||
# CHECK: fcvt d1, h2
|
||||
# CHECK: fcvt s1, h2
|
||||
# CHECK: fcvt d1, s2
|
||||
# CHECK: fcvt h1, s2
|
||||
|
||||
0x41 0x00 0x44 0x1e
|
||||
0x41 0x04 0x44 0x1e
|
||||
0x41 0x00 0x44 0x9e
|
||||
0x41 0x04 0x44 0x9e
|
||||
0x41 0x00 0x04 0x1e
|
||||
0x41 0x04 0x04 0x1e
|
||||
0x41 0x00 0x04 0x9e
|
||||
0x41 0x04 0x04 0x9e
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Floating-point move
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
0x41 0x00 0xe7 0x1e
|
||||
0x41 0x00 0xe6 0x1e
|
||||
0x41 0x00 0x27 0x1e
|
||||
0x41 0x00 0x26 0x1e
|
||||
0x41 0x00 0x67 0x9e
|
||||
0x41 0x00 0x66 0x9e
|
||||
|
||||
# FP16: fmov h1, w2
|
||||
# FP16: fmov w1, h2
|
||||
# CHECK: fmov s1, w2
|
||||
# CHECK: fmov w1, s2
|
||||
# CHECK: fmov d1, x2
|
||||
# CHECK: fmov x1, d2
|
||||
|
||||
0x01 0x10 0xe8 0x1e
|
||||
0x01 0x10 0x28 0x1e
|
||||
0x01 0x10 0x68 0x1e
|
||||
0x01 0xf0 0x7b 0x1e
|
||||
0x01 0xf0 0x6b 0x1e
|
||||
|
||||
# FP16: fmov h1, #0.12500000
|
||||
# CHECK: fmov s1, #0.12500000
|
||||
# CHECK: fmov d1, #0.12500000
|
||||
# CHECK: fmov d1, #-0.48437500
|
||||
# CHECK: fmov d1, #0.48437500
|
||||
|
||||
0x41 0x40 0xe0 0x1e
|
||||
0x41 0x40 0x20 0x1e
|
||||
0x41 0x40 0x60 0x1e
|
||||
|
||||
# FP16: fmov h1, h2
|
||||
# CHECK: fmov s1, s2
|
||||
# CHECK: fmov d1, d2
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Floating-point round to integral
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
0x41 0x40 0xe6 0x1e
|
||||
0x41 0x40 0x26 0x1e
|
||||
0x41 0x40 0x66 0x1e
|
||||
|
||||
# FP16: frinta h1, h2
|
||||
# CHECK: frinta s1, s2
|
||||
# CHECK: frinta d1, d2
|
||||
|
||||
0x41 0xc0 0xe7 0x1e
|
||||
0x41 0xc0 0x27 0x1e
|
||||
0x41 0xc0 0x67 0x1e
|
||||
|
||||
# FP16: frinti h1, h2
|
||||
# CHECK: frinti s1, s2
|
||||
# CHECK: frinti d1, d2
|
||||
|
||||
0x41 0x40 0xe5 0x1e
|
||||
0x41 0x40 0x25 0x1e
|
||||
0x41 0x40 0x65 0x1e
|
||||
|
||||
# FP16: frintm h1, h2
|
||||
# CHECK: frintm s1, s2
|
||||
# CHECK: frintm d1, d2
|
||||
|
||||
0x41 0x40 0xe4 0x1e
|
||||
0x41 0x40 0x24 0x1e
|
||||
0x41 0x40 0x64 0x1e
|
||||
|
||||
# FP16: frintn h1, h2
|
||||
# CHECK: frintn s1, s2
|
||||
# CHECK: frintn d1, d2
|
||||
|
||||
0x41 0xc0 0xe4 0x1e
|
||||
0x41 0xc0 0x24 0x1e
|
||||
0x41 0xc0 0x64 0x1e
|
||||
|
||||
# FP16: frintp h1, h2
|
||||
# CHECK: frintp s1, s2
|
||||
# CHECK: frintp d1, d2
|
||||
|
||||
0x41 0x40 0xe7 0x1e
|
||||
0x41 0x40 0x27 0x1e
|
||||
0x41 0x40 0x67 0x1e
|
||||
|
||||
# FP16: frintx h1, h2
|
||||
# CHECK: frintx s1, s2
|
||||
# CHECK: frintx d1, d2
|
||||
|
||||
0x41 0xc0 0xe5 0x1e
|
||||
0x41 0xc0 0x25 0x1e
|
||||
0x41 0xc0 0x65 0x1e
|
||||
|
||||
# FP16: frintz h1, h2
|
||||
# CHECK: frintz s1, s2
|
||||
# CHECK: frintz d1, d2
|
||||
|
||||
0x00 0x3c 0xe0 0x7e
|
||||
0x00 0x8c 0xe0 0x5e
|
||||
|
||||
# CHECK: cmhs d0, d0, d0
|
||||
# CHECK: cmtst d0, d0, d0
|
||||
|
||||
0x00 0x00 0xaf 0x9e
|
||||
0x00 0x00 0xae 0x9e
|
||||
|
||||
# CHECK: fmov.d v0[1], x0
|
||||
# CHECK: fmov.d x0, v0[1]
|
||||
|
||||
@ -1,62 +0,0 @@
|
||||
# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
|
||||
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Hint encodings
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
0x1f 0x20 0x03 0xd5
|
||||
# CHECK: nop
|
||||
0x9f 0x20 0x03 0xd5
|
||||
# CHECK: sev
|
||||
0xbf 0x20 0x03 0xd5
|
||||
# CHECK: sevl
|
||||
0x5f 0x20 0x03 0xd5
|
||||
# CHECK: wfe
|
||||
0x7f 0x20 0x03 0xd5
|
||||
# CHECK: wfi
|
||||
0x3f 0x20 0x03 0xd5
|
||||
# CHECK: yield
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Single-immediate operand instructions
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
0x5f 0x3a 0x03 0xd5
|
||||
# CHECK: clrex #10
|
||||
0xdf 0x3f 0x03 0xd5
|
||||
# CHECK: isb{{$}}
|
||||
0xdf 0x31 0x03 0xd5
|
||||
# CHECK: isb #1
|
||||
0xbf 0x33 0x03 0xd5
|
||||
# CHECK: dmb osh
|
||||
0x9f 0x37 0x03 0xd5
|
||||
# CHECK: dsb nsh
|
||||
0x3f 0x76 0x08 0xd5
|
||||
# CHECK: dc ivac
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Generic system instructions
|
||||
#-----------------------------------------------------------------------------
|
||||
0xff 0x05 0x0a 0xd5
|
||||
0xe7 0x6a 0x0f 0xd5
|
||||
0xf4 0x3f 0x2e 0xd5
|
||||
0xbf 0x40 0x00 0xd5
|
||||
0x00 0xb0 0x18 0xd5
|
||||
0x00 0xb0 0x38 0xd5
|
||||
|
||||
# CHECK: sys #2, c0, c5, #7
|
||||
# CHECK: sys #7, c6, c10, #7, x7
|
||||
# CHECK: sysl x20, #6, c3, c15, #7
|
||||
# CHECK: msr SPSel, #0
|
||||
# CHECK: msr S3_0_C11_C0_0, x0
|
||||
# CHECK: mrs x0, S3_0_C11_C0_0
|
||||
|
||||
0x40 0xc0 0x1e 0xd5
|
||||
0x40 0xc0 0x1c 0xd5
|
||||
0x40 0xc0 0x18 0xd5
|
||||
|
||||
# CHECK: msr RMR_EL3, x0
|
||||
# CHECK: msr RMR_EL2, x0
|
||||
# CHECK: msr RMR_EL1, x0
|
||||
|
||||
@ -1,87 +0,0 @@
|
||||
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
|
||||
|
||||
0x41,0x7c,0xa0,0x08
|
||||
0x41,0x7c,0xe0,0x08
|
||||
0x41,0xfc,0xa0,0x08
|
||||
0x41,0xfc,0xe0,0x08
|
||||
0x41,0x7c,0xa0,0x48
|
||||
0x41,0x7c,0xe0,0x48
|
||||
0x41,0xfc,0xa0,0x48
|
||||
0x41,0xfc,0xe0,0x48
|
||||
# CHECK: casb w0, w1, [x2]
|
||||
# CHECK: casab w0, w1, [x2]
|
||||
# CHECK: caslb w0, w1, [x2]
|
||||
# CHECK: casalb w0, w1, [x2]
|
||||
# CHECK: cash w0, w1, [x2]
|
||||
# CHECK: casah w0, w1, [x2]
|
||||
# CHECK: caslh w0, w1, [x2]
|
||||
# CHECK: casalh w0, w1, [x2]
|
||||
|
||||
0x41,0x7c,0xa0,0x88
|
||||
0x41,0x7c,0xe0,0x88
|
||||
0x41,0xfc,0xa0,0x88
|
||||
0x41,0xfc,0xe0,0x88
|
||||
0x41,0x7c,0xa0,0xc8
|
||||
0x41,0x7c,0xe0,0xc8
|
||||
0x41,0xfc,0xa0,0xc8
|
||||
0x41,0xfc,0xe0,0xc8
|
||||
# CHECK: cas w0, w1, [x2]
|
||||
# CHECK: casa w0, w1, [x2]
|
||||
# CHECK: casl w0, w1, [x2]
|
||||
# CHECK: casal w0, w1, [x2]
|
||||
# CHECK: cas x0, x1, [x2]
|
||||
# CHECK: casa x0, x1, [x2]
|
||||
# CHECK: casl x0, x1, [x2]
|
||||
# CHECK: casal x0, x1, [x2]
|
||||
|
||||
0x41,0x80,0x20,0xf8
|
||||
0x41,0x80,0x20,0x38
|
||||
0x41,0x80,0x60,0x78
|
||||
0xe1,0x83,0xe0,0xf8
|
||||
# CHECK: swp x0, x1, [x2]
|
||||
# CHECK: swpb w0, w1, [x2]
|
||||
# CHECK: swplh w0, w1, [x2]
|
||||
# CHECK: swpal x0, x1, [sp]
|
||||
|
||||
0x41,0x00,0xa0,0xf8
|
||||
0x41,0x10,0x60,0xf8
|
||||
0x41,0x20,0xe0,0xf8
|
||||
0x41,0x30,0x20,0xf8
|
||||
0x41,0x40,0xa0,0xb8
|
||||
0x41,0x50,0x60,0x38
|
||||
0x41,0x60,0xe0,0x78
|
||||
0x41,0x70,0x20,0xb8
|
||||
0xab,0x51,0xe7,0x78
|
||||
# CHECK: ldadda x0, x1, [x2]
|
||||
# CHECK: ldclrl x0, x1, [x2]
|
||||
# CHECK: ldeoral x0, x1, [x2]
|
||||
# CHECK: ldset x0, x1, [x2]
|
||||
# CHECK: ldsmaxa w0, w1, [x2]
|
||||
# CHECK: ldsminlb w0, w1, [x2]
|
||||
# CHECK: ldumaxalh w0, w1, [x2]
|
||||
# CHECK: ldumin w0, w1, [x2]
|
||||
# CHECK: ldsminalh w7, w11, [x13]
|
||||
|
||||
0x5f,0x00,0x60,0x38
|
||||
0x5f,0x10,0x60,0x78
|
||||
0x5f,0x20,0x60,0xb8
|
||||
0x5f,0x30,0x60,0xf8
|
||||
0x5f,0x40,0x20,0x38
|
||||
0x5f,0x50,0x20,0x78
|
||||
0x5f,0x60,0x20,0xb8
|
||||
0x5f,0x70,0x20,0xf8
|
||||
0xff,0x53,0x7d,0xf8
|
||||
# CHECK: staddlb w0, [x2]
|
||||
# CHECK: stclrlh w0, [x2]
|
||||
# CHECK: steorl w0, [x2]
|
||||
# CHECK: stsetl x0, [x2]
|
||||
# CHECK: stsmaxb w0, [x2]
|
||||
# CHECK: stsminh w0, [x2]
|
||||
# CHECK: stumax w0, [x2]
|
||||
# CHECK: stumin x0, [x2]
|
||||
# CHECK: stsminl x29, [sp]
|
||||
|
||||
0x82,0x7c,0x20,0x48
|
||||
0x82,0x7c,0x20,0x08
|
||||
# CHECK: casp x0, x1, x2, x3, [x4]
|
||||
# CHECK: casp w0, w1, w2, w3, [x4]
|
||||
@ -1,38 +0,0 @@
|
||||
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
|
||||
|
||||
0x20,0x7c,0xdf,0x08
|
||||
0x20,0x7c,0xdf,0x48
|
||||
0x20,0x7c,0xdf,0x88
|
||||
0x20,0x7c,0xdf,0xc8
|
||||
0x20,0x7c,0x9f,0x08
|
||||
0x20,0x7c,0x9f,0x48
|
||||
0x20,0x7c,0x9f,0x88
|
||||
0x20,0x7c,0x9f,0xc8
|
||||
# CHECK: ldlarb w0, [x1]
|
||||
# CHECK: ldlarh w0, [x1]
|
||||
# CHECK: ldlar w0, [x1]
|
||||
# CHECK: ldlar x0, [x1]
|
||||
# CHECK: stllrb w0, [x1]
|
||||
# CHECK: stllrh w0, [x1]
|
||||
# CHECK: stllr w0, [x1]
|
||||
# CHECK: stllr x0, [x1]
|
||||
0x00,0xa4,0x18,0xd5
|
||||
0x20,0xa4,0x18,0xd5
|
||||
0x40,0xa4,0x18,0xd5
|
||||
0x60,0xa4,0x18,0xd5
|
||||
0xe0,0xa4,0x18,0xd5
|
||||
# CHECK: msr LORSA_EL1, x0
|
||||
# CHECK: msr LOREA_EL1, x0
|
||||
# CHECK: msr LORN_EL1, x0
|
||||
# CHECK: msr LORC_EL1, x0
|
||||
# CHECK: msr S3_0_C10_C4_7, x0
|
||||
0x00,0xa4,0x38,0xd5
|
||||
0x20,0xa4,0x38,0xd5
|
||||
0x40,0xa4,0x38,0xd5
|
||||
0x60,0xa4,0x38,0xd5
|
||||
0xe0,0xa4,0x38,0xd5
|
||||
# CHECK: mrs x0, LORSA_EL1
|
||||
# CHECK: mrs x0, LOREA_EL1
|
||||
# CHECK: mrs x0, LORN_EL1
|
||||
# CHECK: mrs x0, LORC_EL1
|
||||
# CHECK: mrs x0, LORID_EL1
|
||||
@ -1,12 +0,0 @@
|
||||
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
|
||||
|
||||
0x9f,0x40,0x00,0xd5
|
||||
0x9f,0x41,0x00,0xd5
|
||||
0x9f,0x42,0x00,0xd5
|
||||
0x65,0x42,0x18,0xd5
|
||||
0x6d,0x42,0x38,0xd5
|
||||
# CHECK: msr PAN, #0
|
||||
# CHECK: msr PAN, #1
|
||||
# CHECK-NOT: msr PAN, #2
|
||||
# CHECK: msr PAN, x5
|
||||
# CHECK: mrs x13, PAN
|
||||
@ -1,129 +0,0 @@
|
||||
# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s
|
||||
|
||||
[0x20,0x84,0x02,0x2e] # sqrdmlah v0.8b, v1.8b, v2.8b
|
||||
[0x20,0x8c,0x02,0x2e] # sqrdmlsh v0.8b, v1.8b, v2.8b
|
||||
[0x20,0x84,0xc2,0x2e] # sqrdmlah v0.1d, v1.1d, v2.1d
|
||||
[0x20,0x8c,0xc2,0x2e] # sqrdmlsh v0.1d, v1.1d, v2.1d
|
||||
[0x20,0x84,0x02,0x6e] # sqrdmlah v0.16b, v1.16b, v2.16b
|
||||
[0x20,0x8c,0x02,0x6e] # sqrdmlsh v0.16b, v1.16b, v2.16b
|
||||
[0x20,0x84,0xc2,0x6e] # sqrdmlah v0.2d, v1.2d, v2.2d
|
||||
[0x20,0x8c,0xc2,0x6e] # sqrdmlsh v0.2d, v1.2d, v2.2d
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x84,0x02,0x2e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x8c,0x02,0x2e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x84,0xc2,0x2e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x8c,0xc2,0x2e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x84,0x02,0x6e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x8c,0x02,0x6e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x84,0xc2,0x6e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x8c,0xc2,0x6e]
|
||||
|
||||
[0x20,0x84,0x02,0x7e] # sqrdmlah b0, b1, b2
|
||||
[0x20,0x8c,0x02,0x7e] # sqrdmlsh b0, b1, b2
|
||||
[0x20,0x84,0xc2,0x7e] # sqrdmlah d0, d1, d2
|
||||
[0x20,0x8c,0xc2,0x7e] # sqrdmlsh d0, d1, d2
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x84,0x02,0x7e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x8c,0x02,0x7e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x84,0xc2,0x7e]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0x8c,0xc2,0x7e]
|
||||
|
||||
[0x20,0xd0,0x32,0x2f] # sqrdmlah v0.8b, v1.8b, v2.b[3]
|
||||
[0x20,0xf0,0x32,0x2f] # sqrdmlsh v0.8b, v1.8b, v2.b[3]
|
||||
[0x20,0xd0,0xe2,0x2f] # sqrdmlah v0.1d, v1.1d, v2.d[1]
|
||||
[0x20,0xf0,0xe2,0x2f] # sqrdmlsh v0.1d, v1.1d, v2.d[1]
|
||||
[0x20,0xd0,0x32,0x6f] # sqrdmlah v0.16b, v1.16b, v2.b[3]
|
||||
[0x20,0xf0,0x32,0x6f] # sqrdmlsh v0.16b, v1.16b, v2.b[3]
|
||||
[0x20,0xd8,0xe2,0x6f] # sqrdmlah v0.2d, v1.2d, v2.d[3]
|
||||
[0x20,0xf8,0xe2,0x6f] # sqrdmlsh v0.2d, v1.2d, v2.d[3]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xd0,0x32,0x2f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xf0,0x32,0x2f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xd0,0xe2,0x2f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xf0,0xe2,0x2f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xd0,0x32,0x6f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xf0,0x32,0x6f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xd8,0xe2,0x6f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xf8,0xe2,0x6f]
|
||||
|
||||
[0x20,0xd0,0x32,0x7f] # sqrdmlah b0, b1, v2.b[3]
|
||||
[0x20,0xf0,0x32,0x7f] # sqrdmlsh b0, b1, v2.b[3]
|
||||
[0x20,0xd8,0xe2,0x7f] # sqrdmlah d0, d1, v2.d[3]
|
||||
[0x20,0xf8,0xe2,0x7f] # sqrdmlsh d0, d1, v2.d[3]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xd0,0x32,0x7f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xf0,0x32,0x7f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xd8,0xe2,0x7f]
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: [0x20,0xf8,0xe2,0x7f]
|
||||
|
||||
[0x20,0x84,0x42,0x2e]
|
||||
[0x20,0x8c,0x42,0x2e]
|
||||
[0x20,0x84,0x82,0x2e]
|
||||
[0x20,0x8c,0x82,0x2e]
|
||||
[0x20,0x84,0x42,0x6e]
|
||||
[0x20,0x8c,0x42,0x6e]
|
||||
[0x20,0x84,0x82,0x6e]
|
||||
[0x20,0x8c,0x82,0x6e]
|
||||
# CHECK: sqrdmlah v0.4h, v1.4h, v2.4h
|
||||
# CHECK: sqrdmlsh v0.4h, v1.4h, v2.4h
|
||||
# CHECK: sqrdmlah v0.2s, v1.2s, v2.2s
|
||||
# CHECK: sqrdmlsh v0.2s, v1.2s, v2.2s
|
||||
# CHECK: sqrdmlah v0.8h, v1.8h, v2.8h
|
||||
# CHECK: sqrdmlsh v0.8h, v1.8h, v2.8h
|
||||
# CHECK: sqrdmlah v0.4s, v1.4s, v2.4s
|
||||
# CHECK: sqrdmlsh v0.4s, v1.4s, v2.4s
|
||||
|
||||
[0x20,0x84,0x42,0x7e]
|
||||
[0x20,0x8c,0x42,0x7e]
|
||||
[0x20,0x84,0x82,0x7e]
|
||||
[0x20,0x8c,0x82,0x7e]
|
||||
# CHECK: sqrdmlah h0, h1, h2
|
||||
# CHECK: sqrdmlsh h0, h1, h2
|
||||
# CHECK: sqrdmlah s0, s1, s2
|
||||
# CHECK: sqrdmlsh s0, s1, s2
|
||||
|
||||
0x20,0xd0,0x72,0x2f
|
||||
0x20,0xf0,0x72,0x2f
|
||||
0x20,0xd0,0xa2,0x2f
|
||||
0x20,0xf0,0xa2,0x2f
|
||||
0x20,0xd0,0x72,0x6f
|
||||
0x20,0xf0,0x72,0x6f
|
||||
0x20,0xd8,0xa2,0x6f
|
||||
0x20,0xf8,0xa2,0x6f
|
||||
# CHECK: sqrdmlah v0.4h, v1.4h, v2.h[3]
|
||||
# CHECK: sqrdmlsh v0.4h, v1.4h, v2.h[3]
|
||||
# CHECK: sqrdmlah v0.2s, v1.2s, v2.s[1]
|
||||
# CHECK: sqrdmlsh v0.2s, v1.2s, v2.s[1]
|
||||
# CHECK: sqrdmlah v0.8h, v1.8h, v2.h[3]
|
||||
# CHECK: sqrdmlsh v0.8h, v1.8h, v2.h[3]
|
||||
# CHECK: sqrdmlah v0.4s, v1.4s, v2.s[3]
|
||||
# CHECK: sqrdmlsh v0.4s, v1.4s, v2.s[3]
|
||||
|
||||
0x20,0xd0,0x72,0x7f
|
||||
0x20,0xf0,0x72,0x7f
|
||||
0x20,0xd8,0xa2,0x7f
|
||||
0x20,0xf8,0xa2,0x7f
|
||||
# CHECK: sqrdmlah h0, h1, v2.h[3]
|
||||
# CHECK: sqrdmlsh h0, h1, v2.h[3]
|
||||
# CHECK: sqrdmlah s0, s1, v2.s[3]
|
||||
# CHECK: sqrdmlsh s0, s1, v2.s[3]
|
||||
@ -1,56 +0,0 @@
|
||||
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
|
||||
|
||||
0x20,0x20,0x1c,0xd5
|
||||
0x20,0xd0,0x1c,0xd5
|
||||
0x00,0xe3,0x1c,0xd5
|
||||
0x40,0xe3,0x1c,0xd5
|
||||
0x20,0xe3,0x1c,0xd5
|
||||
0x00,0x10,0x1d,0xd5
|
||||
0x40,0x10,0x1d,0xd5
|
||||
0x00,0x20,0x1d,0xd5
|
||||
0x20,0x20,0x1d,0xd5
|
||||
0x40,0x20,0x1d,0xd5
|
||||
0x00,0x51,0x1d,0xd5
|
||||
0x20,0x51,0x1d,0xd5
|
||||
0x00,0x52,0x1d,0xd5
|
||||
0x00,0x60,0x1d,0xd5
|
||||
0x00,0xa2,0x1d,0xd5
|
||||
0x00,0xa3,0x1d,0xd5
|
||||
0x00,0xc0,0x1d,0xd5
|
||||
0x20,0xd0,0x1d,0xd5
|
||||
0x00,0xe1,0x1d,0xd5
|
||||
0x00,0xe2,0x1d,0xd5
|
||||
0x20,0xe2,0x1d,0xd5
|
||||
0x40,0xe2,0x1d,0xd5
|
||||
0x00,0xe3,0x1d,0xd5
|
||||
0x20,0xe3,0x1d,0xd5
|
||||
0x40,0xe3,0x1d,0xd5
|
||||
0x00,0x40,0x1d,0xd5
|
||||
0x20,0x40,0x1d,0xd5
|
||||
# CHECK: msr TTBR1_EL2, x0
|
||||
# CHECK: msr CONTEXTIDR_EL2, x0
|
||||
# CHECK: msr CNTHV_TVAL_EL2, x0
|
||||
# CHECK: msr CNTHV_CVAL_EL2, x0
|
||||
# CHECK: msr CNTHV_CTL_EL2, x0
|
||||
# CHECK: msr SCTLR_EL12, x0
|
||||
# CHECK: msr CPACR_EL12, x0
|
||||
# CHECK: msr TTBR0_EL12, x0
|
||||
# CHECK: msr TTBR1_EL12, x0
|
||||
# CHECK: msr TCR_EL12, x0
|
||||
# CHECK: msr AFSR0_EL12, x0
|
||||
# CHECK: msr AFSR1_EL12, x0
|
||||
# CHECK: msr ESR_EL12, x0
|
||||
# CHECK: msr FAR_EL12, x0
|
||||
# CHECK: msr MAIR_EL12, x0
|
||||
# CHECK: msr AMAIR_EL12, x0
|
||||
# CHECK: msr VBAR_EL12, x0
|
||||
# CHECK: msr CONTEXTIDR_EL12, x0
|
||||
# CHECK: msr CNTKCTL_EL12, x0
|
||||
# CHECK: msr CNTP_TVAL_EL02, x0
|
||||
# CHECK: msr CNTP_CTL_EL02, x0
|
||||
# CHECK: msr CNTP_CVAL_EL02, x0
|
||||
# CHECK: msr CNTV_TVAL_EL02, x0
|
||||
# CHECK: msr CNTV_CTL_EL02, x0
|
||||
# CHECK: msr CNTV_CVAL_EL02, x0
|
||||
# CHECK: msr SPSR_EL12, x0
|
||||
# CHECK: msr ELR_EL12, x0
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user