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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
This commit is contained in:
Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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19
external/llvm/test/MC/AArch64/SVE/add-diagnostics.s vendored
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@@ -1,19 +0,0 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Register z32 does not exist.
add z22.h, z10.h, z32.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: add z22.h, z10.h, z32.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Invalid element kind.
add z20.h, z2.h, z31.x
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
// CHECK-NEXT: add z20.h, z2.h, z31.x
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Element size specifiers should match.
add z27.h, z11.h, z27.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: add z27.h, z11.h, z27.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

104
external/llvm/test/MC/AArch64/SVE/add.s vendored
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@@ -1,104 +0,0 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
add z31.s, z31.s, z31.s
// CHECK-INST: add z31.s, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x03,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 03 bf 04 <unknown>
add z23.d, z13.d, z8.d
// CHECK-INST: add z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0x01,0xe8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 01 e8 04 <unknown>
add z0.s, z0.s, z0.s
// CHECK-INST: add z0.s, z0.s, z0.s
// CHECK-ENCODING: [0x00,0x00,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 a0 04 <unknown>
add z31.d, z31.d, z31.d
// CHECK-INST: add z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x03,0xff,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 03 ff 04 <unknown>
add z21.b, z10.b, z21.b
// CHECK-INST: add z21.b, z10.b, z21.b
// CHECK-ENCODING: [0x55,0x01,0x35,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 01 35 04 <unknown>
add z31.b, z31.b, z31.b
// CHECK-INST: add z31.b, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x03,0x3f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 03 3f 04 <unknown>
add z0.h, z0.h, z0.h
// CHECK-INST: add z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x00,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 60 04 <unknown>
add z23.b, z13.b, z8.b
// CHECK-INST: add z23.b, z13.b, z8.b
// CHECK-ENCODING: [0xb7,0x01,0x28,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 01 28 04 <unknown>
add z0.d, z0.d, z0.d
// CHECK-INST: add z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x00,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 e0 04 <unknown>
add z31.h, z31.h, z31.h
// CHECK-INST: add z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x03,0x7f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 03 7f 04 <unknown>
add z0.b, z0.b, z0.b
// CHECK-INST: add z0.b, z0.b, z0.b
// CHECK-ENCODING: [0x00,0x00,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 20 04 <unknown>
add z21.d, z10.d, z21.d
// CHECK-INST: add z21.d, z10.d, z21.d
// CHECK-ENCODING: [0x55,0x01,0xf5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 01 f5 04 <unknown>
add z21.h, z10.h, z21.h
// CHECK-INST: add z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x01,0x75,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 01 75 04 <unknown>
add z21.s, z10.s, z21.s
// CHECK-INST: add z21.s, z10.s, z21.s
// CHECK-ENCODING: [0x55,0x01,0xb5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 01 b5 04 <unknown>
add z23.h, z13.h, z8.h
// CHECK-INST: add z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x01,0x68,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 01 68 04 <unknown>
add z23.s, z13.s, z8.s
// CHECK-INST: add z23.s, z13.s, z8.s
// CHECK-ENCODING: [0xb7,0x01,0xa8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 01 a8 04 <unknown>

20
external/llvm/test/MC/AArch64/SVE/dot-req-diagnostics.s vendored
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@@ -1,20 +0,0 @@
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+sve < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ERROR %s
foo:
// CHECK: error: sve predicate register without type specifier expected
pbarb .req p1.b
// CHECK: error: sve predicate register without type specifier expected
pbarh .req p1.h
// CHECK: error: sve predicate register without type specifier expected
pbars .req p1.s
// CHECK: error: sve predicate register without type specifier expected
pbard .req p1.d
// CHECK: error: sve vector register without type specifier expected
zbarb .req z1.b
// CHECK: error: sve vector register without type specifier expected
zbarh .req z1.h
// CHECK: error: sve vector register without type specifier expected
zbars .req z1.s
// CHECK: error: sve vector register without type specifier expected
zbard .req z1.d

9
external/llvm/test/MC/AArch64/SVE/dot-req.s vendored
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@@ -1,9 +0,0 @@
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sve -show-encoding < %s 2>&1 | FileCheck %s
foo:
// CHECK-NOT: error:
pbar .req p1
// CHECK: add z0.s, z1.s, z2.s
zbar .req z1
add z0.s, zbar.s, z2.s

19
external/llvm/test/MC/AArch64/SVE/sub-diagnostics.s vendored
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@@ -1,19 +0,0 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Register z32 does not exist.
sub z3.h, z26.h, z32.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sub z3.h, z26.h, z32.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Invalid element kind.
sub z4.h, z27.h, z31.x
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
// CHECK-NEXT: sub z4.h, z27.h, z31.x
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Element size specifiers should match.
sub z0.h, z8.h, z8.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sub z0.h, z8.h, z8.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

104
external/llvm/test/MC/AArch64/SVE/sub.s vendored
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@@ -1,104 +0,0 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sub z0.h, z0.h, z0.h
// CHECK-INST: sub z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x04,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 04 60 04 <unknown>
sub z21.b, z10.b, z21.b
// CHECK-INST: sub z21.b, z10.b, z21.b
// CHECK-ENCODING: [0x55,0x05,0x35,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 05 35 04 <unknown>
sub z31.h, z31.h, z31.h
// CHECK-INST: sub z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x07,0x7f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 07 7f 04 <unknown>
sub z21.h, z10.h, z21.h
// CHECK-INST: sub z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x05,0x75,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 05 75 04 <unknown>
sub z31.b, z31.b, z31.b
// CHECK-INST: sub z31.b, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x07,0x3f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 07 3f 04 <unknown>
sub z0.s, z0.s, z0.s
// CHECK-INST: sub z0.s, z0.s, z0.s
// CHECK-ENCODING: [0x00,0x04,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 04 a0 04 <unknown>
sub z23.b, z13.b, z8.b
// CHECK-INST: sub z23.b, z13.b, z8.b
// CHECK-ENCODING: [0xb7,0x05,0x28,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 05 28 04 <unknown>
sub z21.d, z10.d, z21.d
// CHECK-INST: sub z21.d, z10.d, z21.d
// CHECK-ENCODING: [0x55,0x05,0xf5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 05 f5 04 <unknown>
sub z21.s, z10.s, z21.s
// CHECK-INST: sub z21.s, z10.s, z21.s
// CHECK-ENCODING: [0x55,0x05,0xb5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 05 b5 04 <unknown>
sub z0.b, z0.b, z0.b
// CHECK-INST: sub z0.b, z0.b, z0.b
// CHECK-ENCODING: [0x00,0x04,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 04 20 04 <unknown>
sub z23.d, z13.d, z8.d
// CHECK-INST: sub z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0x05,0xe8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 05 e8 04 <unknown>
sub z23.s, z13.s, z8.s
// CHECK-INST: sub z23.s, z13.s, z8.s
// CHECK-ENCODING: [0xb7,0x05,0xa8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 05 a8 04 <unknown>
sub z31.d, z31.d, z31.d
// CHECK-INST: sub z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x07,0xff,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 07 ff 04 <unknown>
sub z23.h, z13.h, z8.h
// CHECK-INST: sub z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x05,0x68,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 05 68 04 <unknown>
sub z0.d, z0.d, z0.d
// CHECK-INST: sub z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x04,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 04 e0 04 <unknown>
sub z31.s, z31.s, z31.s
// CHECK-INST: sub z31.s, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x07,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 07 bf 04 <unknown>

43
external/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s vendored
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@@ -1,43 +0,0 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Invalid element kind.
zip1 z10.h, z22.h, z31.x
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
// CHECK-NEXT: zip1 z10.h, z22.h, z31.x
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Element size specifiers should match.
zip1 z10.h, z3.h, z15.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: zip1 z10.h, z3.h, z15.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Too few operands
zip1 z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
// CHECK-NEXT: zip1 z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// z32 is not a valid SVE data register
zip1 z1.s, z2.s, z32.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: zip1 z1.s, z2.s, z32.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// p16 is not a valid SVE predicate register
zip1 p1.s, p2.s, p16.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: zip1 p1.s, p2.s, p16.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining data and predicate registers as operands
zip1 z1.s, z2.s, p3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: zip1 z1.s, z2.s, p3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining predicate and data registers as operands
zip1 p1.s, p2.s, z3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: zip1 p1.s, p2.s, z3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

104
external/llvm/test/MC/AArch64/SVE/zip1.s vendored
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@@ -1,104 +0,0 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
zip1 z0.b, z0.b, z0.b
// CHECK-INST: zip1 z0.b, z0.b, z0.b
// CHECK-ENCODING: [0x00,0x60,0x20,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 20 05 <unknown>
zip1 z0.h, z0.h, z0.h
// CHECK-INST: zip1 z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x60,0x60,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 60 05 <unknown>
zip1 z0.s, z0.s, z0.s
// CHECK-INST: zip1 z0.s, z0.s, z0.s
// CHECK-ENCODING: [0x00,0x60,0xa0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 a0 05 <unknown>
zip1 z0.d, z0.d, z0.d
// CHECK-INST: zip1 z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x60,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 e0 05 <unknown>
zip1 z31.b, z31.b, z31.b
// CHECK-INST: zip1 z31.b, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x63,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 63 3f 05 <unknown>
zip1 z31.h, z31.h, z31.h
// CHECK-INST: zip1 z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x63,0x7f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 63 7f 05 <unknown>
zip1 z31.s, z31.s, z31.s
// CHECK-INST: zip1 z31.s, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x63,0xbf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 63 bf 05 <unknown>
zip1 z31.d, z31.d, z31.d
// CHECK-INST: zip1 z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x63,0xff,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 63 ff 05 <unknown>
zip1 p0.b, p0.b, p0.b
// CHECK-INST: zip1 p0.b, p0.b, p0.b
// CHECK-ENCODING: [0x00,0x40,0x20,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 20 05 <unknown>
zip1 p0.h, p0.h, p0.h
// CHECK-INST: zip1 p0.h, p0.h, p0.h
// CHECK-ENCODING: [0x00,0x40,0x60,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 60 05 <unknown>
zip1 p0.s, p0.s, p0.s
// CHECK-INST: zip1 p0.s, p0.s, p0.s
// CHECK-ENCODING: [0x00,0x40,0xa0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 a0 05 <unknown>
zip1 p0.d, p0.d, p0.d
// CHECK-INST: zip1 p0.d, p0.d, p0.d
// CHECK-ENCODING: [0x00,0x40,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 e0 05 <unknown>
zip1 p15.b, p15.b, p15.b
// CHECK-INST: zip1 p15.b, p15.b, p15.b
// CHECK-ENCODING: [0xef,0x41,0x2f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 41 2f 05 <unknown>
zip1 p15.s, p15.s, p15.s
// CHECK-INST: zip1 p15.s, p15.s, p15.s
// CHECK-ENCODING: [0xef,0x41,0xaf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 41 af 05 <unknown>
zip1 p15.h, p15.h, p15.h
// CHECK-INST: zip1 p15.h, p15.h, p15.h
// CHECK-ENCODING: [0xef,0x41,0x6f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 41 6f 05 <unknown>
zip1 p15.d, p15.d, p15.d
// CHECK-INST: zip1 p15.d, p15.d, p15.d
// CHECK-ENCODING: [0xef,0x41,0xef,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 41 ef 05 <unknown>

43
external/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s vendored
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@@ -1,43 +0,0 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Invalid element kind.
zip2 z6.h, z23.h, z31.x
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
// CHECK-NEXT: zip2 z6.h, z23.h, z31.x
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Element size specifiers should match.
zip2 z0.h, z30.h, z24.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: zip2 z0.h, z30.h, z24.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Too few operands
zip2 z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
// CHECK-NEXT: zip2 z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// z32 is not a valid SVE data register
zip2 z1.s, z2.s, z32.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: zip2 z1.s, z2.s, z32.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// p16 is not a valid SVE predicate register
zip2 p1.s, p2.s, p16.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: zip2 p1.s, p2.s, p16.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining data and predicate registers as operands
zip2 z1.s, z2.s, p3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: zip2 z1.s, z2.s, p3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining predicate and data registers as operands
zip2 p1.s, p2.s, z3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: zip2 p1.s, p2.s, z3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

104
external/llvm/test/MC/AArch64/SVE/zip2.s vendored
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@@ -1,104 +0,0 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
zip2 z0.b, z0.b, z0.b
// CHECK-INST: zip2 z0.b, z0.b, z0.b
// CHECK-ENCODING: [0x00,0x64,0x20,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 64 20 05 <unknown>
zip2 z0.h, z0.h, z0.h
// CHECK-INST: zip2 z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x64,0x60,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 64 60 05 <unknown>
zip2 z0.s, z0.s, z0.s
// CHECK-INST: zip2 z0.s, z0.s, z0.s
// CHECK-ENCODING: [0x00,0x64,0xa0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 64 a0 05 <unknown>
zip2 z0.d, z0.d, z0.d
// CHECK-INST: zip2 z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x64,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 64 e0 05 <unknown>
zip2 z31.b, z31.b, z31.b
// CHECK-INST: zip2 z31.b, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x67,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 67 3f 05 <unknown>
zip2 z31.h, z31.h, z31.h
// CHECK-INST: zip2 z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x67,0x7f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 67 7f 05 <unknown>
zip2 z31.s, z31.s, z31.s
// CHECK-INST: zip2 z31.s, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x67,0xbf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 67 bf 05 <unknown>
zip2 z31.d, z31.d, z31.d
// CHECK-INST: zip2 z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x67,0xff,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 67 ff 05 <unknown>
zip2 p0.b, p0.b, p0.b
// CHECK-INST: zip2 p0.b, p0.b, p0.b
// CHECK-ENCODING: [0x00,0x44,0x20,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 44 20 05 <unknown>
zip2 p0.h, p0.h, p0.h
// CHECK-INST: zip2 p0.h, p0.h, p0.h
// CHECK-ENCODING: [0x00,0x44,0x60,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 44 60 05 <unknown>
zip2 p0.s, p0.s, p0.s
// CHECK-INST: zip2 p0.s, p0.s, p0.s
// CHECK-ENCODING: [0x00,0x44,0xa0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 44 a0 05 <unknown>
zip2 p0.d, p0.d, p0.d
// CHECK-INST: zip2 p0.d, p0.d, p0.d
// CHECK-ENCODING: [0x00,0x44,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 44 e0 05 <unknown>
zip2 p15.b, p15.b, p15.b
// CHECK-INST: zip2 p15.b, p15.b, p15.b
// CHECK-ENCODING: [0xef,0x45,0x2f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 45 2f 05 <unknown>
zip2 p15.h, p15.h, p15.h
// CHECK-INST: zip2 p15.h, p15.h, p15.h
// CHECK-ENCODING: [0xef,0x45,0x6f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 45 6f 05 <unknown>
zip2 p15.s, p15.s, p15.s
// CHECK-INST: zip2 p15.s, p15.s, p15.s
// CHECK-ENCODING: [0xef,0x45,0xaf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 45 af 05 <unknown>
zip2 p15.d, p15.d, p15.d
// CHECK-INST: zip2 p15.d, p15.d, p15.d
// CHECK-ENCODING: [0xef,0x45,0xef,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 45 ef 05 <unknown>

23
external/llvm/test/MC/AArch64/adrp-relocation.s vendored
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@@ -1,23 +0,0 @@
// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s| llvm-readobj -r - | FileCheck %s
// RUN: llvm-mc -target-abi=ilp32 -triple=aarch64-linux-gnu -filetype=obj \
// RUN: -o - %s| llvm-readobj -r - | FileCheck -check-prefix=CHECK-ILP32 %s
.text
// This tests that LLVM doesn't think it can deal with the relocation on the ADRP
// itself (even though it knows everything about the relative offsets of sym and
// the adrp instruction) because its value depends on where this object file's
// .text section gets relocated in memory.
adrp x0, sym
adrp x0, :got:sym
adrp x0, :gottprel:sym
adrp x0, :tlsdesc:sym
.global sym
sym:
// CHECK: R_AARCH64_ADR_PREL_PG_HI21 sym
// CHECK: R_AARCH64_ADR_GOT_PAGE sym
// CHECK: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
// CHECK: R_AARCH64_TLSDESC_ADR_PAGE21 sym
// CHECK-ILP32: R_AARCH64_P32_ADR_PREL_PG_HI21 sym
// CHECK-ILP32: R_AARCH64_P32_ADR_GOT_PAGE sym
// CHECK-ILP32: R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym
// CHECK-ILP32: R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym

115
external/llvm/test/MC/AArch64/alias-addsubimm.s vendored
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@@ -1,115 +0,0 @@
// RUN: llvm-mc -triple=aarch64-none-linux-gnu < %s | FileCheck %s
// RUN: not llvm-mc -mattr=+no-neg-immediates -triple=aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-NEG-IMM
// CHECK: sub w0, w2, #2, lsl #12
// CHECK: sub w0, w2, #2, lsl #12
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
sub w0, w2, #2, lsl 12
add w0, w2, #-2, lsl 12
// CHECK: sub x1, x3, #2, lsl #12
// CHECK: sub x1, x3, #2, lsl #12
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
sub x1, x3, #2, lsl 12
add x1, x3, #-2, lsl 12
// CHECK: sub x1, x3, #4
// CHECK: sub x1, x3, #4
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
sub x1, x3, #4
add x1, x3, #-4
// CHECK: sub x1, x3, #4095
// CHECK: sub x1, x3, #4095
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
sub x1, x3, #4095, lsl 0
add x1, x3, #-4095, lsl 0
// CHECK: sub x3, x4, #0
sub x3, x4, #0
// CHECK: add w0, w2, #2, lsl #12
// CHECK: add w0, w2, #2, lsl #12
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
add w0, w2, #2, lsl 12
sub w0, w2, #-2, lsl 12
// CHECK: add x1, x3, #2, lsl #12
// CHECK: add x1, x3, #2, lsl #12
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
add x1, x3, #2, lsl 12
sub x1, x3, #-2, lsl 12
// CHECK: add x1, x3, #4
// CHECK: add x1, x3, #4
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
add x1, x3, #4
sub x1, x3, #-4
// CHECK: add x1, x3, #4095
// CHECK: add x1, x3, #4095
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
add x1, x3, #4095, lsl 0
sub x1, x3, #-4095, lsl 0
// CHECK: add x2, x5, #0
add x2, x5, #0
// CHECK: subs w0, w2, #2, lsl #12
// CHECK: subs w0, w2, #2, lsl #12
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
subs w0, w2, #2, lsl 12
adds w0, w2, #-2, lsl 12
// CHECK: subs x1, x3, #2, lsl #12
// CHECK: subs x1, x3, #2, lsl #12
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
subs x1, x3, #2, lsl 12
adds x1, x3, #-2, lsl 12
// CHECK: subs x1, x3, #4
// CHECK: subs x1, x3, #4
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
subs x1, x3, #4
adds x1, x3, #-4
// CHECK: subs x1, x3, #4095
// CHECK: subs x1, x3, #4095
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
subs x1, x3, #4095, lsl 0
adds x1, x3, #-4095, lsl 0
// CHECK: subs x3, x4, #0
subs x3, x4, #0
// CHECK: adds w0, w2, #2, lsl #12
// CHECK: adds w0, w2, #2, lsl #12
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
adds w0, w2, #2, lsl 12
subs w0, w2, #-2, lsl 12
// CHECK: adds x1, x3, #2, lsl #12
// CHECK: adds x1, x3, #2, lsl #12
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
adds x1, x3, #2, lsl 12
subs x1, x3, #-2, lsl 12
// CHECK: adds x1, x3, #4
// CHECK: adds x1, x3, #4
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
adds x1, x3, #4
subs x1, x3, #-4
// CHECK: adds x1, x3, #4095
// CHECK: adds x1, x3, #4095
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
adds x1, x3, #4095, lsl 0
subs x1, x3, #-4095, lsl 0
// CHECK: adds x2, x5, #0
adds x2, x5, #0
// CHECK: {{adds xzr,|cmn}} x5, #5
// CHECK: {{adds xzr,|cmn}} x5, #5
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
cmn x5, #5
cmp x5, #-5
// CHECK: {{subs xzr,|cmp}} x6, #4095
// CHECK: {{subs xzr,|cmp}} x6, #4095
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
cmp x6, #4095
cmn x6, #-4095
// CHECK: {{adds wzr,|cmn}} w7, #5
// CHECK: {{adds wzr,|cmn}} w7, #5
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
cmn w7, #5
cmp w7, #-5
// CHECK: {{subs wzr,|cmp}} w8, #4095
// CHECK: {{subs wzr,|cmp}} w8, #4095
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
cmp w8, #4095
cmn w8, #-4095

50
external/llvm/test/MC/AArch64/alias-logicalimm.s vendored
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@@ -1,50 +0,0 @@
// RUN: llvm-mc -triple=aarch64-none-linux-gnu < %s | FileCheck %s
// RUN: not llvm-mc -mattr=+no-neg-immediates -triple=aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-NEG-IMM
// CHECK: and x0, x1, #0xfffffffffffffffd
// CHECK: and x0, x1, #0xfffffffffffffffd
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
and x0, x1, #~2
bic x0, x1, #2
// CHECK: and w0, w1, #0xfffffffd
// CHECK: and w0, w1, #0xfffffffd
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
and w0, w1, #~2
bic w0, w1, #2
// CHECK: ands x0, x1, #0xfffffffffffffffd
// CHECK: ands x0, x1, #0xfffffffffffffffd
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
ands x0, x1, #~2
bics x0, x1, #2
// CHECK: ands w0, w1, #0xfffffffd
// CHECK: ands w0, w1, #0xfffffffd
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
ands w0, w1, #~2
bics w0, w1, #2
// CHECK: orr x0, x1, #0xfffffffffffffffd
// CHECK: orr x0, x1, #0xfffffffffffffffd
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
orr x0, x1, #~2
orn x0, x1, #2
// CHECK: orr w2, w1, #0xfffffffc
// CHECK: orr w2, w1, #0xfffffffc
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
orr w2, w1, #~3
orn w2, w1, #3
// CHECK: eor x0, x1, #0xfffffffffffffffd
// CHECK: eor x0, x1, #0xfffffffffffffffd
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
eor x0, x1, #~2
eon x0, x1, #2
// CHECK: eor w2, w1, #0xfffffffc
// CHECK: eor w2, w1, #0xfffffffc
// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
eor w2, w1, #~3
eon w2, w1, #3

264
external/llvm/test/MC/AArch64/arm32-elf-relocs.s vendored
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@@ -1,264 +0,0 @@
// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -o - < %s | \
// RUN: FileCheck %s
// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding \
// RUN: -o - < %s | FileCheck --check-prefix=CHECK-ENCODING %s
// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -filetype=obj < %s | \
// RUN: llvm-objdump -triple=arm64-linux-gnu - -r | \
// RUN: FileCheck %s --check-prefix=CHECK-OBJ-ILP32
add x0, x2, #:lo12:sym
// CHECK: add x0, x2, :lo12:sym
// CHECK-OBJ-ILP32: 0 R_AARCH64_P32_ADD_ABS_LO12_NC sym
add x5, x7, #:dtprel_lo12:sym
// CHECK: add x5, x7, :dtprel_lo12:sym
// CHECK-OBJ-ILP32: 4 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym
add x9, x12, #:dtprel_lo12_nc:sym
// CHECK: add x9, x12, :dtprel_lo12_nc:sym
// CHECK-OBJ-ILP32: 8 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym
add x20, x30, #:tprel_lo12:sym
// CHECK: add x20, x30, :tprel_lo12:sym
// CHECK-OBJ-ILP32: c R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym
add x9, x12, #:tprel_lo12_nc:sym
// CHECK: add x9, x12, :tprel_lo12_nc:sym
// CHECK-OBJ-ILP32: 10 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym
add x5, x0, #:tlsdesc_lo12:sym
// CHECK: add x5, x0, :tlsdesc_lo12:sym
// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12 sym
add x0, x2, #:lo12:sym+8
// CHECK: add x0, x2, :lo12:sym
// CHECK-OBJ-ILP32: 18 R_AARCH64_P32_ADD_ABS_LO12_NC sym+8
add x5, x7, #:dtprel_lo12:sym+1
// CHECK: add x5, x7, :dtprel_lo12:sym+1
// CHECK-OBJ-ILP32: 1c R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym+1
add x9, x12, #:dtprel_lo12_nc:sym+2
// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
// CHECK-OBJ-ILP32:20 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym+2
add x20, x30, #:tprel_lo12:sym+12
// CHECK: add x20, x30, :tprel_lo12:sym+12
// CHECK-OBJ-ILP32: 24 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym+12
add x9, x12, #:tprel_lo12_nc:sym+54
// CHECK: add x9, x12, :tprel_lo12_nc:sym+54
// CHECK-OBJ-ILP32: 28 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym+54
add x5, x0, #:tlsdesc_lo12:sym+70
// CHECK: add x5, x0, :tlsdesc_lo12:sym+70
// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12 sym+70
.hword sym + 4 - .
// CHECK-OBJ-ILP32: 30 R_AARCH64_P32_PREL16 sym+4
.word sym - . + 8
// CHECK-OBJ-ILP32: 32 R_AARCH64_P32_PREL32 sym+8
.hword sym
// CHECK-OBJ-ILP32: 36 R_AARCH64_P32_ABS16 sym
.word sym+1
// CHECK-OBJ-ILP32: 38 R_AARCH64_P32_ABS32 sym+1
adrp x0, sym
// CHECK: adrp x0, sym
// CHECK-OBJ-ILP32: 3c R_AARCH64_P32_ADR_PREL_PG_HI21 sym
adrp x15, :got:sym
// CHECK: adrp x15, :got:sym
// CHECK-OBJ-ILP32: 40 R_AARCH64_P32_ADR_GOT_PAGE sym
adrp x29, :gottprel:sym
// CHECK: adrp x29, :gottprel:sym
// CHECK-OBJ-ILP32: 44 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym
adrp x2, :tlsdesc:sym
// CHECK: adrp x2, :tlsdesc:sym
// CHECK-OBJ-ILP32: 48 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym
// LLVM is not competent enough to do this relocation because the
// page boundary could occur anywhere after linking. A relocation
// is needed.
adrp x3, trickQuestion
.global trickQuestion
trickQuestion:
// CHECK: adrp x3, trickQuestion
// CHECK-OBJ-ILP32: 4c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion
ldrb w2, [x3, :lo12:sym]
ldrsb w5, [x7, #:lo12:sym]
ldrsb x11, [x13, :lo12:sym]
ldr b17, [x19, #:lo12:sym]
// CHECK: ldrb w2, [x3, :lo12:sym]
// CHECK: ldrsb w5, [x7, :lo12:sym]
// CHECK: ldrsb x11, [x13, :lo12:sym]
// CHECK: ldr b17, [x19, :lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
ldrb w23, [x29, #:dtprel_lo12_nc:sym]
ldrsb w23, [x19, #:dtprel_lo12:sym]
ldrsb x17, [x13, :dtprel_lo12_nc:sym]
ldr b11, [x7, #:dtprel_lo12:sym]
// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
ldrb w1, [x2, :tprel_lo12:sym]
ldrsb w3, [x4, #:tprel_lo12_nc:sym]
ldrsb x5, [x6, :tprel_lo12:sym]
ldr b7, [x8, #:tprel_lo12_nc:sym]
// CHECK: ldrb w1, [x2, :tprel_lo12:sym]
// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
ldrh w2, [x3, #:lo12:sym]
ldrsh w5, [x7, :lo12:sym]
ldrsh x11, [x13, #:lo12:sym]
ldr h17, [x19, :lo12:sym]
// CHECK: ldrh w2, [x3, :lo12:sym]
// CHECK: ldrsh w5, [x7, :lo12:sym]
// CHECK: ldrsh x11, [x13, :lo12:sym]
// CHECK: ldr h17, [x19, :lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
ldrh w23, [x29, #:dtprel_lo12_nc:sym]
ldrsh w23, [x19, :dtprel_lo12:sym]
ldrsh x17, [x13, :dtprel_lo12_nc:sym]
ldr h11, [x7, #:dtprel_lo12:sym]
// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
ldrh w1, [x2, :tprel_lo12:sym]
ldrsh w3, [x4, #:tprel_lo12_nc:sym]
ldrsh x5, [x6, :tprel_lo12:sym]
ldr h7, [x8, #:tprel_lo12_nc:sym]
// CHECK: ldrh w1, [x2, :tprel_lo12:sym]
// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
ldr w1, [x2, #:lo12:sym]
ldrsw x3, [x4, #:lo12:sym]
ldr s4, [x5, :lo12:sym]
// CHECK: ldr w1, [x2, :lo12:sym]
// CHECK: ldrsw x3, [x4, :lo12:sym]
// CHECK: ldr s4, [x5, :lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
ldr w1, [x2, :dtprel_lo12:sym]
ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
ldr s4, [x5, #:dtprel_lo12_nc:sym]
// CHECK: ldr w1, [x2, :dtprel_lo12:sym]
// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
ldr w1, [x2, #:tprel_lo12:sym]
ldrsw x3, [x4, :tprel_lo12_nc:sym]
ldr s4, [x5, :tprel_lo12_nc:sym]
// CHECK: ldr w1, [x2, :tprel_lo12:sym]
// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
ldr x28, [x27, :lo12:sym]
ldr d26, [x25, :lo12:sym]
// CHECK: ldr x28, [x27, :lo12:sym]
// CHECK: ldr d26, [x25, :lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym
ldr w24, [x23, :got_lo12:sym]
ldr s22, [x21, :got_lo12:sym]
// CHECK: ldr w24, [x23, :got_lo12:sym]
// CHECK: ldr s22, [x21, :got_lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym
ldr x24, [x23, :dtprel_lo12_nc:sym]
ldr d22, [x21, :dtprel_lo12:sym]
// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
// CHECK: ldr d22, [x21, :dtprel_lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym
ldr q24, [x23, :dtprel_lo12_nc:sym]
ldr q22, [x21, :dtprel_lo12:sym]
// CHECK: ldr q24, [x23, :dtprel_lo12_nc:sym]
// CHECK: ldr q22, [x21, :dtprel_lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 sym
ldr x24, [x23, :tprel_lo12:sym]
ldr d22, [x21, :tprel_lo12_nc:sym]
// CHECK: ldr x24, [x23, :tprel_lo12:sym]
// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym
ldr q24, [x23, :tprel_lo12:sym]
ldr q22, [x21, :tprel_lo12_nc:sym]
// CHECK: ldr q24, [x23, :tprel_lo12:sym]
// CHECK: ldr q22, [x21, :tprel_lo12_nc:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC sym
ldr w24, [x23, :gottprel_lo12:sym]
ldr s22, [x21, :gottprel_lo12:sym]
ldr w24, [x23, :tlsdesc_lo12:sym]
ldr s22, [x21, :tlsdesc_lo12:sym]
// CHECK: ldr w24, [x23, :tlsdesc_lo12:sym]
// CHECK: ldr s22, [x21, :tlsdesc_lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym
// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym
ldr q20, [x19, #:lo12:sym]
// CHECK: ldr q20, [x19, :lo12:sym]
// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST128_ABS_LO12_NC sym
// check encoding here, since encoding test doesn't belong with TLS encoding
// tests, as it isn't a TLS relocation.
// CHECK-ENCODING: ldr q20, [x19, :lo12:sym] // encoding: [0x74,0bAAAAAA10,0b11AAAAAA,0x3d]
// CHECK-ENCODING-NEXT: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale16
// Since relocated instructions print without a '#', that syntax should
// certainly be accepted when assembling.
add x3, x5, :lo12:imm
// CHECK: add x3, x5, :lo12:imm

31
external/llvm/test/MC/AArch64/arm64-adr.s vendored
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@@ -1,31 +0,0 @@
// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s
// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
adr x0, #0
adr x0, #1
adr x0, 1f
adr x0, foo
// CHECK: adr x0, #0 // encoding: [0x00,0x00,0x00,0x10]
// CHECK: adr x0, #1 // encoding: [0x00,0x00,0x00,0x30]
// CHECK: adr x0, .Ltmp0 // encoding: [A,A,A,0x10'A']
// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_aarch64_pcrel_adr_imm21
// CHECK: adr x0, foo // encoding: [A,A,A,0x10'A']
// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_aarch64_pcrel_adr_imm21
adrp x0, #0
adrp x0, #4096
adrp x0, 1f
adrp x0, foo
// CHECK: adrp x0, #0 // encoding: [0x00,0x00,0x00,0x90]
// CHECK: adrp x0, #4096 // encoding: [0x00,0x00,0x00,0xb0]
// CHECK: adrp x0, .Ltmp0 // encoding: [A,A,A,0x90'A']
// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_aarch64_pcrel_adrp_imm21
// CHECK: adrp x0, foo // encoding: [A,A,A,0x90'A']
// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_aarch64_pcrel_adrp_imm21
adr x0, #0xffffffff
adrp x0, #0xffffffff
adrp x0, #1
// CHECK-ERRORS: error: expected label or encodable integer pc offset
// CHECK-ERRORS: error: expected label or encodable integer pc offset
// CHECK-ERRORS: error: expected label or encodable integer pc offset

2148
external/llvm/test/MC/AArch64/arm64-advsimd.s vendored
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File diff suppressed because it is too large Load Diff

836
external/llvm/test/MC/AArch64/arm64-aliases.s vendored
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File diff suppressed because it is too large Load Diff

615
external/llvm/test/MC/AArch64/arm64-arithmetic-encoding.s vendored
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File diff suppressed because it is too large Load Diff

10
external/llvm/test/MC/AArch64/arm64-arm64-fixup.s vendored
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@@ -1,10 +0,0 @@
; RUN: llvm-mc < %s -triple arm64-apple-darwin --show-encoding | FileCheck %s
foo:
adr x3, Lbar
; CHECK: adr x3, Lbar ; encoding: [0x03'A',A,A,0x10'A']
; CHECK: fixup A - offset: 0, value: Lbar, kind: fixup_aarch64_pcrel_adr_imm21
Lbar:
adrp x3, _printf@page
; CHECK: adrp x3, _printf@PAGE ; encoding: [0x03'A',A,A,0x90'A']
; CHECK: fixup A - offset: 0, value: _printf@PAGE, kind: fixup_aarch64_pcrel_adrp_imm21

18
external/llvm/test/MC/AArch64/arm64-basic-a64-instructions.s vendored
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@@ -1,18 +0,0 @@
// RUN: llvm-mc -triple arm64 -mattr=+crc -show-encoding < %s | FileCheck %s
crc32b w5, w7, w20
crc32h w28, wzr, w30
crc32w w0, w1, w2
crc32x w7, w9, x20
crc32cb w9, w5, w4
crc32ch w13, w17, w25
crc32cw wzr, w3, w5
crc32cx w18, w16, xzr
// CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a]
// CHECK: crc32h w28, wzr, w30 // encoding: [0xfc,0x47,0xde,0x1a]
// CHECK: crc32w w0, w1, w2 // encoding: [0x20,0x48,0xc2,0x1a]
// CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a]
// CHECK: crc32cb w9, w5, w4 // encoding: [0xa9,0x50,0xc4,0x1a]
// CHECK: crc32ch w13, w17, w25 // encoding: [0x2d,0x56,0xd9,0x1a]
// CHECK: crc32cw wzr, w3, w5 // encoding: [0x7f,0x58,0xc5,0x1a]
// CHECK: crc32cx w18, w16, xzr // encoding: [0x12,0x5e,0xdf,0x9a]

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