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Imported Upstream version 5.18.0.167
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external/llvm/test/CodeGen/X86/wide-integer-cmp.ll
vendored
145
external/llvm/test/CodeGen/X86/wide-integer-cmp.ll
vendored
@ -1,145 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i686-linux-gnu %s -o - | FileCheck %s
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define i32 @branch_eq(i64 %a, i64 %b) {
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; CHECK-LABEL: branch_eq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: jne .LBB0_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB0_2: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp eq i64 %a, %b
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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define i32 @branch_slt(i64 %a, i64 %b) {
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; CHECK-LABEL: branch_slt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: jge .LBB1_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB1_2: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp slt i64 %a, %b
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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define i32 @branch_ule(i64 %a, i64 %b) {
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; CHECK-LABEL: branch_ule:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: jb .LBB2_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB2_2: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp ule i64 %a, %b
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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define i32 @set_gt(i64 %a, i64 %b) {
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; CHECK-LABEL: set_gt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: setl %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp sgt i64 %a, %b
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%res = select i1 %cmp, i32 1, i32 0
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ret i32 %res
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}
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define i32 @test_wide(i128 %a, i128 %b) {
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; CHECK-LABEL: test_wide:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: .cfi_offset %esi, -8
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: jge .LBB4_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB4_2: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp slt i128 %a, %b
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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; The comparison of the low bits will be folded to a CARRY_FALSE node. Make
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; sure the code can handle that.
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define i32 @test_carry_false(i64 %a, i64 %b) {
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; CHECK-LABEL: test_carry_false:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: jge .LBB5_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB5_2: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: retl
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entry:
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%x = and i64 %a, -4294967296 ;0xffffffff00000000
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%y = and i64 %b, -4294967296
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%cmp = icmp slt i64 %x, %y
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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