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Imported Upstream version 5.18.0.167
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external/llvm/test/CodeGen/SystemZ/vec-abs-01.ll
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146
external/llvm/test/CodeGen/SystemZ/vec-abs-01.ll
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; Test v16i8 absolute.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test with slt.
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define <16 x i8> @f1(<16 x i8> %val) {
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; CHECK-LABEL: f1:
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; CHECK: vlpb %v24, %v24
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; CHECK: br %r14
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%cmp = icmp slt <16 x i8> %val, zeroinitializer
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%neg = sub <16 x i8> zeroinitializer, %val
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%ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
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ret <16 x i8> %ret
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}
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; Test with sle.
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define <16 x i8> @f2(<16 x i8> %val) {
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; CHECK-LABEL: f2:
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; CHECK: vlpb %v24, %v24
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; CHECK: br %r14
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%cmp = icmp sle <16 x i8> %val, zeroinitializer
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%neg = sub <16 x i8> zeroinitializer, %val
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%ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
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ret <16 x i8> %ret
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}
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; Test with sgt.
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define <16 x i8> @f3(<16 x i8> %val) {
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; CHECK-LABEL: f3:
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; CHECK: vlpb %v24, %v24
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; CHECK: br %r14
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%cmp = icmp sgt <16 x i8> %val, zeroinitializer
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%neg = sub <16 x i8> zeroinitializer, %val
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%ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
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ret <16 x i8> %ret
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}
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; Test with sge.
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define <16 x i8> @f4(<16 x i8> %val) {
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; CHECK-LABEL: f4:
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; CHECK: vlpb %v24, %v24
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; CHECK: br %r14
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%cmp = icmp sge <16 x i8> %val, zeroinitializer
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%neg = sub <16 x i8> zeroinitializer, %val
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%ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
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ret <16 x i8> %ret
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}
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; Test that negative absolute uses VLPB too. There is no vector equivalent
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; of LOAD NEGATIVE.
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define <16 x i8> @f5(<16 x i8> %val) {
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; CHECK-LABEL: f5:
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; CHECK: vlpb [[REG:%v[0-9]+]], %v24
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; CHECK: vlcb %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp slt <16 x i8> %val, zeroinitializer
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%neg = sub <16 x i8> zeroinitializer, %val
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%abs = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
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%ret = sub <16 x i8> zeroinitializer, %abs
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ret <16 x i8> %ret
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}
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; Try another form of negative absolute (slt version).
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define <16 x i8> @f6(<16 x i8> %val) {
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; CHECK-LABEL: f6:
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; CHECK: vlpb [[REG:%v[0-9]+]], %v24
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; CHECK: vlcb %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp slt <16 x i8> %val, zeroinitializer
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%neg = sub <16 x i8> zeroinitializer, %val
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%ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
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ret <16 x i8> %ret
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}
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; Test with sle.
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define <16 x i8> @f7(<16 x i8> %val) {
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; CHECK-LABEL: f7:
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; CHECK: vlpb [[REG:%v[0-9]+]], %v24
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; CHECK: vlcb %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp sle <16 x i8> %val, zeroinitializer
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%neg = sub <16 x i8> zeroinitializer, %val
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%ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
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ret <16 x i8> %ret
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}
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; Test with sgt.
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define <16 x i8> @f8(<16 x i8> %val) {
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; CHECK-LABEL: f8:
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; CHECK: vlpb [[REG:%v[0-9]+]], %v24
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; CHECK: vlcb %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp sgt <16 x i8> %val, zeroinitializer
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%neg = sub <16 x i8> zeroinitializer, %val
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%ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
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ret <16 x i8> %ret
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}
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; Test with sge.
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define <16 x i8> @f9(<16 x i8> %val) {
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; CHECK-LABEL: f9:
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; CHECK: vlpb [[REG:%v[0-9]+]], %v24
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; CHECK: vlcb %v24, [[REG]]
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; CHECK: br %r14
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%cmp = icmp sge <16 x i8> %val, zeroinitializer
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%neg = sub <16 x i8> zeroinitializer, %val
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%ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
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ret <16 x i8> %ret
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}
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; Test with an SRA-based boolean vector.
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define <16 x i8> @f10(<16 x i8> %val) {
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; CHECK-LABEL: f10:
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; CHECK: vlpb %v24, %v24
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; CHECK: br %r14
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%shr = ashr <16 x i8> %val,
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<i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
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i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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%neg = sub <16 x i8> zeroinitializer, %val
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%and1 = and <16 x i8> %shr, %neg
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%not = xor <16 x i8> %shr,
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<i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%and2 = and <16 x i8> %not, %val
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%ret = or <16 x i8> %and1, %and2
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ret <16 x i8> %ret
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}
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; ...and again in reverse
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define <16 x i8> @f11(<16 x i8> %val) {
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; CHECK-LABEL: f11:
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; CHECK: vlpb [[REG:%v[0-9]+]], %v24
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; CHECK: vlcb %v24, [[REG]]
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; CHECK: br %r14
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%shr = ashr <16 x i8> %val,
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<i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
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i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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%and1 = and <16 x i8> %shr, %val
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%not = xor <16 x i8> %shr,
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<i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%neg = sub <16 x i8> zeroinitializer, %val
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%and2 = and <16 x i8> %not, %neg
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%ret = or <16 x i8> %and1, %and2
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ret <16 x i8> %ret
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}
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