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Imported Upstream version 5.18.0.167
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external/llvm/test/CodeGen/SystemZ/trap-03.ll
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157
external/llvm/test/CodeGen/SystemZ/trap-03.ll
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@ -1,157 +0,0 @@
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; Test load-and-trap instructions (LAT/LGAT)
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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declare void @llvm.trap()
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; Check LAT with no displacement.
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define i32 @f1(i32 *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: lat %r2, 0(%r2)
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; CHECK: br %r14
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entry:
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%val = load i32, i32 *%ptr
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 %val
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}
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; Check the high end of the LAT range.
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define i32 @f2(i32 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: lat %r2, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%val = load i32, i32 *%ptr
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 %val
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f3(i32 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r2, 524288
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; CHECK: lat %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%val = load i32, i32 *%ptr
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 %val
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}
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; Check that LAT allows an index.
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define i32 @f4(i64 %src, i64 %index) {
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; CHECK-LABEL: f4:
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; CHECK: lat %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%val = load i32, i32 *%ptr
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 %val
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}
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; Check LGAT with no displacement.
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define i64 @f5(i64 *%ptr) {
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; CHECK-LABEL: f5:
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; CHECK: lgat %r2, 0(%r2)
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; CHECK: br %r14
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entry:
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%val = load i64, i64 *%ptr
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %val
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}
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; Check the high end of the LGAT range.
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define i64 @f6(i64 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: lgat %r2, 524280(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 65535
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%val = load i64, i64 *%ptr
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %val
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f7(i64 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: agfi %r2, 524288
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; CHECK: lgat %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 65536
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%val = load i64, i64 *%ptr
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %val
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}
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; Check that LGAT allows an index.
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define i64 @f8(i64 %src, i64 %index) {
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; CHECK-LABEL: f8:
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; CHECK: lgat %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i64 *
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%val = load i64, i64 *%ptr
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %val
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}
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