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Imported Upstream version 5.18.0.167
Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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278
external/llvm/test/CodeGen/SystemZ/int-conv-13.ll
vendored
278
external/llvm/test/CodeGen/SystemZ/int-conv-13.ll
vendored
@ -1,278 +0,0 @@
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; Test load and zero rightmost byte.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Check LZRF with no displacement.
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define i32 @f1(i32 *%src) {
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; CHECK-LABEL: f1:
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; CHECK: lzrf %r2, 0(%r2)
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; CHECK: br %r14
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%val = load i32, i32 *%src
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%and = and i32 %val, 4294967040
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ret i32 %and
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}
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; Check the high end of the LZRF range.
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define i32 @f2(i32 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: lzrf %r2, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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ret i32 %and
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f3(i32 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r2, 524288
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; CHECK: lzrf %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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ret i32 %and
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}
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; Check the high end of the negative LZRF range.
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define i32 @f4(i32 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: lzrf %r2, -4(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -1
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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ret i32 %and
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}
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; Check the low end of the LZRF range.
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define i32 @f5(i32 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: lzrf %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131072
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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ret i32 %and
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f6(i32 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r2, -524292
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; CHECK: lzrf %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131073
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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ret i32 %and
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}
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; Check that LZRF allows an index.
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define i32 @f7(i64 %src, i64 %index) {
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; CHECK-LABEL: f7:
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; CHECK: lzrf %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%val = load i32 , i32 *%ptr
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%and = and i32 %val, 4294967040
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ret i32 %and
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}
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; Check LZRG with no displacement.
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define i64 @f8(i64 *%src) {
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; CHECK-LABEL: f8:
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; CHECK: lzrg %r2, 0(%r2)
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; CHECK: br %r14
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%val = load i64, i64 *%src
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%and = and i64 %val, 18446744073709551360
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ret i64 %and
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}
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; Check the high end of the LZRG range.
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define i64 @f9(i64 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: lzrg %r2, 524280(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 65535
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%val = load i64, i64 *%ptr
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%and = and i64 %val, 18446744073709551360
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ret i64 %and
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f10(i64 *%src) {
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; CHECK-LABEL: f10:
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; CHECK: agfi %r2, 524288
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; CHECK: lzrg %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 65536
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%val = load i64, i64 *%ptr
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%and = and i64 %val, 18446744073709551360
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ret i64 %and
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}
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; Check the high end of the negative LZRG range.
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define i64 @f11(i64 *%src) {
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; CHECK-LABEL: f11:
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; CHECK: lzrg %r2, -8(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 -1
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%val = load i64, i64 *%ptr
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%and = and i64 %val, 18446744073709551360
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ret i64 %and
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}
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; Check the low end of the LZRG range.
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define i64 @f12(i64 *%src) {
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; CHECK-LABEL: f12:
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; CHECK: lzrg %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 -65536
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%val = load i64, i64 *%ptr
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%and = and i64 %val, 18446744073709551360
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ret i64 %and
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f13(i64 *%src) {
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; CHECK-LABEL: f13:
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; CHECK: agfi %r2, -524296
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; CHECK: lzrg %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 -65537
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%val = load i64, i64 *%ptr
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%and = and i64 %val, 18446744073709551360
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ret i64 %and
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}
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; Check that LZRG allows an index.
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define i64 @f14(i64 %src, i64 %index) {
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; CHECK-LABEL: f14:
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; CHECK: lzrg %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i64 *
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%val = load i64 , i64 *%ptr
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%and = and i64 %val, 18446744073709551360
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ret i64 %and
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}
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; Check LLZRGF with no displacement.
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define i64 @f15(i32 *%src) {
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; CHECK-LABEL: f15:
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; CHECK: llzrgf %r2, 0(%r2)
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; CHECK: br %r14
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%val = load i32, i32 *%src
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%ext = zext i32 %val to i64
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%and = and i64 %ext, 18446744073709551360
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ret i64 %and
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}
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; ... and the other way around.
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define i64 @f16(i32 *%src) {
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; CHECK-LABEL: f16:
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; CHECK: llzrgf %r2, 0(%r2)
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; CHECK: br %r14
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%val = load i32, i32 *%src
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%and = and i32 %val, 4294967040
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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; Check the high end of the LLZRGF range.
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define i64 @f17(i32 *%src) {
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; CHECK-LABEL: f17:
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; CHECK: llzrgf %r2, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f18(i32 *%src) {
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; CHECK-LABEL: f18:
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; CHECK: agfi %r2, 524288
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; CHECK: llzrgf %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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; Check the high end of the negative LLZRGF range.
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define i64 @f19(i32 *%src) {
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; CHECK-LABEL: f19:
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; CHECK: llzrgf %r2, -4(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -1
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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; Check the low end of the LLZRGF range.
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define i64 @f20(i32 *%src) {
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; CHECK-LABEL: f20:
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; CHECK: llzrgf %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131072
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f21(i32 *%src) {
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; CHECK-LABEL: f21:
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; CHECK: agfi %r2, -524292
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; CHECK: llzrgf %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131073
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%val = load i32, i32 *%ptr
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%and = and i32 %val, 4294967040
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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; Check that LLZRGF allows an index.
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define i64 @f22(i64 %src, i64 %index) {
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; CHECK-LABEL: f22:
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; CHECK: llzrgf %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%val = load i32 , i32 *%ptr
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%and = and i32 %val, 4294967040
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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; Check that we still get a RISBGN if the source is in a register.
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define i64 @f23(i32 %src) {
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; CHECK-LABEL: f23:
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; CHECK: risbgn %r2, %r2, 32, 183, 0
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; CHECK: br %r14
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%and = and i32 %src, 4294967040
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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