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Imported Upstream version 5.18.0.167
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external/llvm/test/CodeGen/SystemZ/cond-store-02.ll
vendored
380
external/llvm/test/CodeGen/SystemZ/cond-store-02.ll
vendored
@ -1,380 +0,0 @@
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; Test 16-bit conditional stores that are presented as selects. The volatile
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; tests require z10, which use a branch instead of a LOCR.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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declare void @foo(i16 *)
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; Test the simple case, with the loaded value first.
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define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %alt, i16 %orig
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store i16 %res, i16 *%ptr
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ret void
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}
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; Test cases where the value is explicitly sign-extended to 32 bits, with the
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; loaded value first.
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define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%ext = sext i16 %orig to i32
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%res = select i1 %cond, i32 %ext, i32 %alt
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%trunc = trunc i32 %res to i16
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store i16 %trunc, i16 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%ext = sext i16 %orig to i32
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%res = select i1 %cond, i32 %alt, i32 %ext
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%trunc = trunc i32 %res to i16
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store i16 %trunc, i16 *%ptr
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ret void
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}
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; Test cases where the value is explicitly zero-extended to 32 bits, with the
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; loaded value first.
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define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%ext = zext i16 %orig to i32
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%res = select i1 %cond, i32 %ext, i32 %alt
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%trunc = trunc i32 %res to i16
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store i16 %trunc, i16 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%ext = zext i16 %orig to i32
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%res = select i1 %cond, i32 %alt, i32 %ext
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%trunc = trunc i32 %res to i16
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store i16 %trunc, i16 *%ptr
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ret void
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}
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; Test cases where the value is explicitly sign-extended to 64 bits, with the
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; loaded value first.
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define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%ext = sext i16 %orig to i64
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%res = select i1 %cond, i64 %ext, i64 %alt
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%trunc = trunc i64 %res to i16
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store i16 %trunc, i16 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%ext = sext i16 %orig to i64
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%res = select i1 %cond, i64 %alt, i64 %ext
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%trunc = trunc i64 %res to i16
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store i16 %trunc, i16 *%ptr
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ret void
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}
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; Test cases where the value is explicitly zero-extended to 64 bits, with the
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; loaded value first.
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define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f9:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%ext = zext i16 %orig to i64
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%res = select i1 %cond, i64 %ext, i64 %alt
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%trunc = trunc i64 %res to i16
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store i16 %trunc, i16 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f10:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%ext = zext i16 %orig to i64
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%res = select i1 %cond, i64 %alt, i64 %ext
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%trunc = trunc i64 %res to i16
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store i16 %trunc, i16 *%ptr
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ret void
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}
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; Check the high end of the aligned STH range.
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define void @f11(i16 *%base, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f11:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sth %r3, 4094(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%base, i64 2047
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; Check the next halfword up, which should use STHY instead of STH.
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define void @f12(i16 *%base, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f12:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sthy %r3, 4096(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%base, i64 2048
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; Check the high end of the aligned STHY range.
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define void @f13(i16 *%base, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f13:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sthy %r3, 524286(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%base, i64 262143
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; Check the next halfword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f14(i16 *%base, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f14:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, 524288
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%base, i64 262144
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; Check the low end of the STHY range.
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define void @f15(i16 *%base, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f15:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sthy %r3, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%base, i64 -262144
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; Check the next halfword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f16(i16 *%base, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f16:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, -524290
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%base, i64 -262145
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; Check that STHY allows an index.
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define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f17:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: sthy %r4, 4096(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i16 *
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; Check that volatile loads are not matched.
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define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f18:
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; CHECK: lh {{%r[0-5]}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: sth {{%r[0-5]}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load volatile i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; ...likewise stores. In this case we should have a conditional load into %r3.
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define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
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; CHECK-LABEL: f19:
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK: lh %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store volatile i16 %res, i16 *%ptr
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ret void
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}
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; Check that atomic loads are not matched. The transformation is OK for
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; the "unordered" case tested here, but since we don't try to handle atomic
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; operations at all in this context, it seems better to assert that than
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; to restrict the test to a stronger ordering.
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define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
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; FIXME: should use a normal load instead of CS.
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; CHECK-LABEL: f20:
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; CHECK: lh {{%r[0-9]+}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: sth {{%r[0-9]+}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load atomic i16 , i16 *%ptr unordered, align 2
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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ret void
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}
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; ...likewise stores.
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define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
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; FIXME: should use a normal store instead of CS.
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; CHECK-LABEL: f21:
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK: lh %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: sth %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store atomic i16 %res, i16 *%ptr unordered, align 2
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ret void
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}
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; Try a frame index base.
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define void @f22(i16 %alt, i32 %limit) {
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; CHECK-LABEL: f22:
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; CHECK: brasl %r14, foo@PLT
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; CHECK-NOT: %r15
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r15
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; CHECK: sth {{%r[0-9]+}}, {{[0-9]+}}(%r15)
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; CHECK: [[LABEL]]:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%ptr = alloca i16
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call void @foo(i16 *%ptr)
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%cond = icmp ult i32 %limit, 420
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%orig = load i16 , i16 *%ptr
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%res = select i1 %cond, i16 %orig, i16 %alt
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store i16 %res, i16 *%ptr
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call void @foo(i16 *%ptr)
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ret void
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}
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