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Imported Upstream version 5.18.0.167
Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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@ -1,18 +0,0 @@
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; RUN: llc -mtriple=s390x-linux-gnu -mcpu=zEC12 < %s | FileCheck %s
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;
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; Check that DAGCombiner doesn't crash in SystemZ combineTruncateExtract()
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; when handling EXTRACT_VECTOR_ELT without vector support.
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define void @autogen_SD21598(<2 x i8> %Arg) {
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; CHECK: stc %r3, 0(%r1)
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; CHECK: j .LBB0_1
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entry:
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br label %loop
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loop: ; preds = %CF249, %CF247
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%Shuff = shufflevector <2 x i8> undef, <2 x i8> %Arg, <2 x i32> <i32 3, i32 1>
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%E = extractelement <2 x i8> %Shuff, i32 0
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store i8 %E, i8* undef
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br label %loop
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}
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@ -1,26 +0,0 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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;
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; Check that DAGCombiner does not crash after producing an illegal
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; BUILD_VECTOR node.
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define void @pr32422() {
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; CHECK: cdbr %f0, %f0
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; CHECK: jo .LBB0_1
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BB:
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%I = insertelement <8 x i8> zeroinitializer, i8 -95, i32 3
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%I8 = insertelement <8 x i8> zeroinitializer, i8 -119, i32 2
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%FC = uitofp <8 x i8> %I8 to <8 x float>
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%Cmp18 = fcmp uno <8 x float> zeroinitializer, %FC
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%I22 = insertelement <8 x i1> %Cmp18, i1 true, i32 5
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br label %CF
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CF: ; preds = %CF, %BB
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%Cmp40 = fcmp uno double 0xC663C682E9619F00, undef
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br i1 %Cmp40, label %CF, label %CF353
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CF353: ; preds = %CF
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%E195 = extractelement <8 x i1> %I22, i32 4
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ret void
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}
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@ -1,143 +0,0 @@
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; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
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;
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; Check that the second load of @g_2 is not incorrectly eliminated by
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; DAGCombiner. It is needed since the preceding store is aliasing.
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; %.b1.i = load i1, i1* @g_2, align 4
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; ...
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; %g_717.sink.i = select i1 %cmp.i, i1* @g_717, i1* @g_2
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; store i1 true, i1* %g_717.sink.i, align 4
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; %.b = load i1, i1* @g_2, align 4
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; CHECK: # %bb.6: # %crc32_gentab.exit
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; CHECK: larl %r2, g_2
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; CHECK-NEXT: llc %r3, 0(%r2)
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; CHECK-NOT: %r2
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; CHECK: llc %r1, 0(%r2)
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@g_2 = external hidden unnamed_addr global i1, align 4
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@.str.1 = external hidden unnamed_addr constant [4 x i8], align 2
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@g_717 = external hidden unnamed_addr global i1, align 4
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@.str.2 = external hidden unnamed_addr constant [6 x i8], align 2
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@crc32_context = external hidden unnamed_addr global i32, align 4
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@crc32_tab = external hidden unnamed_addr global [256 x i32], align 4
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@g_5 = external hidden unnamed_addr global i32, align 4
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@.str.4 = external hidden unnamed_addr constant [15 x i8], align 2
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; Function Attrs: nounwind
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define signext i32 @main(i32 signext %argc, i8** nocapture readonly %argv) local_unnamed_addr #0 {
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entry:
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%cmp = icmp eq i32 %argc, 2
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br i1 %cmp, label %cond.true, label %vector.ph
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cond.true: ; preds = %entry
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%arrayidx = getelementptr inbounds i8*, i8** %argv, i64 1
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%0 = load i8*, i8** %arrayidx, align 8, !tbaa !2
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%1 = load i8, i8* %0, align 1, !tbaa !6
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%conv4 = zext i8 %1 to i32
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%sub = sub nsw i32 49, %conv4
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%cmp8 = icmp eq i32 %sub, 0
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br i1 %cmp8, label %if.then, label %if.end35
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if.then: ; preds = %cond.true
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%arrayidx11 = getelementptr inbounds i8, i8* %0, i64 1
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%2 = load i8, i8* %arrayidx11, align 1, !tbaa !6
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%conv12 = zext i8 %2 to i32
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%sub13 = sub nsw i32 0, %conv12
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br label %if.end35
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if.end35: ; preds = %if.then, %cond.true
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%__result.0 = phi i32 [ %sub13, %if.then ], [ %sub, %cond.true ]
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%phitmp = icmp eq i32 %__result.0, 0
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%spec.select = zext i1 %phitmp to i32
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br label %vector.ph
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vector.ph: ; preds = %if.end35, %entry
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%print_hash_value.0 = phi i32 [ 0, %entry ], [ %spec.select, %if.end35 ]
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%vec.ind22 = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next23, %vector.body ]
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%3 = and <4 x i32> %vec.ind22, <i32 1, i32 1, i32 1, i32 1>
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%4 = icmp eq <4 x i32> %3, zeroinitializer
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%5 = lshr <4 x i32> %vec.ind22, <i32 1, i32 1, i32 1, i32 1>
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%6 = xor <4 x i32> %5, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%7 = select <4 x i1> %4, <4 x i32> %5, <4 x i32> %6
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%8 = and <4 x i32> %7, <i32 1, i32 1, i32 1, i32 1>
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%9 = icmp eq <4 x i32> %8, zeroinitializer
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%10 = lshr <4 x i32> %7, <i32 1, i32 1, i32 1, i32 1>
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%11 = xor <4 x i32> %10, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%12 = select <4 x i1> %9, <4 x i32> %10, <4 x i32> %11
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%13 = and <4 x i32> %12, <i32 1, i32 1, i32 1, i32 1>
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%14 = icmp eq <4 x i32> %13, zeroinitializer
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%15 = lshr <4 x i32> %12, <i32 1, i32 1, i32 1, i32 1>
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%16 = xor <4 x i32> %15, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%17 = select <4 x i1> %14, <4 x i32> %15, <4 x i32> %16
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%18 = and <4 x i32> %17, <i32 1, i32 1, i32 1, i32 1>
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%19 = icmp eq <4 x i32> %18, zeroinitializer
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%20 = lshr <4 x i32> %17, <i32 1, i32 1, i32 1, i32 1>
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%21 = xor <4 x i32> %20, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%22 = select <4 x i1> %19, <4 x i32> %20, <4 x i32> %21
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%23 = and <4 x i32> %22, <i32 1, i32 1, i32 1, i32 1>
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%24 = icmp eq <4 x i32> %23, zeroinitializer
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%25 = lshr <4 x i32> %22, <i32 1, i32 1, i32 1, i32 1>
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%26 = xor <4 x i32> %25, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%27 = select <4 x i1> %24, <4 x i32> %25, <4 x i32> %26
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%28 = and <4 x i32> %27, <i32 1, i32 1, i32 1, i32 1>
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%29 = icmp eq <4 x i32> %28, zeroinitializer
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%30 = lshr <4 x i32> %27, <i32 1, i32 1, i32 1, i32 1>
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%31 = xor <4 x i32> %30, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%32 = select <4 x i1> %29, <4 x i32> %30, <4 x i32> %31
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%33 = and <4 x i32> %32, <i32 1, i32 1, i32 1, i32 1>
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%34 = icmp eq <4 x i32> %33, zeroinitializer
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%35 = lshr <4 x i32> %32, <i32 1, i32 1, i32 1, i32 1>
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%36 = xor <4 x i32> %35, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%37 = select <4 x i1> %34, <4 x i32> %35, <4 x i32> %36
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%38 = and <4 x i32> %37, <i32 1, i32 1, i32 1, i32 1>
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%39 = icmp eq <4 x i32> %38, zeroinitializer
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%40 = lshr <4 x i32> %37, <i32 1, i32 1, i32 1, i32 1>
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%41 = xor <4 x i32> %40, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%42 = select <4 x i1> %39, <4 x i32> %40, <4 x i32> %41
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%43 = getelementptr inbounds [256 x i32], [256 x i32]* @crc32_tab, i64 0, i64 %index
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%44 = bitcast i32* %43 to <4 x i32>*
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store <4 x i32> %42, <4 x i32>* %44, align 4, !tbaa !7
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%index.next = add i64 %index, 4
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%vec.ind.next23 = add <4 x i32> %vec.ind22, <i32 4, i32 4, i32 4, i32 4>
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%45 = icmp eq i64 %index.next, 256
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br i1 %45, label %crc32_gentab.exit, label %vector.body
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crc32_gentab.exit: ; preds = %vector.body
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%46 = load i32, i32* @g_5, align 4, !tbaa !7
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%.b1.i = load i1, i1* @g_2, align 4
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%47 = select i1 %.b1.i, i32 1, i32 2
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%and.i21 = and i32 %47, %46
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store i32 %and.i21, i32* @g_5, align 4, !tbaa !7
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%cmp.i = icmp eq i32 %and.i21, 1
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%g_717.sink.i = select i1 %cmp.i, i1* @g_717, i1* @g_2
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store i1 true, i1* %g_717.sink.i, align 4
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%.b = load i1, i1* @g_2, align 4
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%conv44 = select i1 %.b, i64 1, i64 2
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tail call fastcc void @transparent_crc(i64 %conv44, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.1, i64 0, i64 0), i32 signext %print_hash_value.0)
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%.b20 = load i1, i1* @g_717, align 4
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%conv45 = select i1 %.b20, i64 2, i64 0
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tail call fastcc void @transparent_crc(i64 %conv45, i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.2, i64 0, i64 0), i32 signext %print_hash_value.0)
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%48 = load i32, i32* @crc32_context, align 4, !tbaa !7
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%49 = xor i32 %48, -1
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%call.i = tail call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @.str.4, i64 0, i64 0), i32 zeroext %49) #2
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ret i32 0
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}
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; Function Attrs: nounwind
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declare hidden fastcc void @transparent_crc(i64, i8*, i32 signext) unnamed_addr #0
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; Function Attrs: nounwind
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declare signext i32 @printf(i8* nocapture readonly, ...) local_unnamed_addr #1
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!2 = !{!3, !3, i64 0}
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!3 = !{!"any pointer", !4, i64 0}
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!4 = !{!"omnipotent char", !5, i64 0}
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!5 = !{!"Simple C/C++ TBAA"}
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!6 = !{!4, !4, i64 0}
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!7 = !{!8, !8, i64 0}
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!8 = !{!"int", !4, i64 0}
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@ -1,108 +0,0 @@
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# Test normal conditional branches in cases where the sheer number of
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# instructions causes some branches to be out of range.
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# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
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# Construct:
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#
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# before0:
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# conditional branch to after0
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# ...
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# beforeN:
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# conditional branch to after0
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# main:
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# 0xffd8 bytes, from MVIY instructions
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# conditional branch to main
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# after0:
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# ...
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# conditional branch to main
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# afterN:
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#
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# Each conditional branch sequence occupies 8 bytes if it uses a short branch
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# and 10 if it uses a long one. The ones before "main:" have to take the branch
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# length into account -- which is 4 bytes for short branches -- so the final
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# (0x28 - 4) / 8 == 4 blocks can use short branches. The ones after "main:"
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# do not, so the first 0x28 / 8 == 5 can use short branches. However,
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# the conservative algorithm we use makes one branch unnecessarily long
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# on each side.
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#
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# CHECK: c %r4, 0(%r3)
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# CHECK: jge [[LABEL:\.L[^ ]*]]
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# CHECK: c %r4, 4(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 8(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 12(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 16(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 20(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 24(%r3)
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# CHECK: j{{g?}}e [[LABEL]]
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# CHECK: c %r4, 28(%r3)
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# CHECK: je [[LABEL]]
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# CHECK: c %r4, 32(%r3)
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# CHECK: je [[LABEL]]
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# CHECK: c %r4, 36(%r3)
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# CHECK: je [[LABEL]]
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# ...main goes here...
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# CHECK: c %r4, 100(%r3)
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# CHECK: je [[LABEL:\.L[^ ]*]]
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# CHECK: c %r4, 104(%r3)
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# CHECK: je [[LABEL]]
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# CHECK: c %r4, 108(%r3)
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# CHECK: je [[LABEL]]
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# CHECK: c %r4, 112(%r3)
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# CHECK: je [[LABEL]]
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# CHECK: c %r4, 116(%r3)
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# CHECK: j{{g?}}e [[LABEL]]
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# CHECK: c %r4, 120(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 124(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 128(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 132(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 136(%r3)
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# CHECK: jge [[LABEL]]
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branch_blocks = 10
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main_size = 0xffd8
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print '@global = global i32 0'
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print 'define void @f1(i8 *%base, i32 *%stop, i32 %limit) {'
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print 'entry:'
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print ' br label %before0'
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print ''
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for i in xrange(branch_blocks):
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next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
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print 'before%d:' % i
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print ' %%bstop%d = getelementptr i32, i32 *%%stop, i64 %d' % (i, i)
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print ' %%bcur%d = load i32 , i32 *%%bstop%d' % (i, i)
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print ' %%btest%d = icmp eq i32 %%limit, %%bcur%d' % (i, i)
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print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
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print ''
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print '%s:' % next
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a, b = 1, 1
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for i in xrange(0, main_size, 6):
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a, b = b, a + b
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offset = 4096 + b % 500000
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value = a % 256
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print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
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print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
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for i in xrange(branch_blocks):
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print ' %%astop%d = getelementptr i32, i32 *%%stop, i64 %d' % (i, i + 25)
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print ' %%acur%d = load i32 , i32 *%%astop%d' % (i, i)
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print ' %%atest%d = icmp eq i32 %%limit, %%acur%d' % (i, i)
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print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
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print ''
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print 'after%d:' % i
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print ' %dummy = load volatile i32, i32 *@global'
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print ' ret void'
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print '}'
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@ -1,82 +0,0 @@
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# Test normal conditional branches in cases where block alignments cause
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# some branches to be out of range.
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# RUN: python %s | llc -mtriple=s390x-linux-gnu -align-all-blocks=8 | FileCheck %s
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# Construct:
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#
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# b0:
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# conditional branch to end
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# ...
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# b<N>:
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# conditional branch to end
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# b<N+1>:
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# conditional branch to b0
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# ...
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# b<2*N>:
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# conditional branch to b0
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# end:
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#
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# with N == 256 + 4. The -align-all-blocks=8 option ensures that all blocks
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# are 256 bytes in size. The first 4 blocks and the last 4 blocks are then
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# out of range.
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#
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# CHECK: c %r4, 0(%r3)
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# CHECK: jge [[LABEL:\.L[^ ]*]]
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# CHECK: c %r4, 4(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 8(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 12(%r3)
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# CHECK: jge [[LABEL]]
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# CHECK: c %r4, 16(%r3)
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# CHECK: je [[LABEL]]
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# CHECK: c %r4, 20(%r3)
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# CHECK: je [[LABEL]]
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# CHECK: c %r4, 24(%r3)
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# CHECK: je [[LABEL]]
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# CHECK: c %r4, 28(%r3)
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# CHECK: je [[LABEL]]
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# ...lots of other blocks...
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# CHECK: c %r4, 1004(%r3)
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# CHECK: je [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: c %r4, 1008(%r3)
|
||||
# CHECK: je [[LABEL]]
|
||||
# CHECK: c %r4, 1012(%r3)
|
||||
# CHECK: je [[LABEL]]
|
||||
# CHECK: c %r4, 1016(%r3)
|
||||
# CHECK: je [[LABEL]]
|
||||
# CHECK: c %r4, 1020(%r3)
|
||||
# CHECK: je [[LABEL]]
|
||||
# CHECK: c %r4, 1024(%r3)
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: c %r4, 1028(%r3)
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: c %r4, 1032(%r3)
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: c %r4, 1036(%r3)
|
||||
# CHECK: jge [[LABEL]]
|
||||
|
||||
blocks = 256 + 4
|
||||
|
||||
print 'define void @f1(i8 *%base, i32 *%stop, i32 %limit) {'
|
||||
print 'entry:'
|
||||
print ' br label %b0'
|
||||
print ''
|
||||
|
||||
a, b = 1, 1
|
||||
for i in xrange(blocks):
|
||||
a, b = b, a + b
|
||||
value = a % 256
|
||||
next = 'b%d' % (i + 1) if i + 1 < blocks else 'end'
|
||||
other = 'end' if 2 * i < blocks else 'b0'
|
||||
print 'b%d:' % i
|
||||
print ' store volatile i8 %d, i8 *%%base' % value
|
||||
print ' %%astop%d = getelementptr i32, i32 *%%stop, i64 %d' % (i, i)
|
||||
print ' %%acur%d = load i32 , i32 *%%astop%d' % (i, i)
|
||||
print ' %%atest%d = icmp eq i32 %%limit, %%acur%d' % (i, i)
|
||||
print ' br i1 %%atest%d, label %%%s, label %%%s' % (i, other, next)
|
||||
|
||||
print ''
|
||||
print '%s:' % next
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,110 +0,0 @@
|
||||
# Test 32-bit COMPARE AND BRANCH in cases where the sheer number of
|
||||
# instructions causes some branches to be out of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# before0:
|
||||
# conditional branch to after0
|
||||
# ...
|
||||
# beforeN:
|
||||
# conditional branch to after0
|
||||
# main:
|
||||
# 0xffcc bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# conditional branch to main
|
||||
# afterN:
|
||||
#
|
||||
# Each conditional branch sequence occupies 12 bytes if it uses a short
|
||||
# branch and 14 if it uses a long one. The ones before "main:" have to
|
||||
# take the branch length into account, which is 6 for short branches,
|
||||
# so the final (0x34 - 6) / 12 == 3 blocks can use short branches.
|
||||
# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks
|
||||
# can use short branches.
|
||||
#
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 1(%r3)
|
||||
# CHECK: cr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 2(%r3)
|
||||
# CHECK: cr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 3(%r3)
|
||||
# CHECK: cr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 4(%r3)
|
||||
# CHECK: cr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 5(%r3)
|
||||
# CHECK: crje %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 6(%r3)
|
||||
# CHECK: crje %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 7(%r3)
|
||||
# CHECK: crje %r4, [[REG]], [[LABEL]]
|
||||
# ...main goes here...
|
||||
# CHECK: lb [[REG:%r[0-5]]], 25(%r3)
|
||||
# CHECK: crje %r4, [[REG]], [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 26(%r3)
|
||||
# CHECK: crje %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 27(%r3)
|
||||
# CHECK: crje %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 28(%r3)
|
||||
# CHECK: crje %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 29(%r3)
|
||||
# CHECK: cr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 30(%r3)
|
||||
# CHECK: cr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 31(%r3)
|
||||
# CHECK: cr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 32(%r3)
|
||||
# CHECK: cr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffcc
|
||||
|
||||
print '@global = global i32 0'
|
||||
|
||||
print 'define void @f1(i8 *%base, i8 *%stop, i32 %limit) {'
|
||||
print 'entry:'
|
||||
print ' br label %before0'
|
||||
print ''
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
|
||||
print 'before%d:' % i
|
||||
print ' %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i)
|
||||
print ' %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i)
|
||||
print ' %%bext%d = sext i8 %%bcur%d to i32' % (i, i)
|
||||
print ' %%btest%d = icmp eq i32 %%limit, %%bext%d' % (i, i)
|
||||
print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
|
||||
print ''
|
||||
|
||||
print '%s:' % next
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25)
|
||||
print ' %%acur%d = load i8 , i8 *%%astop%d' % (i, i)
|
||||
print ' %%aext%d = sext i8 %%acur%d to i32' % (i, i)
|
||||
print ' %%atest%d = icmp eq i32 %%limit, %%aext%d' % (i, i)
|
||||
print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' %dummy = load volatile i32, i32 *@global'
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,114 +0,0 @@
|
||||
# Test 64-bit COMPARE AND BRANCH in cases where the sheer number of
|
||||
# instructions causes some branches to be out of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# before0:
|
||||
# conditional branch to after0
|
||||
# ...
|
||||
# beforeN:
|
||||
# conditional branch to after0
|
||||
# main:
|
||||
# 0xffcc bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# conditional branch to main
|
||||
# afterN:
|
||||
#
|
||||
# Each conditional branch sequence occupies 12 bytes if it uses a short
|
||||
# branch and 16 if it uses a long one. The ones before "main:" have to
|
||||
# take the branch length into account, which is 6 for short branches,
|
||||
# so the final (0x34 - 6) / 12 == 3 blocks can use short branches.
|
||||
# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks
|
||||
# can use short branches. The conservative algorithm we use makes
|
||||
# one of the forward branches unnecessarily long, as noted in the
|
||||
# check output below.
|
||||
#
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 1(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 2(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 3(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 4(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# ...as mentioned above, the next one could be a CGRJE instead...
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 5(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 6(%r3)
|
||||
# CHECK: cgrje %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 7(%r3)
|
||||
# CHECK: cgrje %r4, [[REG]], [[LABEL]]
|
||||
# ...main goes here...
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 25(%r3)
|
||||
# CHECK: cgrje %r4, [[REG]], [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 26(%r3)
|
||||
# CHECK: cgrje %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 27(%r3)
|
||||
# CHECK: cgrje %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 28(%r3)
|
||||
# CHECK: cgrje %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 29(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 30(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 31(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 32(%r3)
|
||||
# CHECK: cgr %r4, [[REG]]
|
||||
# CHECK: jge [[LABEL]]
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffcc
|
||||
|
||||
print '@global = global i32 0'
|
||||
|
||||
print 'define void @f1(i8 *%base, i8 *%stop, i64 %limit) {'
|
||||
print 'entry:'
|
||||
print ' br label %before0'
|
||||
print ''
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
|
||||
print 'before%d:' % i
|
||||
print ' %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i)
|
||||
print ' %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i)
|
||||
print ' %%bext%d = sext i8 %%bcur%d to i64' % (i, i)
|
||||
print ' %%btest%d = icmp eq i64 %%limit, %%bext%d' % (i, i)
|
||||
print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
|
||||
print ''
|
||||
|
||||
print '%s:' % next
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25)
|
||||
print ' %%acur%d = load i8 , i8 *%%astop%d' % (i, i)
|
||||
print ' %%aext%d = sext i8 %%acur%d to i64' % (i, i)
|
||||
print ' %%atest%d = icmp eq i64 %%limit, %%aext%d' % (i, i)
|
||||
print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' %dummy = load volatile i32, i32 *@global'
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,112 +0,0 @@
|
||||
# Test 32-bit COMPARE IMMEDIATE AND BRANCH in cases where the sheer number of
|
||||
# instructions causes some branches to be out of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# before0:
|
||||
# conditional branch to after0
|
||||
# ...
|
||||
# beforeN:
|
||||
# conditional branch to after0
|
||||
# main:
|
||||
# 0xffcc bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# conditional branch to main
|
||||
# afterN:
|
||||
#
|
||||
# Each conditional branch sequence occupies 12 bytes if it uses a short
|
||||
# branch and 16 if it uses a long one. The ones before "main:" have to
|
||||
# take the branch length into account, which is 6 for short branches,
|
||||
# so the final (0x34 - 6) / 12 == 3 blocks can use short branches.
|
||||
# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks
|
||||
# can use short branches. The conservative algorithm we use makes
|
||||
# one of the forward branches unnecessarily long, as noted in the
|
||||
# check output below.
|
||||
#
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 50
|
||||
# CHECK: jgl [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 51
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 52
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 53
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 54
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# ...as mentioned above, the next one could be a CIJL instead...
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 55
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cijl [[REG]], 56, [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cijl [[REG]], 57, [[LABEL]]
|
||||
# ...main goes here...
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cijl [[REG]], 100, [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cijl [[REG]], 101, [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cijl [[REG]], 102, [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cijl [[REG]], 103, [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 104
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 105
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 106
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: chi [[REG]], 107
|
||||
# CHECK: jgl [[LABEL]]
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffcc
|
||||
|
||||
print '@global = global i32 0'
|
||||
|
||||
print 'define void @f1(i8 *%base, i8 *%stop) {'
|
||||
print 'entry:'
|
||||
print ' br label %before0'
|
||||
print ''
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
|
||||
print 'before%d:' % i
|
||||
print ' %%bcur%d = load i8 , i8 *%%stop' % i
|
||||
print ' %%bext%d = sext i8 %%bcur%d to i32' % (i, i)
|
||||
print ' %%btest%d = icmp slt i32 %%bext%d, %d' % (i, i, i + 50)
|
||||
print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
|
||||
print ''
|
||||
|
||||
print '%s:' % next
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%acur%d = load i8 , i8 *%%stop' % i
|
||||
print ' %%aext%d = sext i8 %%acur%d to i32' % (i, i)
|
||||
print ' %%atest%d = icmp slt i32 %%aext%d, %d' % (i, i, i + 100)
|
||||
print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' %dummy = load volatile i32, i32 *@global'
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,112 +0,0 @@
|
||||
# Test 64-bit COMPARE IMMEDIATE AND BRANCH in cases where the sheer number of
|
||||
# instructions causes some branches to be out of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# before0:
|
||||
# conditional branch to after0
|
||||
# ...
|
||||
# beforeN:
|
||||
# conditional branch to after0
|
||||
# main:
|
||||
# 0xffcc bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# conditional branch to main
|
||||
# afterN:
|
||||
#
|
||||
# Each conditional branch sequence occupies 12 bytes if it uses a short
|
||||
# branch and 16 if it uses a long one. The ones before "main:" have to
|
||||
# take the branch length into account, which is 6 for short branches,
|
||||
# so the final (0x34 - 6) / 12 == 3 blocks can use short branches.
|
||||
# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks
|
||||
# can use short branches. The conservative algorithm we use makes
|
||||
# one of the forward branches unnecessarily long, as noted in the
|
||||
# check output below.
|
||||
#
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 50
|
||||
# CHECK: jgl [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 51
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 52
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 53
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 54
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# ...as mentioned above, the next one could be a CGIJL instead...
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 55
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cgijl [[REG]], 56, [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cgijl [[REG]], 57, [[LABEL]]
|
||||
# ...main goes here...
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cgijl [[REG]], 100, [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cgijl [[REG]], 101, [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cgijl [[REG]], 102, [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cgijl [[REG]], 103, [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 104
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 105
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 106
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: cghi [[REG]], 107
|
||||
# CHECK: jgl [[LABEL]]
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffcc
|
||||
|
||||
print '@global = global i32 0'
|
||||
|
||||
print 'define void @f1(i8 *%base, i8 *%stop) {'
|
||||
print 'entry:'
|
||||
print ' br label %before0'
|
||||
print ''
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
|
||||
print 'before%d:' % i
|
||||
print ' %%bcur%d = load i8 , i8 *%%stop' % i
|
||||
print ' %%bext%d = sext i8 %%bcur%d to i64' % (i, i)
|
||||
print ' %%btest%d = icmp slt i64 %%bext%d, %d' % (i, i, i + 50)
|
||||
print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
|
||||
print ''
|
||||
|
||||
print '%s:' % next
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%acur%d = load i8 , i8 *%%stop' % i
|
||||
print ' %%aext%d = sext i8 %%acur%d to i64' % (i, i)
|
||||
print ' %%atest%d = icmp slt i64 %%aext%d, %d' % (i, i, i + 100)
|
||||
print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' %dummy = load volatile i32, i32 *@global'
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,68 +0,0 @@
|
||||
# Test 32-bit BRANCH RELATIVE ON COUNT in cases where some branches are out
|
||||
# of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# loopN:
|
||||
# load of countN
|
||||
# ...
|
||||
# loop0:
|
||||
# 0xffd8 bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# decrement of countN
|
||||
# conditional branch to loopN
|
||||
# afterN:
|
||||
#
|
||||
# Each load occupies 4 bytes. Each decrement and branch occupies 4
|
||||
# bytes if BRCT can be used, otherwise it occupies 10 bytes (AHI + BRCL).
|
||||
# This means that loop 6 contains 5 * 4 + 0xffd8 + 5 * 4 == 0x10000 bytes
|
||||
# and is therefore (just) in range. Loop 7 is out of range.
|
||||
#
|
||||
# CHECK: brct {{%r[0-9]+}}
|
||||
# CHECK: brct {{%r[0-9]+}}
|
||||
# CHECK: brct {{%r[0-9]+}}
|
||||
# CHECK: brct {{%r[0-9]+}}
|
||||
# CHECK: brct {{%r[0-9]+}}
|
||||
# CHECK: brct {{%r[0-9]+}}
|
||||
# CHECK: ahi {{%r[0-9]+}}, -1
|
||||
# CHECK: jglh
|
||||
# CHECK: ahi {{%r[0-9]+}}, -1
|
||||
# CHECK: jglh
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffd8
|
||||
|
||||
print 'define void @f1(i8 *%base, i32 *%counts) {'
|
||||
print 'entry:'
|
||||
|
||||
for i in xrange(branch_blocks - 1, -1, -1):
|
||||
print ' %%countptr%d = getelementptr i32, i32 *%%counts, i64 %d' % (i, i)
|
||||
print ' %%initcount%d = load i32 , i32 *%%countptr%d' % (i, i)
|
||||
print ' br label %%loop%d' % i
|
||||
|
||||
print 'loop%d:' % i
|
||||
block1 = 'entry' if i == branch_blocks - 1 else 'loop%d' % (i + 1)
|
||||
block2 = 'loop0' if i == 0 else 'after%d' % (i - 1)
|
||||
print (' %%count%d = phi i32 [ %%initcount%d, %%%s ],'
|
||||
' [ %%nextcount%d, %%%s ]' % (i, i, block1, i, block2))
|
||||
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%nextcount%d = add i32 %%count%d, -1' % (i, i)
|
||||
print ' %%test%d = icmp ne i32 %%nextcount%d, 0' % (i, i)
|
||||
print ' br i1 %%test%d, label %%loop%d, label %%after%d' % (i, i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,69 +0,0 @@
|
||||
# Test 64-bit BRANCH RELATIVE ON COUNT in cases where some branches are out
|
||||
# of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# loopN:
|
||||
# load of countN
|
||||
# ...
|
||||
# loop0:
|
||||
# 0xffd8 bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# decrement of countN
|
||||
# conditional branch to loopN
|
||||
# afterN:
|
||||
#
|
||||
# Each load occupies 6 bytes. Each decrement and branch occupies 4
|
||||
# bytes if BRCTG can be used, otherwise it occupies 10 bytes (AGHI + BRCL).
|
||||
# This means that loop 5 contains 4 * 6 + 0xffd8 + 4 * 4 == 0x10000 bytes
|
||||
# and is therefore (just) in range. Loop 6 is out of range.
|
||||
#
|
||||
# CHECK: brctg {{%r[0-9]+}}
|
||||
# CHECK: brctg {{%r[0-9]+}}
|
||||
# CHECK: brctg {{%r[0-9]+}}
|
||||
# CHECK: brctg {{%r[0-9]+}}
|
||||
# CHECK: brctg {{%r[0-9]+}}
|
||||
# CHECK: aghi {{%r[0-9]+}}, -1
|
||||
# CHECK: jglh
|
||||
# CHECK: aghi {{%r[0-9]+}}, -1
|
||||
# CHECK: jglh
|
||||
# CHECK: aghi {{%r[0-9]+}}, -1
|
||||
# CHECK: jglh
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffd8
|
||||
|
||||
print 'define void @f1(i8 *%base, i64 *%counts) {'
|
||||
print 'entry:'
|
||||
|
||||
for i in xrange(branch_blocks - 1, -1, -1):
|
||||
print ' %%countptr%d = getelementptr i64, i64 *%%counts, i64 %d' % (i, i)
|
||||
print ' %%initcount%d = load i64 , i64 *%%countptr%d' % (i, i)
|
||||
print ' br label %%loop%d' % i
|
||||
|
||||
print 'loop%d:' % i
|
||||
block1 = 'entry' if i == branch_blocks - 1 else 'loop%d' % (i + 1)
|
||||
block2 = 'loop0' if i == 0 else 'after%d' % (i - 1)
|
||||
print (' %%count%d = phi i64 [ %%initcount%d, %%%s ],'
|
||||
' [ %%nextcount%d, %%%s ]' % (i, i, block1, i, block2))
|
||||
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%nextcount%d = add i64 %%count%d, -1' % (i, i)
|
||||
print ' %%test%d = icmp ne i64 %%nextcount%d, 0' % (i, i)
|
||||
print ' br i1 %%test%d, label %%loop%d, label %%after%d' % (i, i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,110 +0,0 @@
|
||||
# Test 32-bit COMPARE LOGICAL AND BRANCH in cases where the sheer number of
|
||||
# instructions causes some branches to be out of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# before0:
|
||||
# conditional branch to after0
|
||||
# ...
|
||||
# beforeN:
|
||||
# conditional branch to after0
|
||||
# main:
|
||||
# 0xffcc bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# conditional branch to main
|
||||
# afterN:
|
||||
#
|
||||
# Each conditional branch sequence occupies 12 bytes if it uses a short
|
||||
# branch and 14 if it uses a long one. The ones before "main:" have to
|
||||
# take the branch length into account, which is 6 for short branches,
|
||||
# so the final (0x34 - 6) / 12 == 3 blocks can use short branches.
|
||||
# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks
|
||||
# can use short branches.
|
||||
#
|
||||
# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: clr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 1(%r3)
|
||||
# CHECK: clr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 2(%r3)
|
||||
# CHECK: clr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 3(%r3)
|
||||
# CHECK: clr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 4(%r3)
|
||||
# CHECK: clr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 5(%r3)
|
||||
# CHECK: clrjl %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 6(%r3)
|
||||
# CHECK: clrjl %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 7(%r3)
|
||||
# CHECK: clrjl %r4, [[REG]], [[LABEL]]
|
||||
# ...main goes here...
|
||||
# CHECK: lb [[REG:%r[0-5]]], 25(%r3)
|
||||
# CHECK: clrjl %r4, [[REG]], [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 26(%r3)
|
||||
# CHECK: clrjl %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 27(%r3)
|
||||
# CHECK: clrjl %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 28(%r3)
|
||||
# CHECK: clrjl %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 29(%r3)
|
||||
# CHECK: clr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 30(%r3)
|
||||
# CHECK: clr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 31(%r3)
|
||||
# CHECK: clr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lb [[REG:%r[0-5]]], 32(%r3)
|
||||
# CHECK: clr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffcc
|
||||
|
||||
print '@global = global i32 0'
|
||||
|
||||
print 'define void @f1(i8 *%base, i8 *%stop, i32 %limit) {'
|
||||
print 'entry:'
|
||||
print ' br label %before0'
|
||||
print ''
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
|
||||
print 'before%d:' % i
|
||||
print ' %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i)
|
||||
print ' %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i)
|
||||
print ' %%bext%d = sext i8 %%bcur%d to i32' % (i, i)
|
||||
print ' %%btest%d = icmp ult i32 %%limit, %%bext%d' % (i, i)
|
||||
print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
|
||||
print ''
|
||||
|
||||
print '%s:' % next
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25)
|
||||
print ' %%acur%d = load i8 , i8 *%%astop%d' % (i, i)
|
||||
print ' %%aext%d = sext i8 %%acur%d to i32' % (i, i)
|
||||
print ' %%atest%d = icmp ult i32 %%limit, %%aext%d' % (i, i)
|
||||
print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' %dummy = load volatile i32, i32 *@global'
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,114 +0,0 @@
|
||||
# Test 64-bit COMPARE LOGICAL AND BRANCH in cases where the sheer number of
|
||||
# instructions causes some branches to be out of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# before0:
|
||||
# conditional branch to after0
|
||||
# ...
|
||||
# beforeN:
|
||||
# conditional branch to after0
|
||||
# main:
|
||||
# 0xffcc bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# conditional branch to main
|
||||
# afterN:
|
||||
#
|
||||
# Each conditional branch sequence occupies 12 bytes if it uses a short
|
||||
# branch and 16 if it uses a long one. The ones before "main:" have to
|
||||
# take the branch length into account, which is 6 for short branches,
|
||||
# so the final (0x34 - 6) / 12 == 3 blocks can use short branches.
|
||||
# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks
|
||||
# can use short branches. The conservative algorithm we use makes
|
||||
# one of the forward branches unnecessarily long, as noted in the
|
||||
# check output below.
|
||||
#
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 1(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 2(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 3(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 4(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# ...as mentioned above, the next one could be a CLGRJL instead...
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 5(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 6(%r3)
|
||||
# CHECK: clgrjl %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 7(%r3)
|
||||
# CHECK: clgrjl %r4, [[REG]], [[LABEL]]
|
||||
# ...main goes here...
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 25(%r3)
|
||||
# CHECK: clgrjl %r4, [[REG]], [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 26(%r3)
|
||||
# CHECK: clgrjl %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 27(%r3)
|
||||
# CHECK: clgrjl %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 28(%r3)
|
||||
# CHECK: clgrjl %r4, [[REG]], [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 29(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 30(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 31(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lgb [[REG:%r[0-5]]], 32(%r3)
|
||||
# CHECK: clgr %r4, [[REG]]
|
||||
# CHECK: jgl [[LABEL]]
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffcc
|
||||
|
||||
print '@global = global i32 0'
|
||||
|
||||
print 'define void @f1(i8 *%base, i8 *%stop, i64 %limit) {'
|
||||
print 'entry:'
|
||||
print ' br label %before0'
|
||||
print ''
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
|
||||
print 'before%d:' % i
|
||||
print ' %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i)
|
||||
print ' %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i)
|
||||
print ' %%bext%d = sext i8 %%bcur%d to i64' % (i, i)
|
||||
print ' %%btest%d = icmp ult i64 %%limit, %%bext%d' % (i, i)
|
||||
print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
|
||||
print ''
|
||||
|
||||
print '%s:' % next
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25)
|
||||
print ' %%acur%d = load i8 , i8 *%%astop%d' % (i, i)
|
||||
print ' %%aext%d = sext i8 %%acur%d to i64' % (i, i)
|
||||
print ' %%atest%d = icmp ult i64 %%limit, %%aext%d' % (i, i)
|
||||
print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' %dummy = load volatile i32, i32 *@global'
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,130 +0,0 @@
|
||||
# Test 32-bit COMPARE LOGICAL IMMEDIATE AND BRANCH in cases where the sheer
|
||||
# number of instructions causes some branches to be out of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# before0:
|
||||
# conditional branch to after0
|
||||
# ...
|
||||
# beforeN:
|
||||
# conditional branch to after0
|
||||
# main:
|
||||
# 0xffc6 bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# conditional branch to main
|
||||
# afterN:
|
||||
#
|
||||
# Each conditional branch sequence occupies 14 bytes if it uses a short
|
||||
# branch and 20 if it uses a long one. The ones before "main:" have to
|
||||
# take the branch length into account, which is 6 for short branches,
|
||||
# so the final (0x3a - 6) / 14 == 3 blocks can use short branches.
|
||||
# The ones after "main:" do not, so the first 0x3a / 14 == 4 blocks
|
||||
# can use short branches. The conservative algorithm we use makes
|
||||
# one of the forward branches unnecessarily long, as noted in the
|
||||
# check output below.
|
||||
#
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 50
|
||||
# CHECK: jgl [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 51
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 52
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 53
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 54
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# ...as mentioned above, the next one could be a CLIJL instead...
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 55
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clijl [[REG]], 56, [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clijl [[REG]], 57, [[LABEL]]
|
||||
# ...main goes here...
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clijl [[REG]], 100, [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clijl [[REG]], 101, [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clijl [[REG]], 102, [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clijl [[REG]], 103, [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 104
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 105
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 106
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: l [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: s [[REG]], 0(%r4)
|
||||
# CHECK: clfi [[REG]], 107
|
||||
# CHECK: jgl [[LABEL]]
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffc6
|
||||
|
||||
print '@global = global i32 0'
|
||||
|
||||
print 'define void @f1(i8 *%base, i32 *%stopa, i32 *%stopb) {'
|
||||
print 'entry:'
|
||||
print ' br label %before0'
|
||||
print ''
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
|
||||
print 'before%d:' % i
|
||||
print ' %%bcur%da = load i32 , i32 *%%stopa' % i
|
||||
print ' %%bcur%db = load i32 , i32 *%%stopb' % i
|
||||
print ' %%bsub%d = sub i32 %%bcur%da, %%bcur%db' % (i, i, i)
|
||||
print ' %%btest%d = icmp ult i32 %%bsub%d, %d' % (i, i, i + 50)
|
||||
print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
|
||||
print ''
|
||||
|
||||
print '%s:' % next
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%acur%da = load i32 , i32 *%%stopa' % i
|
||||
print ' %%acur%db = load i32 , i32 *%%stopb' % i
|
||||
print ' %%asub%d = sub i32 %%acur%da, %%acur%db' % (i, i, i)
|
||||
print ' %%atest%d = icmp ult i32 %%asub%d, %d' % (i, i, i + 100)
|
||||
print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' %dummy = load volatile i32, i32 *@global'
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,130 +0,0 @@
|
||||
# Test 64-bit COMPARE LOGICAL IMMEDIATE AND BRANCH in cases where the sheer
|
||||
# number of instructions causes some branches to be out of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# Construct:
|
||||
#
|
||||
# before0:
|
||||
# conditional branch to after0
|
||||
# ...
|
||||
# beforeN:
|
||||
# conditional branch to after0
|
||||
# main:
|
||||
# 0xffb4 bytes, from MVIY instructions
|
||||
# conditional branch to main
|
||||
# after0:
|
||||
# ...
|
||||
# conditional branch to main
|
||||
# afterN:
|
||||
#
|
||||
# Each conditional branch sequence occupies 18 bytes if it uses a short
|
||||
# branch and 24 if it uses a long one. The ones before "main:" have to
|
||||
# take the branch length into account, which is 6 for short branches,
|
||||
# so the final (0x4c - 6) / 18 == 3 blocks can use short branches.
|
||||
# The ones after "main:" do not, so the first 0x4c / 18 == 4 blocks
|
||||
# can use short branches. The conservative algorithm we use makes
|
||||
# one of the forward branches unnecessarily long, as noted in the
|
||||
# check output below.
|
||||
#
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 50
|
||||
# CHECK: jgl [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 51
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 52
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 53
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 54
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# ...as mentioned above, the next one could be a CLGIJL instead...
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 55
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgijl [[REG]], 56, [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgijl [[REG]], 57, [[LABEL]]
|
||||
# ...main goes here...
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgijl [[REG]], 100, [[LABEL:\.L[^ ]*]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgijl [[REG]], 101, [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgijl [[REG]], 102, [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgijl [[REG]], 103, [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 104
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 105
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 106
|
||||
# CHECK: jgl [[LABEL]]
|
||||
# CHECK: lg [[REG:%r[0-5]]], 0(%r3)
|
||||
# CHECK: sg [[REG]], 0(%r4)
|
||||
# CHECK: clgfi [[REG]], 107
|
||||
# CHECK: jgl [[LABEL]]
|
||||
|
||||
branch_blocks = 8
|
||||
main_size = 0xffb4
|
||||
|
||||
print '@global = global i32 0'
|
||||
|
||||
print 'define void @f1(i8 *%base, i64 *%stopa, i64 *%stopb) {'
|
||||
print 'entry:'
|
||||
print ' br label %before0'
|
||||
print ''
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
|
||||
print 'before%d:' % i
|
||||
print ' %%bcur%da = load i64 , i64 *%%stopa' % i
|
||||
print ' %%bcur%db = load i64 , i64 *%%stopb' % i
|
||||
print ' %%bsub%d = sub i64 %%bcur%da, %%bcur%db' % (i, i, i)
|
||||
print ' %%btest%d = icmp ult i64 %%bsub%d, %d' % (i, i, i + 50)
|
||||
print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
|
||||
print ''
|
||||
|
||||
print '%s:' % next
|
||||
a, b = 1, 1
|
||||
for i in xrange(0, main_size, 6):
|
||||
a, b = b, a + b
|
||||
offset = 4096 + b % 500000
|
||||
value = a % 256
|
||||
print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
|
||||
print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
|
||||
|
||||
for i in xrange(branch_blocks):
|
||||
print ' %%acur%da = load i64 , i64 *%%stopa' % i
|
||||
print ' %%acur%db = load i64 , i64 *%%stopb' % i
|
||||
print ' %%asub%d = sub i64 %%acur%da, %%acur%db' % (i, i, i)
|
||||
print ' %%atest%d = icmp ult i64 %%asub%d, %d' % (i, i, i + 100)
|
||||
print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
|
||||
print ''
|
||||
print 'after%d:' % i
|
||||
|
||||
print ' %dummy = load volatile i32, i32 *@global'
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,9 +0,0 @@
|
||||
config.suffixes = ['.py']
|
||||
|
||||
# These tests take on the order of seconds to run, so skip them unless
|
||||
# we're running long tests.
|
||||
if 'long_tests' not in config.available_features:
|
||||
config.unsupported = True
|
||||
|
||||
if not 'SystemZ' in config.root.targets:
|
||||
config.unsupported = True
|
||||
@ -1,40 +0,0 @@
|
||||
# Test cases where MVC is used for spill slots that end up being out of range.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# There are 8 usable call-saved GPRs, two of which are needed for the base
|
||||
# registers. The first 160 bytes of the frame are needed for the ABI
|
||||
# call frame, and a further 8 bytes are needed for the emergency spill slot.
|
||||
# That means we will have at least one out-of-range slot if:
|
||||
#
|
||||
# count == (4096 - 168) / 8 + 6 + 1 == 498
|
||||
#
|
||||
# Add in some extra room and check both %r15+4096 (the first out-of-range slot)
|
||||
# and %r15+4104.
|
||||
#
|
||||
# CHECK: f1:
|
||||
# CHECK: lay [[REG:%r[0-5]]], 4096(%r15)
|
||||
# CHECK: mvc 0(8,[[REG]]), {{[0-9]+}}({{%r[0-9]+}})
|
||||
# CHECK: brasl %r14, foo@PLT
|
||||
# CHECK: lay [[REG:%r[0-5]]], 4096(%r15)
|
||||
# CHECK: mvc {{[0-9]+}}(8,{{%r[0-9]+}}), 8([[REG]])
|
||||
# CHECK: br %r14
|
||||
count = 500
|
||||
|
||||
print 'declare void @foo()'
|
||||
print ''
|
||||
print 'define void @f1(i64 *%base0, i64 *%base1) {'
|
||||
|
||||
for i in range(count):
|
||||
print ' %%ptr%d = getelementptr i64, i64 *%%base%d, i64 %d' % (i, i % 2, i / 2)
|
||||
print ' %%val%d = load i64 , i64 *%%ptr%d' % (i, i)
|
||||
print ''
|
||||
|
||||
print ' call void @foo()'
|
||||
print ''
|
||||
|
||||
for i in range(count):
|
||||
print ' store i64 %%val%d, i64 *%%ptr%d' % (i, i)
|
||||
|
||||
print ''
|
||||
print ' ret void'
|
||||
print '}'
|
||||
@ -1,73 +0,0 @@
|
||||
# Test cases where we spill from one frame index to another, both of which
|
||||
# are out of range of MVC, and both of which need emergency spill slots.
|
||||
# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
# CHECK: f1:
|
||||
# CHECK: %fallthru
|
||||
# CHECK-DAG: stg [[REG1:%r[0-9]+]], 8168(%r15)
|
||||
# CHECK-DAG: stg [[REG2:%r[0-9]+]], 8176(%r15)
|
||||
# CHECK-DAG: lay [[REG3:%r[0-9]+]], 8192(%r15)
|
||||
# CHECK-DAG: lay [[REG4:%r[0-9]+]], 4096(%r15)
|
||||
# CHECK: mvc 0(8,[[REG3]]), 4088([[REG4]])
|
||||
# CHECK-DAG: lg [[REG1]], 8168(%r15)
|
||||
# CHECK-DAG: lg [[REG2]], 8176(%r15)
|
||||
# CHECK: %skip
|
||||
# CHECK: br %r14
|
||||
|
||||
# Arrange for %foo's spill slot to be at 8184(%r15) and the alloca area to be at
|
||||
# 8192(%r15). The two emergency spill slots live below that, so this requires
|
||||
# the first 8168 bytes to be used for the call. 160 of these bytes are
|
||||
# allocated for the ABI frame. There are also 5 argument registers, one of
|
||||
# which is used as a base pointer.
|
||||
args = (8168 - 160) / 8 + (5 - 1)
|
||||
|
||||
print 'declare i64 *@foo(i64 *%s)' % (', i64' * args)
|
||||
print 'declare void @bar(i64 *)'
|
||||
print ''
|
||||
print 'define i64 @f1(i64 %foo) {'
|
||||
print 'entry:'
|
||||
|
||||
# Make the allocation big, so that it goes at the top of the frame.
|
||||
print ' %array = alloca [1000 x i64]'
|
||||
print ' %area = getelementptr [1000 x i64], [1000 x i64] *%array, i64 0, i64 0'
|
||||
print ' %%base = call i64 *@foo(i64 *%%area%s)' % (', i64 0' * args)
|
||||
print ''
|
||||
|
||||
# Make sure all GPRs are used. One is needed for the stack pointer and
|
||||
# another for %base, so we need 14 live values.
|
||||
count = 14
|
||||
for i in range(count):
|
||||
print ' %%ptr%d = getelementptr i64, i64 *%%base, i64 %d' % (i, i / 2)
|
||||
print ' %%val%d = load volatile i64 , i64 *%%ptr%d' % (i, i)
|
||||
print ''
|
||||
|
||||
# Encourage the register allocator to give preference to these %vals
|
||||
# by using them several times.
|
||||
for j in range(4):
|
||||
for i in range(count):
|
||||
print ' store volatile i64 %%val%d, i64 *%%ptr%d' % (i, i)
|
||||
print ''
|
||||
|
||||
# Copy the incoming argument, which we expect to be spilled, to the frame
|
||||
# index for the alloca area. Also throw in a volatile store, so that this
|
||||
# block cannot be reordered with the surrounding code.
|
||||
print ' %cond = icmp eq i64 %val0, %val1'
|
||||
print ' br i1 %cond, label %skip, label %fallthru'
|
||||
print ''
|
||||
print 'fallthru:'
|
||||
print ' store i64 %foo, i64 *%area'
|
||||
print ' store volatile i64 %val0, i64 *%ptr0'
|
||||
print ' br label %skip'
|
||||
print ''
|
||||
print 'skip:'
|
||||
|
||||
# Use each %val a few more times to emphasise the point, and to make sure
|
||||
# that they are live across the store of %foo.
|
||||
for j in range(4):
|
||||
for i in range(count):
|
||||
print ' store volatile i64 %%val%d, i64 *%%ptr%d' % (i, i)
|
||||
print ''
|
||||
|
||||
print ' call void @bar(i64 *%area)'
|
||||
print ' ret i64 0'
|
||||
print '}'
|
||||
@ -1,267 +0,0 @@
|
||||
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -run-pass=regallocbasic %s -o - | FileCheck %s
|
||||
# This test used to assert in RABasic. The problem was when we split live-ranges,
|
||||
# we were not updating the LiveRegMatrix properly and the interference calculation
|
||||
# wouldn't match what the assignment thought it could do.
|
||||
# In other words, this test case needs to trigger live-range splitting to exercise
|
||||
# the problem.
|
||||
#
|
||||
# PR33057
|
||||
--- |
|
||||
target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
|
||||
target triple = "s390x--linux-gnu"
|
||||
|
||||
define void @autogen_SD21418() #0 {
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-cpu"="z13" }
|
||||
|
||||
...
|
||||
|
||||
# CHECK: name: autogen_SD21418
|
||||
# Check that at least one live-range has been split
|
||||
# CHECK: id: 114, class
|
||||
---
|
||||
name: autogen_SD21418
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vr128bit }
|
||||
- { id: 1, class: vr128bit }
|
||||
- { id: 2, class: vr128bit }
|
||||
- { id: 3, class: vr64bit }
|
||||
- { id: 4, class: gr64bit }
|
||||
- { id: 5, class: vr128bit }
|
||||
- { id: 6, class: grx32bit }
|
||||
- { id: 7, class: vr128bit }
|
||||
- { id: 8, class: vr128bit }
|
||||
- { id: 9, class: gr32bit }
|
||||
- { id: 10, class: gr64bit }
|
||||
- { id: 11, class: vr128bit }
|
||||
- { id: 12, class: fp64bit }
|
||||
- { id: 13, class: vr64bit }
|
||||
- { id: 14, class: vr64bit }
|
||||
- { id: 15, class: gr64bit }
|
||||
- { id: 16, class: gr128bit }
|
||||
- { id: 17, class: gr64bit }
|
||||
- { id: 18, class: gr32bit }
|
||||
- { id: 19, class: gr32bit }
|
||||
- { id: 20, class: gr128bit }
|
||||
- { id: 21, class: gr32bit }
|
||||
- { id: 22, class: gr64bit }
|
||||
- { id: 23, class: gr32bit }
|
||||
- { id: 24, class: gr32bit }
|
||||
- { id: 25, class: gr128bit }
|
||||
- { id: 26, class: grx32bit }
|
||||
- { id: 27, class: gr64bit }
|
||||
- { id: 28, class: gr64bit }
|
||||
- { id: 29, class: vr128bit }
|
||||
- { id: 30, class: vr128bit }
|
||||
- { id: 31, class: gr64bit }
|
||||
- { id: 32, class: gr32bit }
|
||||
- { id: 33, class: gr32bit }
|
||||
- { id: 34, class: gr128bit }
|
||||
- { id: 35, class: gr32bit }
|
||||
- { id: 36, class: vr128bit }
|
||||
- { id: 37, class: gr64bit }
|
||||
- { id: 38, class: gr32bit }
|
||||
- { id: 39, class: gr32bit }
|
||||
- { id: 40, class: gr128bit }
|
||||
- { id: 41, class: gr32bit }
|
||||
- { id: 42, class: addr64bit }
|
||||
- { id: 43, class: grx32bit }
|
||||
- { id: 44, class: addr64bit }
|
||||
- { id: 45, class: vr64bit }
|
||||
- { id: 46, class: vr64bit }
|
||||
- { id: 47, class: gr32bit }
|
||||
- { id: 48, class: gr32bit }
|
||||
- { id: 49, class: grx32bit }
|
||||
- { id: 50, class: vr64bit }
|
||||
- { id: 51, class: gr64bit }
|
||||
- { id: 52, class: grx32bit }
|
||||
- { id: 53, class: gr32bit }
|
||||
- { id: 54, class: gr64bit }
|
||||
- { id: 55, class: grx32bit }
|
||||
- { id: 56, class: gr32bit }
|
||||
- { id: 57, class: gr128bit }
|
||||
- { id: 58, class: gr128bit }
|
||||
- { id: 59, class: gr32bit }
|
||||
- { id: 60, class: gr64bit }
|
||||
- { id: 61, class: grx32bit }
|
||||
- { id: 62, class: gr32bit }
|
||||
- { id: 63, class: gr64bit }
|
||||
- { id: 64, class: grx32bit }
|
||||
- { id: 65, class: gr32bit }
|
||||
- { id: 66, class: gr128bit }
|
||||
- { id: 67, class: gr128bit }
|
||||
- { id: 68, class: grx32bit }
|
||||
- { id: 69, class: gr64bit }
|
||||
- { id: 70, class: gr64bit }
|
||||
- { id: 71, class: vr128bit }
|
||||
- { id: 72, class: vr128bit }
|
||||
- { id: 73, class: gr64bit }
|
||||
- { id: 74, class: grx32bit }
|
||||
- { id: 75, class: gr32bit }
|
||||
- { id: 76, class: gr64bit }
|
||||
- { id: 77, class: grx32bit }
|
||||
- { id: 78, class: gr32bit }
|
||||
- { id: 79, class: gr128bit }
|
||||
- { id: 80, class: gr128bit }
|
||||
- { id: 81, class: gr32bit }
|
||||
- { id: 82, class: vr128bit }
|
||||
- { id: 83, class: gr64bit }
|
||||
- { id: 84, class: grx32bit }
|
||||
- { id: 85, class: gr32bit }
|
||||
- { id: 86, class: gr64bit }
|
||||
- { id: 87, class: grx32bit }
|
||||
- { id: 88, class: gr32bit }
|
||||
- { id: 89, class: gr128bit }
|
||||
- { id: 90, class: gr128bit }
|
||||
- { id: 91, class: gr32bit }
|
||||
- { id: 92, class: grx32bit }
|
||||
- { id: 93, class: gr64bit }
|
||||
- { id: 94, class: gr32bit }
|
||||
- { id: 95, class: gr32bit }
|
||||
- { id: 96, class: gr32bit }
|
||||
- { id: 97, class: gr64bit }
|
||||
- { id: 98, class: gr64bit }
|
||||
- { id: 99, class: grx32bit }
|
||||
- { id: 100, class: grx32bit }
|
||||
- { id: 101, class: gr128bit }
|
||||
- { id: 102, class: gr128bit }
|
||||
- { id: 103, class: gr128bit }
|
||||
- { id: 104, class: gr64bit }
|
||||
- { id: 105, class: gr128bit }
|
||||
- { id: 106, class: gr128bit }
|
||||
- { id: 107, class: gr64bit }
|
||||
- { id: 108, class: gr128bit }
|
||||
- { id: 109, class: gr128bit }
|
||||
- { id: 110, class: gr64bit }
|
||||
- { id: 111, class: gr128bit }
|
||||
- { id: 112, class: gr128bit }
|
||||
- { id: 113, class: gr64bit }
|
||||
constants:
|
||||
- id: 0
|
||||
value: double 0xD55960F86F577076
|
||||
alignment: 8
|
||||
body: |
|
||||
bb.0:
|
||||
%11 = VGBM 0
|
||||
%43 = LHIMux 0
|
||||
%44 = LARL %const.0
|
||||
%45 = VL64 %44, 0, %noreg :: (load 8 from constant-pool)
|
||||
|
||||
bb.1:
|
||||
ADJCALLSTACKDOWN 0, 0
|
||||
%12 = LZDR
|
||||
%f0d = COPY %12
|
||||
CallBRASL $fmod, killed %f0d, undef %f2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def %f0d
|
||||
ADJCALLSTACKUP 0, 0
|
||||
KILL killed %f0d
|
||||
|
||||
bb.2:
|
||||
%17 = VLGVH %11, %noreg, 0
|
||||
%19 = LHR %17.subreg_l32
|
||||
undef %20.subreg_l64 = LGHI 0
|
||||
%20 = DSGFR %20, %19
|
||||
%22 = VLGVH %11, %noreg, 3
|
||||
%24 = LHR %22.subreg_l32
|
||||
undef %25.subreg_l64 = LGHI 0
|
||||
%25 = DSGFR %25, %24
|
||||
%31 = VLGVH %11, %noreg, 1
|
||||
%33 = LHR %31.subreg_l32
|
||||
undef %34.subreg_l64 = LGHI 0
|
||||
%34 = DSGFR %34, %33
|
||||
%37 = VLGVH %11, %noreg, 2
|
||||
%39 = LHR %37.subreg_l32
|
||||
undef %40.subreg_l64 = LGHI 0
|
||||
%40 = DSGFR %40, %39
|
||||
CHIMux %43, 0, implicit-def %cc
|
||||
BRC 14, 6, %bb.2, implicit killed %cc
|
||||
J %bb.3
|
||||
|
||||
bb.3:
|
||||
WFCDB undef %46, %45, implicit-def %cc
|
||||
%48 = IPM implicit killed %cc
|
||||
%48 = AFIMux %48, 268435456, implicit-def dead %cc
|
||||
%6 = RISBMux undef %6, %48, 31, 159, 35
|
||||
WFCDB undef %50, %45, implicit-def %cc
|
||||
BRC 15, 6, %bb.1, implicit killed %cc
|
||||
J %bb.4
|
||||
|
||||
bb.4:
|
||||
%36 = VLVGP %25.subreg_l64, %25.subreg_l64
|
||||
%36 = VLVGH %36, %20.subreg_l32, %noreg, 0
|
||||
%36 = VLVGH %36, %34.subreg_l32, %noreg, 1
|
||||
dead %36 = VLVGH %36, %40.subreg_l32, %noreg, 2
|
||||
%4 = LG undef %42, 0, %noreg :: (load 8 from `i64* undef`)
|
||||
undef %57.subreg_h64 = LLILL 0
|
||||
undef %66.subreg_h64 = LLILL 0
|
||||
undef %79.subreg_h64 = LLILL 0
|
||||
undef %89.subreg_h64 = LLILL 0
|
||||
%92 = LHIMux 0
|
||||
|
||||
bb.5:
|
||||
|
||||
bb.6:
|
||||
%51 = VLGVH undef %7, %noreg, 0
|
||||
%53 = LLHRMux %51.subreg_l32
|
||||
%54 = VLGVH undef %1, %noreg, 0
|
||||
%57.subreg_l32 = LLHRMux %54.subreg_l32
|
||||
%58 = COPY %57
|
||||
%58 = DLR %58, %53
|
||||
%60 = VLGVH undef %7, %noreg, 3
|
||||
%62 = LLHRMux %60.subreg_l32
|
||||
%63 = VLGVH undef %1, %noreg, 3
|
||||
%66.subreg_l32 = LLHRMux %63.subreg_l32
|
||||
%67 = COPY %66
|
||||
%67 = DLR %67, %62
|
||||
%73 = VLGVH undef %7, %noreg, 1
|
||||
%75 = LLHRMux %73.subreg_l32
|
||||
%76 = VLGVH undef %1, %noreg, 1
|
||||
%79.subreg_l32 = LLHRMux %76.subreg_l32
|
||||
%80 = COPY %79
|
||||
%80 = DLR %80, %75
|
||||
%83 = VLGVH undef %7, %noreg, 2
|
||||
%85 = LLHRMux %83.subreg_l32
|
||||
%86 = VLGVH undef %1, %noreg, 2
|
||||
%89.subreg_l32 = LLHRMux %86.subreg_l32
|
||||
%90 = COPY %89
|
||||
%90 = DLR %90, %85
|
||||
CHIMux %92, 0, implicit-def %cc
|
||||
BRC 14, 6, %bb.7, implicit killed %cc
|
||||
J %bb.6
|
||||
|
||||
bb.7:
|
||||
CGHI undef %93, 0, implicit-def %cc
|
||||
%96 = IPM implicit killed %cc
|
||||
CGHI undef %97, 0, implicit-def %cc
|
||||
BRC 14, 6, %bb.6, implicit killed %cc
|
||||
|
||||
bb.8:
|
||||
CHIMux %6, 0, implicit-def %cc
|
||||
%10 = LLILL 41639
|
||||
dead %10 = LOCGR %10, %4, 14, 6, implicit killed %cc
|
||||
CHIMux %92, 0, implicit-def %cc
|
||||
BRC 14, 6, %bb.5, implicit killed %cc
|
||||
J %bb.9
|
||||
|
||||
bb.9:
|
||||
%82 = VLVGP %67.subreg_h64, %67.subreg_h64
|
||||
%82 = VLVGH %82, %58.subreg_hl32, %noreg, 0
|
||||
%82 = VLVGH %82, %80.subreg_hl32, %noreg, 1
|
||||
dead %82 = VLVGH %82, %90.subreg_hl32, %noreg, 2
|
||||
%96 = AFIMux %96, 1879048192, implicit-def dead %cc
|
||||
%96 = SRL %96, %noreg, 31
|
||||
dead %11 = VLVGF %11, %96, %noreg, 1
|
||||
%100 = LHIMux 0
|
||||
|
||||
bb.10:
|
||||
CHIMux %100, 0, implicit-def %cc
|
||||
BRC 14, 6, %bb.10, implicit killed %cc
|
||||
J %bb.11
|
||||
|
||||
bb.11:
|
||||
Return
|
||||
|
||||
...
|
||||
107
external/llvm/test/CodeGen/SystemZ/addr-01.ll
vendored
107
external/llvm/test/CodeGen/SystemZ/addr-01.ll
vendored
@ -1,107 +0,0 @@
|
||||
; Test selection of addresses with indices in cases where the address
|
||||
; is used once.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
; A simple index address.
|
||||
define void @f1(i64 %addr, i64 %index) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: lb %r0, 0(%r3,%r2)
|
||||
; CHECK: br %r14
|
||||
%add = add i64 %addr, %index
|
||||
%ptr = inttoptr i64 %add to i8 *
|
||||
%a = load volatile i8 , i8 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; An address with an index and a displacement (order 1).
|
||||
define void @f2(i64 %addr, i64 %index) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: lb %r0, 100(%r3,%r2)
|
||||
; CHECK: br %r14
|
||||
%add1 = add i64 %addr, %index
|
||||
%add2 = add i64 %add1, 100
|
||||
%ptr = inttoptr i64 %add2 to i8 *
|
||||
%a = load volatile i8 , i8 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; An address with an index and a displacement (order 2).
|
||||
define void @f3(i64 %addr, i64 %index) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: lb %r0, 100(%r3,%r2)
|
||||
; CHECK: br %r14
|
||||
%add1 = add i64 %addr, 100
|
||||
%add2 = add i64 %add1, %index
|
||||
%ptr = inttoptr i64 %add2 to i8 *
|
||||
%a = load volatile i8 , i8 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; An address with an index and a subtracted displacement (order 1).
|
||||
define void @f4(i64 %addr, i64 %index) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: lb %r0, -100(%r3,%r2)
|
||||
; CHECK: br %r14
|
||||
%add1 = add i64 %addr, %index
|
||||
%add2 = sub i64 %add1, 100
|
||||
%ptr = inttoptr i64 %add2 to i8 *
|
||||
%a = load volatile i8 , i8 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; An address with an index and a subtracted displacement (order 2).
|
||||
define void @f5(i64 %addr, i64 %index) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: lb %r0, -100(%r3,%r2)
|
||||
; CHECK: br %r14
|
||||
%add1 = sub i64 %addr, 100
|
||||
%add2 = add i64 %add1, %index
|
||||
%ptr = inttoptr i64 %add2 to i8 *
|
||||
%a = load volatile i8 , i8 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; An address with an index and a displacement added using OR.
|
||||
define void @f6(i64 %addr, i64 %index) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: nill %r2, 65528
|
||||
; CHECK: lb %r0, 6(%r3,%r2)
|
||||
; CHECK: br %r14
|
||||
%aligned = and i64 %addr, -8
|
||||
%or = or i64 %aligned, 6
|
||||
%add = add i64 %or, %index
|
||||
%ptr = inttoptr i64 %add to i8 *
|
||||
%a = load volatile i8 , i8 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Like f6, but without the masking. This OR doesn't count as a displacement.
|
||||
define void @f7(i64 %addr, i64 %index) {
|
||||
; CHECK-LABEL: f7:
|
||||
; CHECK: oill %r2, 6
|
||||
; CHECK: lb %r0, 0(%r3,%r2)
|
||||
; CHECK: br %r14
|
||||
%or = or i64 %addr, 6
|
||||
%add = add i64 %or, %index
|
||||
%ptr = inttoptr i64 %add to i8 *
|
||||
%a = load volatile i8 , i8 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Like f6, but with the OR applied after the index. We don't know anything
|
||||
; about the alignment of %add here.
|
||||
define void @f8(i64 %addr, i64 %index) {
|
||||
; CHECK-LABEL: f8:
|
||||
; CHECK: nill %r2, 65528
|
||||
; CHECK: agr %r2, %r3
|
||||
; CHECK: oill %r2, 6
|
||||
; CHECK: lb %r0, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%aligned = and i64 %addr, -8
|
||||
%add = add i64 %aligned, %index
|
||||
%or = or i64 %add, 6
|
||||
%ptr = inttoptr i64 %or to i8 *
|
||||
%a = load volatile i8 , i8 *%ptr
|
||||
ret void
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user