Imported Upstream version 5.18.0.167

Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a

external/llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll

@@ -1,44 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
-
-; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
-
-define i64 @addc_adde(i64 %a, i64 %b) {
-; RV32I-LABEL: addc_adde:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    add a1, a1, a3
-; RV32I-NEXT:    add a2, a0, a2
-; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    add a1, a1, a0
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = add i64 %a, %b
-  ret i64 %1
-}
-
-define i64 @subc_sube(i64 %a, i64 %b) {
-; RV32I-LABEL: subc_sube:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    sltu a3, a0, a2
-; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    sub a0, a0, a2
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = sub i64 %a, %b
-  ret i64 %1
-}

external/llvm/test/CodeGen/RISCV/alloca.ll

@@ -1,65 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-declare void @notdead(i8*)
-
-; These tests must ensure the stack pointer is restored using the frame
-; pointer
-
-define void @simple_alloca(i32 %n) nounwind {
-; RV32I-LABEL: simple_alloca:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    addi a0, a0, 15
-; RV32I-NEXT:    andi a0, a0, -16
-; RV32I-NEXT:    sub a0, sp, a0
-; RV32I-NEXT:    mv sp, a0
-; RV32I-NEXT:    lui a1, %hi(notdead)
-; RV32I-NEXT:    addi a1, a1, %lo(notdead)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    addi sp, s0, -16
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = alloca i8, i32 %n
-  call void @notdead(i8* %1)
-  ret void
-}
-
-declare i8* @llvm.stacksave()
-declare void @llvm.stackrestore(i8*)
-
-define void @scoped_alloca(i32 %n) nounwind {
-; RV32I-LABEL: scoped_alloca:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    sw s1, 4(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    mv s1, sp
-; RV32I-NEXT:    addi a0, a0, 15
-; RV32I-NEXT:    andi a0, a0, -16
-; RV32I-NEXT:    sub a0, sp, a0
-; RV32I-NEXT:    mv sp, a0
-; RV32I-NEXT:    lui a1, %hi(notdead)
-; RV32I-NEXT:    addi a1, a1, %lo(notdead)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    mv sp, s1
-; RV32I-NEXT:    addi sp, s0, -16
-; RV32I-NEXT:    lw s1, 4(sp)
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %sp = call i8* @llvm.stacksave()
-  %addr = alloca i8, i32 %n
-  call void @notdead(i8* %addr)
-  call void @llvm.stackrestore(i8* %sp)
-  ret void
-}

external/llvm/test/CodeGen/RISCV/alu32.ll

@@ -1,319 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-; These tests are each targeted at a particular RISC-V ALU instruction. Other
-; files in this folder exercise LLVM IR instructions that don't directly match a
-; RISC-V instruction
-
-; Register-immediate instructions
-
-define i32 @addi(i32 %a) nounwind {
-; RV32I-LABEL: addi:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    addi a0, a0, 1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = add i32 %a, 1
-  ret i32 %1
-}
-
-define i32 @slti(i32 %a) nounwind {
-; RV32I-LABEL: slti:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    slti a0, a0, 2
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp slt i32 %a, 2
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @sltiu(i32 %a) nounwind {
-; RV32I-LABEL: sltiu:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sltiu a0, a0, 3
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp ult i32 %a, 3
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @xori(i32 %a) nounwind {
-; RV32I-LABEL: xori:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    xori a0, a0, 4
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = xor i32 %a, 4
-  ret i32 %1
-}
-
-define i32 @ori(i32 %a) nounwind {
-; RV32I-LABEL: ori:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    ori a0, a0, 5
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = or i32 %a, 5
-  ret i32 %1
-}
-
-define i32 @andi(i32 %a) nounwind {
-; RV32I-LABEL: andi:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    andi a0, a0, 6
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = and i32 %a, 6
-  ret i32 %1
-}
-
-define i32 @slli(i32 %a) nounwind {
-; RV32I-LABEL: slli:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    slli a0, a0, 7
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = shl i32 %a, 7
-  ret i32 %1
-}
-
-define i32 @srli(i32 %a) nounwind {
-; RV32I-LABEL: srli:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    srli a0, a0, 8
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = lshr i32 %a, 8
-  ret i32 %1
-}
-
-define i32 @srai(i32 %a) nounwind {
-; RV32I-LABEL: srai:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    srai a0, a0, 9
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = ashr i32 %a, 9
-  ret i32 %1
-}
-
-; Register-register instructions
-
-define i32 @add(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: add:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = add i32 %a, %b
-  ret i32 %1
-}
-
-define i32 @sub(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sub:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = sub i32 %a, %b
-  ret i32 %1
-}
-
-define i32 @sll(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sll:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sll a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = shl i32 %a, %b
-  ret i32 %1
-}
-
-define i32 @slt(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: slt:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp slt i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @sltu(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sltu:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sltu a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp ult i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @xor(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: xor:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = xor i32 %a, %b
-  ret i32 %1
-}
-
-define i32 @srl(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: srl:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    srl a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = lshr i32 %a, %b
-  ret i32 %1
-}
-
-define i32 @sra(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sra:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sra a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = ashr i32 %a, %b
-  ret i32 %1
-}
-
-define i32 @or(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: or:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = or i32 %a, %b
-  ret i32 %1
-}
-
-define i32 @and(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: and:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = and i32 %a, %b
-  ret i32 %1
-}

external/llvm/test/CodeGen/RISCV/bare-select.ll

@@ -1,24 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
-; RV32I-LABEL: bare_select:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    bnez a0, .LBB0_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a1, a2
-; RV32I-NEXT:  .LBB0_2:
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = select i1 %a, i32 %b, i32 %c
-  ret i32 %1
-}

external/llvm/test/CodeGen/RISCV/blockaddress.ll

@@ -1,33 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-@addr = global i8* null
-
-define void @test_blockaddress() nounwind {
-; RV32I-LABEL: test_blockaddress:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(addr)
-; RV32I-NEXT:    addi a0, a0, %lo(addr)
-; RV32I-NEXT:    lui a1, %hi(.Ltmp0)
-; RV32I-NEXT:    addi a1, a1, %lo(.Ltmp0)
-; RV32I-NEXT:    sw a1, 0(a0)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    jr a0
-; RV32I-NEXT:  .Ltmp0: # Block address taken
-; RV32I-NEXT:  .LBB0_1: # %block
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
-  %val = load volatile i8*, i8** @addr
-  indirectbr i8* %val, [label %block]
-
-block:
-  ret void
-}

external/llvm/test/CodeGen/RISCV/branch.ll

@@ -1,128 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
-
-define void @foo(i32 %a, i32 *%b, i1 %c) {
-; RV32I-LABEL: foo:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    beq a3, a0, .LBB0_12
-; RV32I-NEXT:    j .LBB0_1
-; RV32I-NEXT:  .LBB0_1: # %test2
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bne a3, a0, .LBB0_12
-; RV32I-NEXT:    j .LBB0_2
-; RV32I-NEXT:  .LBB0_2: # %test3
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    blt a3, a0, .LBB0_12
-; RV32I-NEXT:    j .LBB0_3
-; RV32I-NEXT:  .LBB0_3: # %test4
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bge a3, a0, .LBB0_12
-; RV32I-NEXT:    j .LBB0_4
-; RV32I-NEXT:  .LBB0_4: # %test5
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bltu a3, a0, .LBB0_12
-; RV32I-NEXT:    j .LBB0_5
-; RV32I-NEXT:  .LBB0_5: # %test6
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bgeu a3, a0, .LBB0_12
-; RV32I-NEXT:    j .LBB0_6
-; RV32I-NEXT:  .LBB0_6: # %test7
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    blt a0, a3, .LBB0_12
-; RV32I-NEXT:    j .LBB0_7
-; RV32I-NEXT:  .LBB0_7: # %test8
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bge a0, a3, .LBB0_12
-; RV32I-NEXT:    j .LBB0_8
-; RV32I-NEXT:  .LBB0_8: # %test9
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bltu a0, a3, .LBB0_12
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_9: # %test10
-; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bgeu a0, a3, .LBB0_12
-; RV32I-NEXT:    j .LBB0_10
-; RV32I-NEXT:  .LBB0_10: # %test11
-; RV32I-NEXT:    lw a0, 0(a1)
-; RV32I-NEXT:    andi a0, a2, 1
-; RV32I-NEXT:    bnez a0, .LBB0_12
-; RV32I-NEXT:    j .LBB0_11
-; RV32I-NEXT:  .LBB0_11: # %test12
-; RV32I-NEXT:    lw a0, 0(a1)
-; RV32I-NEXT:  .LBB0_12: # %end
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-
-  %val1 = load volatile i32, i32* %b
-  %tst1 = icmp eq i32 %val1, %a
-  br i1 %tst1, label %end, label %test2
-
-test2:
-  %val2 = load volatile i32, i32* %b
-  %tst2 = icmp ne i32 %val2, %a
-  br i1 %tst2, label %end, label %test3
-
-test3:
-  %val3 = load volatile i32, i32* %b
-  %tst3 = icmp slt i32 %val3, %a
-  br i1 %tst3, label %end, label %test4
-
-test4:
-  %val4 = load volatile i32, i32* %b
-  %tst4 = icmp sge i32 %val4, %a
-  br i1 %tst4, label %end, label %test5
-
-test5:
-  %val5 = load volatile i32, i32* %b
-  %tst5 = icmp ult i32 %val5, %a
-  br i1 %tst5, label %end, label %test6
-
-test6:
-  %val6 = load volatile i32, i32* %b
-  %tst6 = icmp uge i32 %val6, %a
-  br i1 %tst6, label %end, label %test7
-
-; Check for condition codes that don't have a matching instruction
-
-test7:
-  %val7 = load volatile i32, i32* %b
-  %tst7 = icmp sgt i32 %val7, %a
-  br i1 %tst7, label %end, label %test8
-
-test8:
-  %val8 = load volatile i32, i32* %b
-  %tst8 = icmp sle i32 %val8, %a
-  br i1 %tst8, label %end, label %test9
-
-test9:
-  %val9 = load volatile i32, i32* %b
-  %tst9 = icmp ugt i32 %val9, %a
-  br i1 %tst9, label %end, label %test10
-
-test10:
-  %val10 = load volatile i32, i32* %b
-  %tst10 = icmp ule i32 %val10, %a
-  br i1 %tst10, label %end, label %test11
-
-; Check the case of a branch where the condition was generated in another
-; function
-
-test11:
-  %val11 = load volatile i32, i32* %b
-  br i1 %c, label %end, label %test12
-
-test12:
-  %val12 = load volatile i32, i32* %b
-  br label %end
-
-end:
-  ret void
-}

external/llvm/test/CodeGen/RISCV/byval.ll

@@ -1,61 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
-
-%struct.Foo = type { i32, i32, i32, i16, i8 }
-@foo = global %struct.Foo { i32 1, i32 2, i32 3, i16 4, i8 5 }, align 4
-
-define i32 @callee(%struct.Foo* byval %f) nounwind {
-; RV32I-LABEL: callee:
-; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-entry:
-  %0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0
-  %1 = load i32, i32* %0, align 4
-  ret i32 %1
-}
-
-
-define void @caller() nounwind {
-; RV32I-LABEL: caller:
-; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s0, 24(sp)
-; RV32I-NEXT:    addi s0, sp, 32
-; RV32I-NEXT:    lui a0, %hi(foo+12)
-; RV32I-NEXT:    addi a0, a0, %lo(foo+12)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -12(s0)
-; RV32I-NEXT:    lui a0, %hi(foo+8)
-; RV32I-NEXT:    addi a0, a0, %lo(foo+8)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -16(s0)
-; RV32I-NEXT:    lui a0, %hi(foo+4)
-; RV32I-NEXT:    addi a0, a0, %lo(foo+4)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -20(s0)
-; RV32I-NEXT:    lui a0, %hi(foo)
-; RV32I-NEXT:    addi a0, a0, %lo(foo)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -24(s0)
-; RV32I-NEXT:    lui a0, %hi(callee)
-; RV32I-NEXT:    addi a1, a0, %lo(callee)
-; RV32I-NEXT:    addi a0, s0, -24
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 24(sp)
-; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    ret
-entry:
-  %call = call i32 @callee(%struct.Foo* byval @foo)
-  ret void
-}

external/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll

@@ -1,497 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
-
-define zeroext i8 @uint8_arg_to_uint8_ret(i8 zeroext %a) nounwind {
-; RV32I-LABEL: uint8_arg_to_uint8_ret:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i8 %a
-}
-
-declare void @receive_uint8(i8 zeroext)
-
-define void @pass_uint8_as_uint8(i8 zeroext %a) nounwind {
-; RV32I-LABEL: pass_uint8_as_uint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(receive_uint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_uint8)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  call void @receive_uint8(i8 zeroext %a)
-  ret void
-}
-
-declare zeroext i8 @return_uint8()
-
-define zeroext i8 @ret_callresult_uint8_as_uint8() nounwind {
-; RV32I-LABEL: ret_callresult_uint8_as_uint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(return_uint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_uint8)
-; RV32I-NEXT:    jalr a0
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call zeroext i8 @return_uint8()
-  ret i8 %1
-}
-
-define signext i8 @uint8_arg_to_sint8_ret(i8 zeroext %a) nounwind {
-; RV32I-LABEL: uint8_arg_to_sint8_ret:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    srai a0, a0, 24
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i8 %a
-}
-
-declare void @receive_sint8(i8 signext)
-
-define void @pass_uint8_as_sint8(i8 zeroext %a) nounwind {
-; RV32I-LABEL: pass_uint8_as_sint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(receive_sint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_sint8)
-; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    srai a0, a0, 24
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-
-  call void @receive_sint8(i8 signext %a)
-  ret void
-}
-
-define signext i8 @ret_callresult_uint8_as_sint8() nounwind {
-; RV32I-LABEL: ret_callresult_uint8_as_sint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(return_uint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_uint8)
-; RV32I-NEXT:    jalr a0
-; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    srai a0, a0, 24
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call zeroext i8 @return_uint8()
-  ret i8 %1
-}
-
-define signext i32 @uint8_arg_to_anyint32_ret(i8 zeroext %a) nounwind {
-; RV32I-LABEL: uint8_arg_to_anyint32_ret:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = zext i8 %a to i32
-  ret i32 %1
-}
-
-declare void @receive_anyint32(i32 signext)
-
-define void @pass_uint8_as_anyint32(i8 zeroext %a) nounwind {
-; RV32I-LABEL: pass_uint8_as_anyint32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(receive_anyint32)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_anyint32)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = zext i8 %a to i32
-  call void @receive_anyint32(i32 signext %1)
-  ret void
-}
-
-define signext i32 @ret_callresult_uint8_as_anyint32() nounwind {
-; RV32I-LABEL: ret_callresult_uint8_as_anyint32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(return_uint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_uint8)
-; RV32I-NEXT:    jalr a0
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call zeroext i8 @return_uint8()
-  %2 = zext i8 %1 to i32
-  ret i32 %2
-}
-
-define zeroext i8 @sint8_arg_to_uint8_ret(i8 signext %a) nounwind {
-; RV32I-LABEL: sint8_arg_to_uint8_ret:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i8 %a
-}
-
-define void @pass_sint8_as_uint8(i8 signext %a) nounwind {
-; RV32I-LABEL: pass_sint8_as_uint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    lui a1, %hi(receive_uint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_uint8)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  call void @receive_uint8(i8 zeroext %a)
-  ret void
-}
-
-declare signext i8 @return_sint8()
-
-define zeroext i8 @ret_callresult_sint8_as_uint8() nounwind {
-; RV32I-LABEL: ret_callresult_sint8_as_uint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(return_sint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_sint8)
-; RV32I-NEXT:    jalr a0
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call signext i8 @return_sint8()
-  ret i8 %1
-}
-
-define signext i8 @sint8_arg_to_sint8_ret(i8 signext %a) nounwind {
-; RV32I-LABEL: sint8_arg_to_sint8_ret:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i8 %a
-}
-
-define void @pass_sint8_as_sint8(i8 signext %a) nounwind {
-; RV32I-LABEL: pass_sint8_as_sint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(receive_sint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_sint8)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  call void @receive_sint8(i8 signext %a)
-  ret void
-}
-
-define signext i8 @ret_callresult_sint8_as_sint8() nounwind {
-; RV32I-LABEL: ret_callresult_sint8_as_sint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(return_sint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_sint8)
-; RV32I-NEXT:    jalr a0
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call signext i8 @return_sint8()
-  ret i8 %1
-}
-
-define signext i32 @sint8_arg_to_anyint32_ret(i8 signext %a) nounwind {
-; RV32I-LABEL: sint8_arg_to_anyint32_ret:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = sext i8 %a to i32
-  ret i32 %1
-}
-
-define void @pass_sint8_as_anyint32(i8 signext %a) nounwind {
-; RV32I-LABEL: pass_sint8_as_anyint32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(receive_anyint32)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_anyint32)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = sext i8 %a to i32
-  call void @receive_anyint32(i32 signext %1)
-  ret void
-}
-
-define signext i32 @ret_callresult_sint8_as_anyint32() nounwind {
-; RV32I-LABEL: ret_callresult_sint8_as_anyint32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(return_sint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_sint8)
-; RV32I-NEXT:    jalr a0
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call signext i8 @return_sint8()
-  %2 = sext i8 %1 to i32
-  ret i32 %2
-}
-
-define zeroext i8 @anyint32_arg_to_uint8_ret(i32 signext %a) nounwind {
-; RV32I-LABEL: anyint32_arg_to_uint8_ret:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = trunc i32 %a to i8
-  ret i8 %1
-}
-
-define void @pass_anyint32_as_uint8(i32 signext %a) nounwind {
-; RV32I-LABEL: pass_anyint32_as_uint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    lui a1, %hi(receive_uint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_uint8)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = trunc i32 %a to i8
-  call void @receive_uint8(i8 zeroext %1)
-  ret void
-}
-
-declare signext i32 @return_anyint32()
-
-define zeroext i8 @ret_callresult_anyint32_as_uint8() nounwind {
-; RV32I-LABEL: ret_callresult_anyint32_as_uint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(return_anyint32)
-; RV32I-NEXT:    addi a0, a0, %lo(return_anyint32)
-; RV32I-NEXT:    jalr a0
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call signext i32 @return_anyint32()
-  %2 = trunc i32 %1 to i8
-  ret i8 %2
-}
-
-define signext i8 @anyint32_arg_to_sint8_ret(i32 signext %a) nounwind {
-; RV32I-LABEL: anyint32_arg_to_sint8_ret:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    srai a0, a0, 24
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = trunc i32 %a to i8
-  ret i8 %1
-}
-
-define void @pass_anyint32_as_sint8(i32 signext %a) nounwind {
-; RV32I-LABEL: pass_anyint32_as_sint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(receive_sint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_sint8)
-; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    srai a0, a0, 24
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = trunc i32 %a to i8
-  call void @receive_sint8(i8 signext %1)
-  ret void
-}
-
-define signext i8 @ret_callresult_anyint32_as_sint8() nounwind {
-; RV32I-LABEL: ret_callresult_anyint32_as_sint8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(return_anyint32)
-; RV32I-NEXT:    addi a0, a0, %lo(return_anyint32)
-; RV32I-NEXT:    jalr a0
-; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    srai a0, a0, 24
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call signext i32 @return_anyint32()
-  %2 = trunc i32 %1 to i8
-  ret i8 %2
-}
-
-define signext i32 @anyint32_arg_to_anyint32_ret(i32 signext %a) nounwind {
-; RV32I-LABEL: anyint32_arg_to_anyint32_ret:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i32 %a
-}
-
-define void @pass_anyint32_as_anyint32(i32 signext %a) nounwind {
-; RV32I-LABEL: pass_anyint32_as_anyint32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(receive_anyint32)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_anyint32)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  call void @receive_anyint32(i32 signext %a)
-  ret void
-}
-
-define signext i32 @ret_callresult_anyint32_as_anyint32() nounwind {
-; RV32I-LABEL: ret_callresult_anyint32_as_anyint32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, %hi(return_anyint32)
-; RV32I-NEXT:    addi a0, a0, %lo(return_anyint32)
-; RV32I-NEXT:    jalr a0
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call signext i32 @return_anyint32()
-  ret i32 %1
-}
-

external/llvm/test/CodeGen/RISCV/calls.ll

@@ -1,197 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
-
-declare i32 @external_function(i32)
-
-define i32 @test_call_external(i32 %a) nounwind {
-; RV32I-LABEL: test_call_external:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(external_function)
-; RV32I-NEXT:    addi a1, a1, %lo(external_function)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call i32 @external_function(i32 %a)
-  ret i32 %1
-}
-
-define i32 @defined_function(i32 %a) nounwind {
-; RV32I-LABEL: defined_function:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    addi a0, a0, 1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = add i32 %a, 1
-  ret i32 %1
-}
-
-define i32 @test_call_defined(i32 %a) nounwind {
-; RV32I-LABEL: test_call_defined:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(defined_function)
-; RV32I-NEXT:    addi a1, a1, %lo(defined_function)
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call i32 @defined_function(i32 %a)
-  ret i32 %1
-}
-
-define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {
-; RV32I-LABEL: test_call_indirect:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:    jalr a2
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call i32 %a(i32 %b)
-  ret i32 %1
-}
-
-; Ensure that calls to fastcc functions aren't rejected. Such calls may be
-; introduced when compiling with optimisation.
-
-define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: fastcc_function:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
- %1 = add i32 %a, %b
- ret i32 %1
-}
-
-define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: test_call_fastcc:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    sw s1, 4(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    lui a0, %hi(fastcc_function)
-; RV32I-NEXT:    addi a2, a0, %lo(fastcc_function)
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    jalr a2
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    lw s1, 4(sp)
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = call fastcc i32 @fastcc_function(i32 %a, i32 %b)
-  ret i32 %a
-}
-
-declare i32 @external_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind
-
-define i32 @test_call_external_many_args(i32 %a) nounwind {
-; RV32I-LABEL: test_call_external_many_args:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s0, 24(sp)
-; RV32I-NEXT:    sw s1, 20(sp)
-; RV32I-NEXT:    addi s0, sp, 32
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    sw s1, 4(sp)
-; RV32I-NEXT:    sw s1, 0(sp)
-; RV32I-NEXT:    lui a0, %hi(external_many_args)
-; RV32I-NEXT:    addi t0, a0, %lo(external_many_args)
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    mv a2, s1
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
-; RV32I-NEXT:    mv a5, s1
-; RV32I-NEXT:    mv a6, s1
-; RV32I-NEXT:    mv a7, s1
-; RV32I-NEXT:    jalr t0
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    lw s1, 20(sp)
-; RV32I-NEXT:    lw s0, 24(sp)
-; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    ret
-  %1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
-                                    i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
-  ret i32 %a
-}
-
-define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %j) nounwind {
-; RV32I-LABEL: defined_many_args:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lw a0, 4(s0)
-; RV32I-NEXT:    addi a0, a0, 1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %added = add i32 %j, 1
-  ret i32 %added
-}
-
-define i32 @test_call_defined_many_args(i32 %a) nounwind {
-; RV32I-LABEL: test_call_defined_many_args:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s0, 24(sp)
-; RV32I-NEXT:    addi s0, sp, 32
-; RV32I-NEXT:    sw a0, 4(sp)
-; RV32I-NEXT:    sw a0, 0(sp)
-; RV32I-NEXT:    lui a1, %hi(defined_many_args)
-; RV32I-NEXT:    addi t0, a1, %lo(defined_many_args)
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    mv a3, a0
-; RV32I-NEXT:    mv a4, a0
-; RV32I-NEXT:    mv a5, a0
-; RV32I-NEXT:    mv a6, a0
-; RV32I-NEXT:    mv a7, a0
-; RV32I-NEXT:    jalr t0
-; RV32I-NEXT:    lw s0, 24(sp)
-; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    ret
-  %1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
-                                   i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
-  ret i32 %1
-}

external/llvm/test/CodeGen/RISCV/div.ll

@@ -1,188 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-define i32 @udiv(i32 %a, i32 %b) {
-; RV32I-LABEL: udiv:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a2, %hi(__udivsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__udivsi3)
-; RV32I-NEXT:    jalr a2
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = udiv i32 %a, %b
-  ret i32 %1
-}
-
-define i32 @udiv_constant(i32 %a) {
-; RV32I-LABEL: udiv_constant:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(__udivsi3)
-; RV32I-NEXT:    addi a2, a1, %lo(__udivsi3)
-; RV32I-NEXT:    addi a1, zero, 5
-; RV32I-NEXT:    jalr a2
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = udiv i32 %a, 5
-  ret i32 %1
-}
-
-define i32 @udiv_pow2(i32 %a) {
-; RV32I-LABEL: udiv_pow2:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    srli a0, a0, 3
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = udiv i32 %a, 8
-  ret i32 %1
-}
-
-define i64 @udiv64(i64 %a, i64 %b) {
-; RV32I-LABEL: udiv64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a4, %hi(__udivdi3)
-; RV32I-NEXT:    addi a4, a4, %lo(__udivdi3)
-; RV32I-NEXT:    jalr a4
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = udiv i64 %a, %b
-  ret i64 %1
-}
-
-define i64 @udiv64_constant(i64 %a) {
-; RV32I-LABEL: udiv64_constant:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a2, %hi(__udivdi3)
-; RV32I-NEXT:    addi a4, a2, %lo(__udivdi3)
-; RV32I-NEXT:    addi a2, zero, 5
-; RV32I-NEXT:    mv a3, zero
-; RV32I-NEXT:    jalr a4
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = udiv i64 %a, 5
-  ret i64 %1
-}
-
-define i32 @sdiv(i32 %a, i32 %b) {
-; RV32I-LABEL: sdiv:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a2, %hi(__divsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__divsi3)
-; RV32I-NEXT:    jalr a2
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = sdiv i32 %a, %b
-  ret i32 %1
-}
-
-define i32 @sdiv_constant(i32 %a) {
-; RV32I-LABEL: sdiv_constant:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(__divsi3)
-; RV32I-NEXT:    addi a2, a1, %lo(__divsi3)
-; RV32I-NEXT:    addi a1, zero, 5
-; RV32I-NEXT:    jalr a2
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = sdiv i32 %a, 5
-  ret i32 %1
-}
-
-define i32 @sdiv_pow2(i32 %a) {
-; RV32I-LABEL: sdiv_pow2:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    srai a1, a0, 31
-; RV32I-NEXT:    srli a1, a1, 29
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    srai a0, a0, 3
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = sdiv i32 %a, 8
-  ret i32 %1
-}
-
-define i64 @sdiv64(i64 %a, i64 %b) {
-; RV32I-LABEL: sdiv64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a4, %hi(__divdi3)
-; RV32I-NEXT:    addi a4, a4, %lo(__divdi3)
-; RV32I-NEXT:    jalr a4
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = sdiv i64 %a, %b
-  ret i64 %1
-}
-
-define i64 @sdiv64_constant(i64 %a) {
-; RV32I-LABEL: sdiv64_constant:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a2, %hi(__divdi3)
-; RV32I-NEXT:    addi a4, a2, %lo(__divdi3)
-; RV32I-NEXT:    addi a2, zero, 5
-; RV32I-NEXT:    mv a3, zero
-; RV32I-NEXT:    jalr a4
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = sdiv i64 %a, 5
-  ret i64 %1
-}

external/llvm/test/CodeGen/RISCV/fp128.ll

@@ -1,134 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
-
-@x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
-@y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
-
-; Besides anything else, these tests help verify that libcall ABI lowering
-; works correctly
-
-define i32 @test_load_and_cmp() nounwind {
-; RV32I-LABEL: test_load_and_cmp:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s0, 40(sp)
-; RV32I-NEXT:    addi s0, sp, 48
-; RV32I-NEXT:    lui a0, %hi(y+12)
-; RV32I-NEXT:    addi a0, a0, %lo(y+12)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -28(s0)
-; RV32I-NEXT:    lui a0, %hi(y+8)
-; RV32I-NEXT:    addi a0, a0, %lo(y+8)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -32(s0)
-; RV32I-NEXT:    lui a0, %hi(y+4)
-; RV32I-NEXT:    addi a0, a0, %lo(y+4)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -36(s0)
-; RV32I-NEXT:    lui a0, %hi(y)
-; RV32I-NEXT:    addi a0, a0, %lo(y)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -40(s0)
-; RV32I-NEXT:    lui a0, %hi(x+12)
-; RV32I-NEXT:    addi a0, a0, %lo(x+12)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -12(s0)
-; RV32I-NEXT:    lui a0, %hi(x+8)
-; RV32I-NEXT:    addi a0, a0, %lo(x+8)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -16(s0)
-; RV32I-NEXT:    lui a0, %hi(x+4)
-; RV32I-NEXT:    addi a0, a0, %lo(x+4)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -20(s0)
-; RV32I-NEXT:    lui a0, %hi(x)
-; RV32I-NEXT:    addi a0, a0, %lo(x)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -24(s0)
-; RV32I-NEXT:    lui a0, %hi(__netf2)
-; RV32I-NEXT:    addi a2, a0, %lo(__netf2)
-; RV32I-NEXT:    addi a0, s0, -24
-; RV32I-NEXT:    addi a1, s0, -40
-; RV32I-NEXT:    jalr a2
-; RV32I-NEXT:    xor a0, a0, zero
-; RV32I-NEXT:    snez a0, a0
-; RV32I-NEXT:    lw s0, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
-; RV32I-NEXT:    ret
-  %1 = load fp128, fp128* @x, align 16
-  %2 = load fp128, fp128* @y, align 16
-  %cmp = fcmp une fp128 %1, %2
-  %3 = zext i1 %cmp to i32
-  ret i32 %3
-}
-
-define i32 @test_add_and_fptosi() nounwind {
-; RV32I-LABEL: test_add_and_fptosi:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -80
-; RV32I-NEXT:    sw ra, 76(sp)
-; RV32I-NEXT:    sw s0, 72(sp)
-; RV32I-NEXT:    addi s0, sp, 80
-; RV32I-NEXT:    lui a0, %hi(y+12)
-; RV32I-NEXT:    addi a0, a0, %lo(y+12)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -44(s0)
-; RV32I-NEXT:    lui a0, %hi(y+8)
-; RV32I-NEXT:    addi a0, a0, %lo(y+8)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -48(s0)
-; RV32I-NEXT:    lui a0, %hi(y+4)
-; RV32I-NEXT:    addi a0, a0, %lo(y+4)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -52(s0)
-; RV32I-NEXT:    lui a0, %hi(y)
-; RV32I-NEXT:    addi a0, a0, %lo(y)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -56(s0)
-; RV32I-NEXT:    lui a0, %hi(x+12)
-; RV32I-NEXT:    addi a0, a0, %lo(x+12)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -28(s0)
-; RV32I-NEXT:    lui a0, %hi(x+8)
-; RV32I-NEXT:    addi a0, a0, %lo(x+8)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -32(s0)
-; RV32I-NEXT:    lui a0, %hi(x+4)
-; RV32I-NEXT:    addi a0, a0, %lo(x+4)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -36(s0)
-; RV32I-NEXT:    lui a0, %hi(x)
-; RV32I-NEXT:    addi a0, a0, %lo(x)
-; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    sw a0, -40(s0)
-; RV32I-NEXT:    lui a0, %hi(__addtf3)
-; RV32I-NEXT:    addi a3, a0, %lo(__addtf3)
-; RV32I-NEXT:    addi a0, s0, -24
-; RV32I-NEXT:    addi a1, s0, -40
-; RV32I-NEXT:    addi a2, s0, -56
-; RV32I-NEXT:    jalr a3
-; RV32I-NEXT:    lw a0, -12(s0)
-; RV32I-NEXT:    sw a0, -60(s0)
-; RV32I-NEXT:    lw a0, -16(s0)
-; RV32I-NEXT:    sw a0, -64(s0)
-; RV32I-NEXT:    lw a0, -20(s0)
-; RV32I-NEXT:    sw a0, -68(s0)
-; RV32I-NEXT:    lw a0, -24(s0)
-; RV32I-NEXT:    sw a0, -72(s0)
-; RV32I-NEXT:    lui a0, %hi(__fixtfsi)
-; RV32I-NEXT:    addi a1, a0, %lo(__fixtfsi)
-; RV32I-NEXT:    addi a0, s0, -72
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    lw s0, 72(sp)
-; RV32I-NEXT:    lw ra, 76(sp)
-; RV32I-NEXT:    addi sp, sp, 80
-; RV32I-NEXT:    ret
-  %1 = load fp128, fp128* @x, align 16
-  %2 = load fp128, fp128* @y, align 16
-  %3 = fadd fp128 %1, %2
-  %4 = fptosi fp128 %3 to i32
-  ret i32 %4
-}

external/llvm/test/CodeGen/RISCV/frame.ll

@@ -1,38 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
-
-%struct.key_t = type { i32, [16 x i8] }
-
-define i32 @test() nounwind {
-; RV32I-LABEL: test:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s0, 24(sp)
-; RV32I-NEXT:    addi s0, sp, 32
-; RV32I-NEXT:    sw zero, -16(s0)
-; RV32I-NEXT:    sw zero, -20(s0)
-; RV32I-NEXT:    sw zero, -24(s0)
-; RV32I-NEXT:    sw zero, -28(s0)
-; RV32I-NEXT:    sw zero, -32(s0)
-; RV32I-NEXT:    lui a0, %hi(test1)
-; RV32I-NEXT:    addi a1, a0, %lo(test1)
-; RV32I-NEXT:    addi a0, s0, -28
-; RV32I-NEXT:    jalr a1
-; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    lw s0, 24(sp)
-; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    ret
-  %key = alloca %struct.key_t, align 4
-  %1 = bitcast %struct.key_t* %key to i8*
-  call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 20, i32 4, i1 false)
-  %2 = getelementptr inbounds %struct.key_t, %struct.key_t* %key, i64 0, i32 1, i64 0
-  call void @test1(i8* %2) #3
-  ret i32 0
-}
-
-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
-
-declare void @test1(i8*)

external/llvm/test/CodeGen/RISCV/i32-icmp.ll

@@ -1,184 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-; TODO: check the generated instructions for the equivalent of seqz, snez,
-; sltz, sgtz map to something simple
-
-define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_eq:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    seqz a0, a0
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp eq i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_ne:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    snez a0, a0
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp ne i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_ugt:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sltu a0, a1, a0
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp ugt i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_uge:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sltu a0, a0, a1
-; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp uge i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_ult:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sltu a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp ult i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_ule:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sltu a0, a1, a0
-; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp ule i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_sgt:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp sgt i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_sge:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp sge i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_slt:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp slt i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_sle:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = icmp sle i32 %a, %b
-  %2 = zext i1 %1 to i32
-  ret i32 %2
-}
-
-; TODO: check variants with an immediate?

external/llvm/test/CodeGen/RISCV/imm.ll

@@ -1,82 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-; Materializing constants
-
-define i32 @zero() nounwind {
-; RV32I-LABEL: zero:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i32 0
-}
-
-define i32 @pos_small() nounwind {
-; RV32I-LABEL: pos_small:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    addi a0, zero, 2047
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i32 2047
-}
-
-define i32 @neg_small() nounwind {
-; RV32I-LABEL: neg_small:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    addi a0, zero, -2048
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i32 -2048
-}
-
-define i32 @pos_i32() nounwind {
-; RV32I-LABEL: pos_i32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, 423811
-; RV32I-NEXT:    addi a0, a0, -1297
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i32 1735928559
-}
-
-define i32 @neg_i32() nounwind {
-; RV32I-LABEL: neg_i32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a0, 912092
-; RV32I-NEXT:    addi a0, a0, -273
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ret i32 -559038737
-}

external/llvm/test/CodeGen/RISCV/indirectbr.ll

@@ -1,46 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-define i32 @indirectbr(i8* %target) nounwind {
-; RV32I-LABEL: indirectbr:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    jr a0
-; RV32I-NEXT:  .LBB0_1: # %ret
-; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  indirectbr i8* %target, [label %test_label]
-test_label:
-  br label %ret
-ret:
-  ret i32 0
-}
-
-define i32 @indirectbr_with_offset(i8* %a) nounwind {
-; RV32I-LABEL: indirectbr_with_offset:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    jalr zero, a0, 1380
-; RV32I-NEXT:  .LBB1_1: # %ret
-; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %target = getelementptr inbounds i8, i8* %a, i32 1380
-  indirectbr i8* %target, [label %test_label]
-test_label:
-  br label %ret
-ret:
-  ret i32 0
-}

external/llvm/test/CodeGen/RISCV/jumptable.ll

@@ -1,70 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-define void @jt(i32 %in, i32* %out) {
-; RV32I-LABEL: jt:
-; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    addi a2, zero, 2
-; RV32I-NEXT:    blt a2, a0, .LBB0_3
-; RV32I-NEXT:    j .LBB0_1
-; RV32I-NEXT:  .LBB0_1: # %entry
-; RV32I-NEXT:    addi a3, zero, 1
-; RV32I-NEXT:    beq a0, a3, .LBB0_5
-; RV32I-NEXT:    j .LBB0_2
-; RV32I-NEXT:  .LBB0_2: # %entry
-; RV32I-NEXT:    beq a0, a2, .LBB0_6
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_6: # %bb2
-; RV32I-NEXT:    addi a0, zero, 3
-; RV32I-NEXT:    sw a0, 0(a1)
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_3: # %entry
-; RV32I-NEXT:    addi a3, zero, 3
-; RV32I-NEXT:    beq a0, a3, .LBB0_7
-; RV32I-NEXT:    j .LBB0_4
-; RV32I-NEXT:  .LBB0_4: # %entry
-; RV32I-NEXT:    addi a2, zero, 4
-; RV32I-NEXT:    beq a0, a2, .LBB0_8
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_8: # %bb4
-; RV32I-NEXT:    addi a0, zero, 1
-; RV32I-NEXT:    sw a0, 0(a1)
-; RV32I-NEXT:  .LBB0_9: # %exit
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_5: # %bb1
-; RV32I-NEXT:    addi a0, zero, 4
-; RV32I-NEXT:    sw a0, 0(a1)
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_7: # %bb3
-; RV32I-NEXT:    sw a2, 0(a1)
-; RV32I-NEXT:    j .LBB0_9
-entry:
-  switch i32 %in, label %exit [
-    i32 1, label %bb1
-    i32 2, label %bb2
-    i32 3, label %bb3
-    i32 4, label %bb4
-  ]
-bb1:
-  store i32 4, i32* %out
-  br label %exit
-bb2:
-  store i32 3, i32* %out
-  br label %exit
-bb3:
-  store i32 2, i32* %out
-  br label %exit
-bb4:
-  store i32 1, i32* %out
-  br label %exit
-exit:
-  ret void
-}

external/llvm/test/CodeGen/RISCV/lit.local.cfg

@@ -1,2 +0,0 @@
-if not 'RISCV' in config.root.targets:
-    config.unsupported = True

external/llvm/test/CodeGen/RISCV/mem.ll

@@ -1,286 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
-
-; Check indexed and unindexed, sext, zext and anyext loads
-
-define i32 @lb(i8 *%a) nounwind {
-; RV32I-LABEL: lb:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lb a1, 0(a0)
-; RV32I-NEXT:    lb a0, 1(a0)
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = getelementptr i8, i8* %a, i32 1
-  %2 = load i8, i8* %1
-  %3 = sext i8 %2 to i32
-  ; the unused load will produce an anyext for selection
-  %4 = load volatile i8, i8* %a
-  ret i32 %3
-}
-
-define i32 @lh(i16 *%a) nounwind {
-; RV32I-LABEL: lh:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lh a1, 0(a0)
-; RV32I-NEXT:    lh a0, 4(a0)
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = getelementptr i16, i16* %a, i32 2
-  %2 = load i16, i16* %1
-  %3 = sext i16 %2 to i32
-  ; the unused load will produce an anyext for selection
-  %4 = load volatile i16, i16* %a
-  ret i32 %3
-}
-
-define i32 @lw(i32 *%a) nounwind {
-; RV32I-LABEL: lw:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lw a1, 0(a0)
-; RV32I-NEXT:    lw a0, 12(a0)
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = getelementptr i32, i32* %a, i32 3
-  %2 = load i32, i32* %1
-  %3 = load volatile i32, i32* %a
-  ret i32 %2
-}
-
-define i32 @lbu(i8 *%a) nounwind {
-; RV32I-LABEL: lbu:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lbu a1, 0(a0)
-; RV32I-NEXT:    lbu a0, 4(a0)
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = getelementptr i8, i8* %a, i32 4
-  %2 = load i8, i8* %1
-  %3 = zext i8 %2 to i32
-  %4 = load volatile i8, i8* %a
-  %5 = zext i8 %4 to i32
-  %6 = add i32 %3, %5
-  ret i32 %6
-}
-
-define i32 @lhu(i16 *%a) nounwind {
-; RV32I-LABEL: lhu:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lhu a1, 0(a0)
-; RV32I-NEXT:    lhu a0, 10(a0)
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = getelementptr i16, i16* %a, i32 5
-  %2 = load i16, i16* %1
-  %3 = zext i16 %2 to i32
-  %4 = load volatile i16, i16* %a
-  %5 = zext i16 %4 to i32
-  %6 = add i32 %3, %5
-  ret i32 %6
-}
-
-; Check indexed and unindexed stores
-
-define void @sb(i8 *%a, i8 %b) nounwind {
-; RV32I-LABEL: sb:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sb a1, 6(a0)
-; RV32I-NEXT:    sb a1, 0(a0)
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  store i8 %b, i8* %a
-  %1 = getelementptr i8, i8* %a, i32 6
-  store i8 %b, i8* %1
-  ret void
-}
-
-define void @sh(i16 *%a, i16 %b) nounwind {
-; RV32I-LABEL: sh:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sh a1, 14(a0)
-; RV32I-NEXT:    sh a1, 0(a0)
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  store i16 %b, i16* %a
-  %1 = getelementptr i16, i16* %a, i32 7
-  store i16 %b, i16* %1
-  ret void
-}
-
-define void @sw(i32 *%a, i32 %b) nounwind {
-; RV32I-LABEL: sw:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    sw a1, 32(a0)
-; RV32I-NEXT:    sw a1, 0(a0)
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  store i32 %b, i32* %a
-  %1 = getelementptr i32, i32* %a, i32 8
-  store i32 %b, i32* %1
-  ret void
-}
-
-; Check load and store to an i1 location
-define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
-; RV32I-LABEL: load_sext_zext_anyext_i1:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lb a1, 0(a0)
-; RV32I-NEXT:    lbu a1, 1(a0)
-; RV32I-NEXT:    lbu a0, 2(a0)
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ; sextload i1
-  %1 = getelementptr i1, i1* %a, i32 1
-  %2 = load i1, i1* %1
-  %3 = sext i1 %2 to i32
-  ; zextload i1
-  %4 = getelementptr i1, i1* %a, i32 2
-  %5 = load i1, i1* %4
-  %6 = zext i1 %5 to i32
-  %7 = add i32 %3, %6
-  ; extload i1 (anyext). Produced as the load is unused.
-  %8 = load volatile i1, i1* %a
-  ret i32 %7
-}
-
-define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
-; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lb a1, 0(a0)
-; RV32I-NEXT:    lbu a1, 1(a0)
-; RV32I-NEXT:    lbu a0, 2(a0)
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  ; sextload i1
-  %1 = getelementptr i1, i1* %a, i32 1
-  %2 = load i1, i1* %1
-  %3 = sext i1 %2 to i16
-  ; zextload i1
-  %4 = getelementptr i1, i1* %a, i32 2
-  %5 = load i1, i1* %4
-  %6 = zext i1 %5 to i16
-  %7 = add i16 %3, %6
-  ; extload i1 (anyext). Produced as the load is unused.
-  %8 = load volatile i1, i1* %a
-  ret i16 %7
-}
-
-; Check load and store to a global
-@G = global i32 0
-
-define i32 @lw_sw_global(i32 %a) nounwind {
-; TODO: the addi should be folded in to the lw/sw operations
-; RV32I-LABEL: lw_sw_global:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, %hi(G)
-; RV32I-NEXT:    addi a2, a1, %lo(G)
-; RV32I-NEXT:    lw a1, 0(a2)
-; RV32I-NEXT:    sw a0, 0(a2)
-; RV32I-NEXT:    lui a2, %hi(G+36)
-; RV32I-NEXT:    addi a2, a2, %lo(G+36)
-; RV32I-NEXT:    lw a3, 0(a2)
-; RV32I-NEXT:    sw a0, 0(a2)
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = load volatile i32, i32* @G
-  store i32 %a, i32* @G
-  %2 = getelementptr i32, i32* @G, i32 9
-  %3 = load volatile i32, i32* %2
-  store i32 %a, i32* %2
-  ret i32 %1
-}
-
-; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
-define i32 @lw_sw_constant(i32 %a) nounwind {
-; TODO: the addi should be folded in to the lw/sw
-; RV32I-LABEL: lw_sw_constant:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s0, 8(sp)
-; RV32I-NEXT:    addi s0, sp, 16
-; RV32I-NEXT:    lui a1, 912092
-; RV32I-NEXT:    addi a2, a1, -273
-; RV32I-NEXT:    lw a1, 0(a2)
-; RV32I-NEXT:    sw a0, 0(a2)
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:    lw s0, 8(sp)
-; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
-  %1 = inttoptr i32 3735928559 to i32*
-  %2 = load volatile i32, i32* %1
-  store i32 %a, i32* %1
-  ret i32 %2
-}