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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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22
external/llvm/test/CodeGen/PowerPC/mtvsrdd.ll vendored
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@@ -1,22 +0,0 @@
; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
define <2 x i64> @const0(i64 %a) {
%vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
%vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1
ret <2 x i64> %vecinit1
; CHECK-LABEL: const0
; CHECK: mtvsrdd v2, 0, r3
}
define <2 x i64> @noconst0(i64* %a, i64* %b) {
%1 = load i64, i64* %a, align 8
%2 = load i64, i64* %b, align 8
%vecinit = insertelement <2 x i64> undef, i64 %2, i32 0
%vecinit1 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
ret <2 x i64> %vecinit1
; CHECK-LABEL: noconst0
; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
}