mono/linux-packaging-mono
0
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Imported Upstream version 5.18.0.167

Browse Source 
Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
This commit is contained in:
Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
external/llvm/test/CodeGen/Mips/lw16-base-reg.ll vendored
View File

@ -1,24 +0,0 @@
; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
; The purpose of this test is to check whether the CodeGen selects
; LW16 instruction with the base register in a range of $2-$7, $16, $17.
%struct.T = type { i32 }
$_ZN1TaSERKS_ = comdat any
define linkonce_odr void @_ZN1TaSERKS_(%struct.T* %this, %struct.T* dereferenceable(4) %t) #0 comdat align 2 {
entry:
%this.addr = alloca %struct.T*, align 4
%t.addr = alloca %struct.T*, align 4
%this1 = load %struct.T*, %struct.T** %this.addr, align 4
%0 = load %struct.T*, %struct.T** %t.addr, align 4
%V3 = getelementptr inbounds %struct.T, %struct.T* %0, i32 0, i32 0
%1 = load i32, i32* %V3, align 4
%V4 = getelementptr inbounds %struct.T, %struct.T* %this1, i32 0, i32 0
store i32 %1, i32* %V4, align 4
ret void
}
; CHECK: lw16 ${{[0-9]+}}, 0(${{[2-7]|16|17}})