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Imported Upstream version 5.18.0.167
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521
external/llvm/test/CodeGen/Mips/llvm-ir/add.ll
vendored
521
external/llvm/test/CodeGen/Mips/llvm-ir/add.ll
vendored
File diff suppressed because it is too large
Load Diff
@ -1,12 +0,0 @@
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
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; Address spaces 1-255 are software defined.
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define i32* @cast(i32 *%arg) {
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%1 = addrspacecast i32* %arg to i32 addrspace(1)*
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%2 = addrspacecast i32 addrspace(1)* %1 to i32 addrspace(2)*
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%3 = addrspacecast i32 addrspace(2)* %2 to i32 addrspace(0)*
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ret i32* %3
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}
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; ALL-LABEL: cast:
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; ALL: move $2, $4
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2135
external/llvm/test/CodeGen/Mips/llvm-ir/and.ll
vendored
2135
external/llvm/test/CodeGen/Mips/llvm-ir/and.ll
vendored
File diff suppressed because it is too large
Load Diff
986
external/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
vendored
986
external/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
vendored
File diff suppressed because it is too large
Load Diff
@ -1,26 +0,0 @@
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; RUN: llc -asm-show-inst -march=mipsel -mcpu=mips32r6 < %s | \
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; RUN: FileCheck %s -check-prefix=CHK32
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; RUN: llc -asm-show-inst -march=mips64el -mcpu=mips64r6 < %s | \
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; RUN: FileCheck %s -check-prefix=CHK64
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@a = common global i32 0, align 4
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@b = common global i64 0, align 8
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define i32 @ll_sc(i32 signext %x) {
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; CHK32-LABEL: ll_sc
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;CHK32: LL_R6
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;CHK32: SC_R6
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%1 = atomicrmw add i32* @a, i32 %x monotonic
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ret i32 %1
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}
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define i64 @lld_scd(i64 signext %x) {
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; CHK64-LABEL: lld_scd
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;CHK64: LLD_R6
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;CHK64: SCD_R6
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%1 = atomicrmw add i64* @b, i64 %x monotonic
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ret i64 %1
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}
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188
external/llvm/test/CodeGen/Mips/llvm-ir/call.ll
vendored
188
external/llvm/test/CodeGen/Mips/llvm-ir/call.ll
vendored
@ -1,188 +0,0 @@
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; Test the 'call' instruction and the tailcall variant.
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; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
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; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
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; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
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; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
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; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
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; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
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; RUN: llc -march=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,R6C
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; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
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; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
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; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
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; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
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; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
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; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
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; RUN: llc -march=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
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; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C
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declare void @extern_void_void()
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declare i32 @extern_i32_void()
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declare float @extern_float_void()
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define i32 @call_void_void() {
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; ALL-LABEL: call_void_void:
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; O32: lw $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
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; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
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; NOT-R6C: jalr $[[TGT]]
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; R6C: jalrc $[[TGT]]
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call void @extern_void_void()
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; R6C: jrc $ra
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ret i32 0
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}
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define i32 @call_i32_void() {
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; ALL-LABEL: call_i32_void:
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; O32: lw $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
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; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
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; NOT-R6C: jalr $[[TGT]]
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; R6C: jalrc $[[TGT]]
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%1 = call i32 @extern_i32_void()
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%2 = add i32 %1, 1
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; R6C: jrc $ra
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ret i32 %2
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}
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define float @call_float_void() {
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; ALL-LABEL: call_float_void:
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; FIXME: Not sure why we don't use $gp directly on such a simple test. We should
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; look into it at some point.
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; O32: addu $[[GP:[0-9]+]], ${{[0-9]+}}, $25
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; O32: lw $[[TGT:[0-9]+]], %call16(extern_float_void)($[[GP]])
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; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
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; NOT-R6C: jalr $[[TGT]]
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; R6C: jalrc $[[TGT]]
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%1 = call float @extern_float_void()
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%2 = fadd float %1, 1.0
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; R6C: jrc $ra
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ret float %2
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}
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define i32 @indirect_call_void_void(void ()* %addr) {
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; ALL-LABEL: indirect_call_void_void:
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; ALL: move $25, $4
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; NOT-R6C: jalr $25
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; R6C: jalrc $25
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call void %addr()
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; R6C: jrc $ra
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ret i32 0
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}
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define i32 @indirect_call_i32_void(i32 ()* %addr) {
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; ALL-LABEL: indirect_call_i32_void:
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; ALL: move $25, $4
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; NOT-R6C: jalr $25
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; R6C: jalrc $25
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%1 = call i32 %addr()
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%2 = add i32 %1, 1
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; R6C: jrc $ra
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ret i32 %2
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}
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define float @indirect_call_float_void(float ()* %addr) {
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; ALL-LABEL: indirect_call_float_void:
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; ALL: move $25, $4
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; NOT-R6C: jalr $25
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; R6C: jalrc $25
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%1 = call float %addr()
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%2 = fadd float %1, 1.0
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; R6C: jrc $ra
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ret float %2
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}
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; We can't use 'musttail' here because the verifier is too conservative and
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; prohibits any prototype difference.
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define void @tail_indirect_call_void_void(void ()* %addr) {
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; ALL-LABEL: tail_indirect_call_void_void:
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; ALL: move $25, $4
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; NOT-R6C: jr $[[TGT]]
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; R6C: jrc $[[TGT]]
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tail call void %addr()
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ret void
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}
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define i32 @tail_indirect_call_i32_void(i32 ()* %addr) {
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; ALL-LABEL: tail_indirect_call_i32_void:
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; ALL: move $25, $4
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; NOT-R6C: jr $[[TGT]]
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; R6C: jrc $[[TGT]]
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%1 = tail call i32 %addr()
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ret i32 %1
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}
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define float @tail_indirect_call_float_void(float ()* %addr) {
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; ALL-LABEL: tail_indirect_call_float_void:
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; ALL: move $25, $4
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; NOT-R6C: jr $[[TGT]]
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; R6C: jrc $[[TGT]]
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%1 = tail call float %addr()
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ret float %1
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}
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; Check that passing undef as a double value doesn't cause machine code errors
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; for FP64.
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declare hidden void @undef_double(i32 %this, double %volume) unnamed_addr align 2
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define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 {
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; ALL-LABEL: thunk_undef_double:
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; O32: # implicit-def: %a2
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; O32: # implicit-def: %a3
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; NOT-R6C: jr $[[TGT]]
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; R6C: jrc $[[TGT]]
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tail call void @undef_double(i32 undef, double undef) #8
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ret void
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}
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; Check that immediate addresses do not use jal.
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define i32 @jal_only_allows_symbols() {
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; ALL-LABEL: jal_only_allows_symbols:
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; ALL-NOT: {{jal }}
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; ALL: addiu $[[TGT:[0-9]+]], $zero, 1234
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; ALL-NOT: {{jal }}
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; NOT-R6C: jalr $[[TGT]]
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; R6C: jalrc $[[TGT]]
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; ALL-NOT: {{jal }}
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call void () inttoptr (i32 1234 to void ()*)()
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; R6C: jrc $ra
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ret i32 0
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}
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@ -1,19 +0,0 @@
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
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; This test triggered a bug in the vector splitting where the type legalizer
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; attempted to extract the element with by storing the vector, then reading
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; an element back. However, the address calculation was:
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; Base + Index * (EltSizeInBits / 8)
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; and EltSizeInBits was 1. This caused the index to be forgotten.
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define i1 @via_stack_bug(i8 signext %idx) {
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%1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx
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ret i1 %1
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}
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; ALL-LABEL: via_stack_bug:
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; ALL-DAG: addiu [[ONE:\$[0-9]+]], $zero, 1
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; ALL-DAG: sh [[ONE]], 6($sp)
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; ALL-DAG: andi [[MASKED_IDX:\$[0-9]+]], $4, 1
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; ALL-DAG: addiu [[VPTR:\$[0-9]+]], $sp, 6
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; ALL-DAG: or [[EPTR:\$[0-9]+]], [[VPTR]], [[MASKED_IDX]]
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; ALL: lbu $2, 0([[EPTR]])
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@ -1,41 +0,0 @@
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; Test all important variants of the unconditional 'br' instruction.
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; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C
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; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6
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define i32 @br(i8 *%addr) {
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; ALL-LABEL: br:
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; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR
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; R6C: jrc $4 # <MCInst #{{[0-9]+}} JIC
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; ALL: {{\$|\.L}}BB0_1: # %L1
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
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; ALL: addiu $2, $zero, 0
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; ALL: {{\$|\.L}}BB0_2: # %L2
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
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; ALL: addiu $2, $zero, 1
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entry:
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indirectbr i8* %addr, [label %L1, label %L2]
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L1:
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ret i32 0
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L2:
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ret i32 1
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}
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@ -1,31 +0,0 @@
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; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s
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; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s
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@us = global i16 0, align 2
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define i32 @lhfunc() {
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entry:
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; CHECK-LABEL: lhfunc
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; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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%0 = load i16, i16* @us, align 2
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%conv = sext i16 %0 to i32
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ret i32 %conv
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}
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define i16 @lhfunc_atomic() {
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entry:
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; CHECK-LABEL: lhfunc_atomic
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; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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%0 = load atomic i16, i16* @us acquire, align 2
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ret i16 %0
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}
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define i32 @lhufunc() {
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entry:
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; CHECK-LABEL: lhufunc
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; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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%0 = load i16, i16* @us, align 2
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%conv = zext i16 %0 to i32
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ret i32 %conv
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}
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@ -1,42 +0,0 @@
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; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,M64
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,M64
|
||||
|
||||
define i8 @load_i8(i8* %ptr) {
|
||||
; ALL-LABEL: load_i8
|
||||
|
||||
; ALL: lb $2, 0($4)
|
||||
; ALL: sync
|
||||
%val = load atomic i8, i8* %ptr acquire, align 1
|
||||
ret i8 %val
|
||||
}
|
||||
|
||||
define i16 @load_i16(i16* %ptr) {
|
||||
; ALL-LABEL: load_i16
|
||||
|
||||
; ALL: lh $2, 0($4)
|
||||
; ALL: sync
|
||||
%val = load atomic i16, i16* %ptr acquire, align 2
|
||||
ret i16 %val
|
||||
}
|
||||
|
||||
define i32 @load_i32(i32* %ptr) {
|
||||
; ALL-LABEL: load_i32
|
||||
|
||||
; ALL: lw $2, 0($4)
|
||||
; ALL: sync
|
||||
%val = load atomic i32, i32* %ptr acquire, align 4
|
||||
ret i32 %val
|
||||
}
|
||||
|
||||
define i64 @load_i64(i64* %ptr) {
|
||||
; M64-LABEL: load_i64
|
||||
|
||||
; M64: ld $2, 0($4)
|
||||
; M64: sync
|
||||
%val = load atomic i64, i64* %ptr acquire, align 8
|
||||
ret i64 %val
|
||||
}
|
||||
1018
external/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
vendored
1018
external/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
vendored
File diff suppressed because it is too large
Load Diff
253
external/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
vendored
253
external/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
vendored
@ -1,253 +0,0 @@
|
||||
; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=ALL,64R6
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=MM32,MM32R3
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
|
||||
; RUN: FileCheck %s -check-prefixes=MM32,MM32R6
|
||||
|
||||
define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: mul_i1:
|
||||
|
||||
; M2: mult $4, $5
|
||||
; M2: mflo $[[T0:[0-9]+]]
|
||||
; M2: andi $[[T0]], $[[T0]], 1
|
||||
; M2: negu $2, $[[T0]]
|
||||
|
||||
; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 32R1-R5: andi $[[T0]], $[[T0]], 1
|
||||
; 32R1-R5: negu $2, $[[T0]]
|
||||
|
||||
; 32R6: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 32R6: andi $[[T0]], $[[T0]], 1
|
||||
; 32R6: negu $2, $[[T0]]
|
||||
|
||||
; M4: mult $4, $5
|
||||
; M4: mflo $[[T0:[0-9]+]]
|
||||
; M4: andi $[[T0]], $[[T0]], 1
|
||||
; M4: negu $2, $[[T0]]
|
||||
|
||||
; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 64R1-R5: andi $[[T0]], $[[T0]], 1
|
||||
; 64R1-R5: negu $2, $[[T0]]
|
||||
|
||||
; 64R6: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 64R6: andi $[[T0]], $[[T0]], 1
|
||||
; 64R6: negu $2, $[[T0]]
|
||||
|
||||
; MM32: mul $[[T0:[0-9]+]], $4, $5
|
||||
; MM32: andi16 $[[T0]], $[[T0]], 1
|
||||
; MM32: li16 $[[T1:[0-9]+]], 0
|
||||
; MM32: subu16 $2, $[[T1]], $[[T0]]
|
||||
|
||||
%r = mul i1 %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: mul_i8:
|
||||
|
||||
; M2: mult $4, $5
|
||||
; M2: mflo $[[T0:[0-9]+]]
|
||||
; M2: sll $[[T0]], $[[T0]], 24
|
||||
; M2: sra $2, $[[T0]], 24
|
||||
|
||||
; 32R1: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 32R1: sll $[[T0]], $[[T0]], 24
|
||||
; 32R1: sra $2, $[[T0]], 24
|
||||
|
||||
; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 32R2-R5: seb $2, $[[T0]]
|
||||
|
||||
; 32R6: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 32R6: seb $2, $[[T0]]
|
||||
|
||||
; M4: mult $4, $5
|
||||
; M4: mflo $[[T0:[0-9]+]]
|
||||
; M4: sll $[[T0]], $[[T0]], 24
|
||||
; M4: sra $2, $[[T0]], 24
|
||||
|
||||
; 64R1: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 64R1: sll $[[T0]], $[[T0]], 24
|
||||
; 64R1: sra $2, $[[T0]], 24
|
||||
|
||||
; 64R2: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 64R2: seb $2, $[[T0]]
|
||||
|
||||
; 64R6: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 64R6: seb $2, $[[T0]]
|
||||
|
||||
; MM32: mul $[[T0:[0-9]+]], $4, $5
|
||||
; MM32: seb $2, $[[T0]]
|
||||
|
||||
%r = mul i8 %a, %b
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: mul_i16:
|
||||
|
||||
; M2: mult $4, $5
|
||||
; M2: mflo $[[T0:[0-9]+]]
|
||||
; M2: sll $[[T0]], $[[T0]], 16
|
||||
; M2: sra $2, $[[T0]], 16
|
||||
|
||||
; 32R1: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 32R1: sll $[[T0]], $[[T0]], 16
|
||||
; 32R1: sra $2, $[[T0]], 16
|
||||
|
||||
; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 32R2-R5: seh $2, $[[T0]]
|
||||
|
||||
; 32R6: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 32R6: seh $2, $[[T0]]
|
||||
|
||||
; M4: mult $4, $5
|
||||
; M4: mflo $[[T0:[0-9]+]]
|
||||
; M4: sll $[[T0]], $[[T0]], 16
|
||||
; M4: sra $2, $[[T0]], 16
|
||||
|
||||
; 64R1: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 64R1: sll $[[T0]], $[[T0]], 16
|
||||
; 64R1: sra $2, $[[T0]], 16
|
||||
|
||||
; 64R2: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 64R2: seh $2, $[[T0]]
|
||||
|
||||
; 64R6: mul $[[T0:[0-9]+]], $4, $5
|
||||
; 64R6: seh $2, $[[T0]]
|
||||
|
||||
; MM32: mul $[[T0:[0-9]+]], $4, $5
|
||||
; MM32: seh $2, $[[T0]]
|
||||
|
||||
%r = mul i16 %a, %b
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: mul_i32:
|
||||
|
||||
; M2: mult $4, $5
|
||||
; M2: mflo $2
|
||||
|
||||
; 32R1-R5: mul $2, $4, $5
|
||||
; 32R6: mul $2, $4, $5
|
||||
|
||||
; 64R1-R5: mul $2, $4, $5
|
||||
; 64R6: mul $2, $4, $5
|
||||
|
||||
; MM32: mul $2, $4, $5
|
||||
|
||||
%r = mul i32 %a, %b
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: mul_i64:
|
||||
|
||||
; M2: mult $4, $7
|
||||
; M2: mflo $[[T0:[0-9]+]]
|
||||
; M2: mult $5, $6
|
||||
; M2: mflo $[[T1:[0-9]+]]
|
||||
; M2: multu $5, $7
|
||||
; M2: mflo $3
|
||||
; M2: mfhi $4
|
||||
; M2: addu $[[T2:[0-9]+]], $4, $[[T1]]
|
||||
; M2: addu $2, $[[T2]], $[[T0]]
|
||||
|
||||
; 32R1-R5: multu $5, $7
|
||||
; 32R1-R5: mflo $3
|
||||
; 32R1-R5: mfhi $[[T0:[0-9]+]]
|
||||
; 32R1-R5: mul $[[T1:[0-9]+]], $5, $6
|
||||
; 32R1-R5: addu $[[T0]], $[[T0]], $[[T1:[0-9]+]]
|
||||
; 32R1-R5: mul $[[T2:[0-9]+]], $4, $7
|
||||
; 32R1-R5: addu $2, $[[T0]], $[[T2]]
|
||||
|
||||
; 32R6-DAG: mul $[[T0:[0-9]+]], $5, $6
|
||||
; 32R6: muhu $[[T1:[0-9]+]], $5, $7
|
||||
; 32R6: addu $[[T0]], $[[T1]], $[[T0]]
|
||||
; 32R6-DAG: mul $[[T2:[0-9]+]], $4, $7
|
||||
; 32R6: addu $2, $[[T0]], $[[T2]]
|
||||
; 32R6-DAG: mul $3, $5, $7
|
||||
|
||||
; M4: dmult $4, $5
|
||||
; M4: mflo $2
|
||||
|
||||
; 64R1-R5: dmult $4, $5
|
||||
; 64R1-R5: mflo $2
|
||||
|
||||
; 64R6: dmul $2, $4, $5
|
||||
|
||||
; MM32R3: multu $[[T0:[0-9]+]], $7
|
||||
; MM32R3: mflo $[[T1:[0-9]+]]
|
||||
; MM32R3: mfhi $[[T2:[0-9]+]]
|
||||
; MM32R3: mul $[[T0]], $[[T0]], $6
|
||||
; MM32R3: addu16 $2, $[[T2]], $[[T0]]
|
||||
; MM32R3: mul $[[T3:[0-9]+]], $4, $7
|
||||
; MM32R3: addu16 $[[T2]], $[[T2]], $[[T3]]
|
||||
|
||||
; MM32R6: mul $[[T0:[0-9]+]], $5, $6
|
||||
; MM32R6: muhu $[[T1:[0-9]+]], $5, $7
|
||||
; MM32R6: addu16 $[[T2:[0-9]+]], $[[T1]], $[[T0]]
|
||||
; MM32R6: mul $[[T3:[0-9]+]], $4, $7
|
||||
; MM32R6: addu16 $2, $[[T2]], $[[T3]]
|
||||
; MM32R6: mul $[[T1]], $5, $7
|
||||
|
||||
%r = mul i64 %a, %b
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: mul_i128:
|
||||
|
||||
; GP32: lw $25, %call16(__multi3)($gp)
|
||||
|
||||
; GP64-NOT-R6: dmult $4, $7
|
||||
; GP64-NOT-R6: mflo $[[T0:[0-9]+]]
|
||||
; GP64-NOT-R6: dmult $5, $6
|
||||
; GP64-NOT-R6: mflo $[[T1:[0-9]+]]
|
||||
; GP64-NOT-R6: dmultu $5, $7
|
||||
; GP64-NOT-R6: mflo $3
|
||||
; GP64-NOT-R6: mfhi $[[T2:[0-9]+]]
|
||||
; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]
|
||||
|
||||
; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
|
||||
; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7
|
||||
; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
|
||||
; 64R6: daddu $2, $[[T1]], $[[T0]]
|
||||
; 64R6-DAG: dmul $3, $5, $7
|
||||
|
||||
; MM32: lw $25, %call16(__multi3)($16)
|
||||
|
||||
%r = mul i128 %a, %b
|
||||
ret i128 %r
|
||||
}
|
||||
227
external/llvm/test/CodeGen/Mips/llvm-ir/not.ll
vendored
227
external/llvm/test/CodeGen/Mips/llvm-ir/not.ll
vendored
@ -1,227 +0,0 @@
|
||||
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP32
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,GP64
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MM,MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MM,MM32
|
||||
|
||||
define signext i1 @not_i1(i1 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: not_i1:
|
||||
|
||||
; GP32: not $2, $4
|
||||
|
||||
; GP64: not $2, $4
|
||||
|
||||
; MM: not16 $2, $4
|
||||
|
||||
%r = xor i1 %a, -1
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define signext i8 @not_i8(i8 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: not_i8:
|
||||
|
||||
; GP32: not $2, $4
|
||||
|
||||
; GP64: not $2, $4
|
||||
|
||||
; MM: not16 $2, $4
|
||||
|
||||
%r = xor i8 %a, -1
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
define signext i16 @not_i16(i16 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: not_i16:
|
||||
|
||||
; GP32: not $2, $4
|
||||
|
||||
; GP64: not $2, $4
|
||||
|
||||
; MM: not16 $2, $4
|
||||
|
||||
%r = xor i16 %a, -1
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
define signext i32 @not_i32(i32 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: not_i32:
|
||||
|
||||
; GP32: not $2, $4
|
||||
|
||||
; GP64: not $2, $4
|
||||
|
||||
; MM: not16 $2, $4
|
||||
|
||||
%r = xor i32 %a, -1
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define signext i64 @not_i64(i64 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: not_i64:
|
||||
|
||||
; GP32: not $2, $4
|
||||
; GP32: not $3, $5
|
||||
|
||||
; GP64: daddiu $[[T0:[0-9]+]], $zero, -1
|
||||
; GP64: xor $2, $4, $[[T0]]
|
||||
|
||||
; MM32: not16 $2, $4
|
||||
; MM32: not16 $3, $5
|
||||
|
||||
%r = xor i64 %a, -1
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define signext i128 @not_i128(i128 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: not_i128:
|
||||
|
||||
; GP32: not $2, $4
|
||||
; GP32: not $3, $5
|
||||
; GP32: not $4, $6
|
||||
; GP32: not $5, $7
|
||||
|
||||
; GP64: daddiu $[[T0:[0-9]+]], $zero, -1
|
||||
; GP64: xor $2, $4, $[[T0]]
|
||||
; GP64: xor $3, $5, $[[T0]]
|
||||
|
||||
; MM32: not16 $2, $4
|
||||
; MM32: not16 $3, $5
|
||||
; MM32: not16 $4, $6
|
||||
; MM32: not16 $5, $7
|
||||
|
||||
%r = xor i128 %a, -1
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define signext i1 @nor_i1(i1 signext %a, i1 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: nor_i1:
|
||||
|
||||
; GP32: nor $2, $5, $4
|
||||
; GP64: or $1, $5, $4
|
||||
; MM32: nor $2, $5, $4
|
||||
|
||||
%or = or i1 %b, %a
|
||||
%r = xor i1 %or, -1
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define signext i8 @nor_i8(i8 signext %a, i8 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: nor_i8:
|
||||
|
||||
; GP32: nor $2, $5, $4
|
||||
; GP64: or $1, $5, $4
|
||||
; MM32: nor $2, $5, $4
|
||||
|
||||
%or = or i8 %b, %a
|
||||
%r = xor i8 %or, -1
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
define signext i16 @nor_i16(i16 signext %a, i16 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: nor_i16:
|
||||
|
||||
; GP32: nor $2, $5, $4
|
||||
; GP64: or $1, $5, $4
|
||||
; MM32: nor $2, $5, $4
|
||||
|
||||
%or = or i16 %b, %a
|
||||
%r = xor i16 %or, -1
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
define signext i32 @nor_i32(i32 signext %a, i32 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: nor_i32:
|
||||
|
||||
; GP32: nor $2, $5, $4
|
||||
|
||||
; GP64: or $[[T0:[0-9]+]], $5, $4
|
||||
; GP64: sll $[[T1:[0-9]+]], $[[T0]], 0
|
||||
; GP64: not $2, $[[T1]]
|
||||
|
||||
; MM32: nor $2, $5, $4
|
||||
|
||||
%or = or i32 %b, %a
|
||||
%r = xor i32 %or, -1
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
|
||||
define signext i64 @nor_i64(i64 signext %a, i64 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: nor_i64:
|
||||
|
||||
; GP32: nor $2, $6, $4
|
||||
; GP32: nor $3, $7, $5
|
||||
|
||||
; GP64: nor $2, $5, $4
|
||||
|
||||
; MM32: nor $2, $6, $4
|
||||
; MM32: nor $3, $7, $5
|
||||
|
||||
%or = or i64 %b, %a
|
||||
%r = xor i64 %or, -1
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define signext i128 @nor_i128(i128 signext %a, i128 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: nor_i128:
|
||||
|
||||
; GP32: lw $[[T1:[0-9]+]], 20($sp)
|
||||
; GP32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; GP32: nor $2, $[[T2]], $4
|
||||
; GP32: nor $3, $[[T1]], $5
|
||||
; GP32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; GP32: nor $4, $[[T0]], $6
|
||||
; GP32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; GP32: nor $5, $[[T3]], $7
|
||||
|
||||
; GP64: nor $2, $6, $4
|
||||
; GP64: nor $3, $7, $5
|
||||
|
||||
; MM32: lw $[[T1:[0-9]+]], 20($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; MM32: nor $2, $[[T2]], $4
|
||||
; MM32: nor $3, $[[T1]], $5
|
||||
; MM32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; MM32: nor $4, $[[T0]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; MM32: nor $5, $[[T3]], $7
|
||||
|
||||
%or = or i128 %b, %a
|
||||
%r = xor i128 %or, -1
|
||||
ret i128 %r
|
||||
}
|
||||
1209
external/llvm/test/CodeGen/Mips/llvm-ir/or.ll
vendored
1209
external/llvm/test/CodeGen/Mips/llvm-ir/or.ll
vendored
File diff suppressed because it is too large
Load Diff
219
external/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
vendored
219
external/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
vendored
@ -1,219 +0,0 @@
|
||||
; Test all important variants of the 'ret' instruction.
|
||||
;
|
||||
; For non-void returns it is necessary to have something to return so we also
|
||||
; test constant generation here.
|
||||
;
|
||||
; We'll test pointer returns in a separate file since the relocation model
|
||||
; affects it and it's undesirable to repeat the non-pointer returns for each
|
||||
; relocation model.
|
||||
|
||||
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C
|
||||
; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
|
||||
|
||||
; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled
|
||||
; as mthc1 has unmodeled side effects. This is an artifact of our backend.
|
||||
; Force the delay slot filler off to check that the sequence jr $ra; nop is
|
||||
; turned into jic 0, $ra.
|
||||
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
|
||||
|
||||
define void @ret_void() {
|
||||
; ALL-LABEL: ret_void:
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define i8 @ret_i8() {
|
||||
; ALL-LABEL: ret_i8:
|
||||
; ALL-DAG: addiu $2, $zero, 3
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i8 3
|
||||
}
|
||||
|
||||
define i16 @ret_i16_3() {
|
||||
; ALL-LABEL: ret_i16_3:
|
||||
; ALL-DAG: addiu $2, $zero, 3
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i16 3
|
||||
}
|
||||
|
||||
define i16 @ret_i16_256() {
|
||||
; ALL-LABEL: ret_i16_256:
|
||||
; ALL-DAG: addiu $2, $zero, 256
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i16 256
|
||||
}
|
||||
|
||||
define i16 @ret_i16_257() {
|
||||
; ALL-LABEL: ret_i16_257:
|
||||
; ALL-DAG: addiu $2, $zero, 257
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i16 257
|
||||
}
|
||||
|
||||
define i32 @ret_i32_257() {
|
||||
; ALL-LABEL: ret_i32_257:
|
||||
; ALL-DAG: addiu $2, $zero, 257
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i32 257
|
||||
}
|
||||
|
||||
define i32 @ret_i32_65536() {
|
||||
; ALL-LABEL: ret_i32_65536:
|
||||
; ALL-DAG: lui $2, 1
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i32 65536
|
||||
}
|
||||
|
||||
define i32 @ret_i32_65537() {
|
||||
; ALL-LABEL: ret_i32_65537:
|
||||
; ALL: lui $[[T0:[0-9]+]], 1
|
||||
; ALL-DAG: ori $2, $[[T0]], 1
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i32 65537
|
||||
}
|
||||
|
||||
define i64 @ret_i64_65537() {
|
||||
; ALL-LABEL: ret_i64_65537:
|
||||
; ALL: lui $[[T0:[0-9]+]], 1
|
||||
|
||||
; GPR32-DAG: ori $3, $[[T0]], 1
|
||||
; GPR32-DAG: addiu $2, $zero, 0
|
||||
|
||||
; GPR64-DAG: ori $2, $[[T0]], 1
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i64 65537
|
||||
}
|
||||
|
||||
define i64 @ret_i64_281479271677952() {
|
||||
; ALL-LABEL: ret_i64_281479271677952:
|
||||
; ALL-DAG: lui $[[T0:[0-9]+]], 1
|
||||
|
||||
; GPR32-DAG: ori $2, $[[T0]], 1
|
||||
; GPR32-DAG: addiu $3, $zero, 0
|
||||
|
||||
; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1
|
||||
; GPR64-DAG: dsll $2, $[[T1]], 32
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i64 281479271677952
|
||||
}
|
||||
|
||||
define i64 @ret_i64_281479271809026() {
|
||||
; ALL-LABEL: ret_i64_281479271809026:
|
||||
; GPR32-DAG: lui $[[T0:[0-9]+]], 1
|
||||
; GPR32-DAG: lui $[[T1:[0-9]+]], 2
|
||||
; GPR32-DAG: ori $2, $[[T0]], 1
|
||||
; GPR32-DAG: ori $3, $[[T1]], 2
|
||||
|
||||
; GPR64-DAG: ori $[[T0:[0-9]+]], $zero, 32769
|
||||
; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 16
|
||||
; GPR64-DAG: daddiu $[[T0:[0-9]+]], $[[T0]], -32767
|
||||
; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 17
|
||||
; GPR64-DAG: daddiu $2, $[[T1]], 2
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i64 281479271809026
|
||||
}
|
||||
|
||||
define float @ret_float_0x0() {
|
||||
; ALL-LABEL: ret_float_0x0:
|
||||
|
||||
; NO-MTHC1-DAG: mtc1 $zero, $f0
|
||||
|
||||
; MTHC1-DAG: mtc1 $zero, $f0
|
||||
|
||||
; DMTC-DAG: dmtc1 $zero, $f0
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret float 0x0000000000000000
|
||||
}
|
||||
|
||||
define float @ret_float_0x3() {
|
||||
; ALL-LABEL: ret_float_0x3:
|
||||
|
||||
; Use a constant pool
|
||||
; O32-DAG: lwc1 $f0, %lo($CPI
|
||||
; N64-DAG: lwc1 $f0, %got_ofst($CPI
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
|
||||
|
||||
; float constants are written as double constants
|
||||
ret float 0x36b8000000000000
|
||||
}
|
||||
|
||||
define double @ret_double_0x0() {
|
||||
; ALL-LABEL: ret_double_0x0:
|
||||
|
||||
; NO-MTHC1-DAG: mtc1 $zero, $f0
|
||||
; NO-MTHC1-DAG: mtc1 $zero, $f1
|
||||
|
||||
; MTHC1-DAG: mtc1 $zero, $f0
|
||||
; MTHC1-DAG: mthc1 $zero, $f0
|
||||
|
||||
; DMTC-DAG: dmtc1 $zero, $f0
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
|
||||
|
||||
ret double 0x0000000000000000
|
||||
}
|
||||
|
||||
define double @ret_double_0x3() {
|
||||
; ALL-LABEL: ret_double_0x3:
|
||||
|
||||
; Use a constant pool
|
||||
; O32-DAG: ldc1 $f0, %lo($CPI
|
||||
; N64-DAG: ldc1 $f0, %got_ofst($CPI
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
|
||||
|
||||
ret double 0x0000000000000003
|
||||
}
|
||||
192
external/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
vendored
192
external/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
vendored
@ -1,192 +0,0 @@
|
||||
; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,R6,GP32
|
||||
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,R6,64R6
|
||||
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MMR3,MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MMR6,MM32
|
||||
|
||||
define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_i1:
|
||||
|
||||
; NOT-R6: div $zero, $4, $5
|
||||
; NOT-R6: teq $5, $zero, 7
|
||||
; NOT-R6: mflo $[[T0:[0-9]+]]
|
||||
; FIXME: The andi/negu instructions are redundant since div is signed.
|
||||
; NOT-R6: andi $[[T0]], $[[T0]], 1
|
||||
; NOT-R6: negu $2, $[[T0]]
|
||||
|
||||
; R6: div $[[T0:[0-9]+]], $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
; FIXME: The andi/negu instructions are redundant since div is signed.
|
||||
; R6: andi $[[T0]], $[[T0]], 1
|
||||
; R6: negu $2, $[[T0]]
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $[[T0:[0-9]+]]
|
||||
; MMR3: andi16 $[[T0]], $[[T0]], 1
|
||||
; MMR3: li16 $[[T1:[0-9]+]], 0
|
||||
; MMR3: subu16 $2, $[[T1]], $[[T0]]
|
||||
|
||||
; MMR6: div $[[T0:[0-9]+]], $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
; MMR6: andi16 $[[T0]], $[[T0]], 1
|
||||
; MMR6: li16 $[[T1:[0-9]+]], 0
|
||||
; MMR6: subu16 $2, $[[T1]], $[[T0]]
|
||||
|
||||
%r = sdiv i1 %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_i8:
|
||||
|
||||
; NOT-R2-R6: div $zero, $4, $5
|
||||
; NOT-R2-R6: teq $5, $zero, 7
|
||||
; NOT-R2-R6: mflo $[[T0:[0-9]+]]
|
||||
; FIXME: The sll/sra instructions are redundant since div is signed.
|
||||
; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24
|
||||
; NOT-R2-R6: sra $2, $[[T1]], 24
|
||||
|
||||
; R2-R5: div $zero, $4, $5
|
||||
; R2-R5: teq $5, $zero, 7
|
||||
; R2-R5: mflo $[[T0:[0-9]+]]
|
||||
; FIXME: This instruction is redundant.
|
||||
; R2-R5: seb $2, $[[T0]]
|
||||
|
||||
; R6: div $[[T0:[0-9]+]], $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
; FIXME: This instruction is redundant.
|
||||
; R6: seb $2, $[[T0]]
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $[[T0:[0-9]+]]
|
||||
; MMR3: seb $2, $[[T0]]
|
||||
|
||||
; MMR6: div $[[T0:[0-9]+]], $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
; MMR6: seb $2, $[[T0]]
|
||||
|
||||
%r = sdiv i8 %a, %b
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_i16:
|
||||
|
||||
; NOT-R2-R6: div $zero, $4, $5
|
||||
; NOT-R2-R6: teq $5, $zero, 7
|
||||
; NOT-R2-R6: mflo $[[T0:[0-9]+]]
|
||||
; FIXME: The sll/sra instructions are redundant since div is signed.
|
||||
; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16
|
||||
; NOT-R2-R6: sra $2, $[[T1]], 16
|
||||
|
||||
; R2-R5: div $zero, $4, $5
|
||||
; R2-R5: teq $5, $zero, 7
|
||||
; R2-R5: mflo $[[T0:[0-9]+]]
|
||||
; FIXME: This is instruction is redundant since div is signed.
|
||||
; R2-R5: seh $2, $[[T0]]
|
||||
|
||||
; R6: div $[[T0:[0-9]+]], $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
; FIXME: This is instruction is redundant since div is signed.
|
||||
; R6: seh $2, $[[T0]]
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $[[T0:[0-9]+]]
|
||||
; MMR3: seh $2, $[[T0]]
|
||||
|
||||
; MMR6: div $[[T0:[0-9]+]], $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
; MMR6: seh $2, $[[T0]]
|
||||
|
||||
%r = sdiv i16 %a, %b
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_i32:
|
||||
|
||||
; NOT-R6: div $zero, $4, $5
|
||||
; NOT-R6: teq $5, $zero, 7
|
||||
; NOT-R6: mflo $2
|
||||
|
||||
; R6: div $2, $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $2
|
||||
|
||||
; MMR6: div $2, $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
|
||||
%r = sdiv i32 %a, %b
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_i64:
|
||||
|
||||
; GP32: lw $25, %call16(__divdi3)($gp)
|
||||
|
||||
; GP64-NOT-R6: ddiv $zero, $4, $5
|
||||
; GP64-NOT-R6: teq $5, $zero, 7
|
||||
; GP64-NOT-R6: mflo $2
|
||||
|
||||
; 64R6: ddiv $2, $4, $5
|
||||
; 64R6: teq $5, $zero, 7
|
||||
|
||||
; MM32: lw $25, %call16(__divdi3)($2)
|
||||
|
||||
%r = sdiv i64 %a, %b
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_i128:
|
||||
|
||||
; GP32: lw $25, %call16(__divti3)($gp)
|
||||
|
||||
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
|
||||
; 64R6: ld $25, %call16(__divti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__divti3)($16)
|
||||
|
||||
%r = sdiv i128 %a, %b
|
||||
ret i128 %r
|
||||
}
|
||||
@ -1,364 +0,0 @@
|
||||
; RUN: llc < %s -march=mips -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,M2,M2-M3
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,SEL-32,32R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,M3,M2-M3
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,SEL-64,64R6
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MM32R3
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MM32R6,SEL-32
|
||||
|
||||
define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_double:
|
||||
|
||||
; M2: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: ldc1 $f0, 16($sp)
|
||||
; M2: jr $ra
|
||||
; M2: nop
|
||||
; M2: $[[BB0]]:
|
||||
; M2: mtc1 $7, $f0
|
||||
; M2: jr $ra
|
||||
; M2: mtc1 $6, $f1
|
||||
|
||||
; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
|
||||
; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
|
||||
; CMOV-32R2-R5: mthc1 $6, $[[F0]]
|
||||
; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV-32: ldc1 $f0, 16($sp)
|
||||
; CMOV-32: movn.d $f0, $[[F0]], $[[T0]]
|
||||
|
||||
; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
|
||||
; SEL-32: mthc1 $6, $[[F0]]
|
||||
; SEL-32: mtc1 $4, $f0
|
||||
; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
|
||||
; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
|
||||
|
||||
; M3: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M3: bnez $[[T0]], [[BB0:.LBB[0-9_]+]]
|
||||
; M3: nop
|
||||
; M3: mov.d $f13, $f14
|
||||
; M3: [[BB0]]:
|
||||
; M3: jr $ra
|
||||
; M3: mov.d $f0, $f13
|
||||
|
||||
; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV-64: movn.d $f14, $f13, $[[T0]]
|
||||
; CMOV-64: mov.d $f0, $f14
|
||||
|
||||
; SEL-64: mtc1 $4, $f0
|
||||
; SEL-64: sel.d $f0, $f14, $f13
|
||||
|
||||
; MM32R3: mtc1 $7, $[[F0:f[0-9]+]]
|
||||
; MM32R3: mthc1 $6, $[[F0]]
|
||||
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R3: ldc1 $f0, 16($sp)
|
||||
; MM32R3: movn.d $f0, $[[F0]], $[[T0]]
|
||||
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_i1_double_reordered(double %x, double %y,
|
||||
i1 signext %s) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_double_reordered:
|
||||
|
||||
; M2: lw $[[T0:[0-9]+]], 16($sp)
|
||||
; M2: andi $[[T1:[0-9]+]], $[[T0]], 1
|
||||
; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: lw $[[T0:[0-9]+]], 16($sp)
|
||||
; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1
|
||||
; CMOV-32: movn.d $f14, $f12, $[[T1]]
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: lw $[[T0:[0-9]+]], 16($sp)
|
||||
; SEL-32: mtc1 $[[T0]], $f0
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; M3: andi $[[T0:[0-9]+]], $6, 1
|
||||
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
|
||||
; M3: nop
|
||||
; M3: mov.d $f12, $f13
|
||||
; M3: [[BB0]]:
|
||||
; M3: jr $ra
|
||||
; M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
|
||||
; CMOV-64: movn.d $f13, $f12, $[[T0]]
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: mtc1 $6, $f0
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
|
||||
; MM32R3: lw $[[T0:[0-9]+]], 16($sp)
|
||||
; MM32R3: andi16 $[[T1:[0-9]+]], $[[T0:[0-9]+]], 1
|
||||
; MM32R3: movn.d $f14, $f12, $[[T1]]
|
||||
; MM32R3: mov.d $f0, $f14
|
||||
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_olt_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_olt_double:
|
||||
|
||||
; M2: c.olt.d $f12, $f14
|
||||
; M3: c.olt.d $f12, $f13
|
||||
; M2: bc1t [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.olt.d $f12, $f14
|
||||
; CMOV-32: movt.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.lt.d $f0, $f12, $f14
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.olt.d $f12, $f13
|
||||
; CMOV-64: movt.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.lt.d $f0, $f12, $f13
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.olt.d $f12, $f14
|
||||
; MM32R3: movt.d $f14, $f12, $fcc0
|
||||
; MM32R3: mov.d $f0, $f14
|
||||
|
||||
%s = fcmp olt double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_ole_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ole_double:
|
||||
|
||||
; M2: c.ole.d $f12, $f14
|
||||
; M3: c.ole.d $f12, $f13
|
||||
; M2: bc1t [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ole.d $f12, $f14
|
||||
; CMOV-32: movt.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.le.d $f0, $f12, $f14
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ole.d $f12, $f13
|
||||
; CMOV-64: movt.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.le.d $f0, $f12, $f13
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.ole.d $f12, $f14
|
||||
; MM32R3: movt.d $f14, $f12, $fcc0
|
||||
; MM32R3: mov.d $f0, $f14
|
||||
|
||||
%s = fcmp ole double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_ogt_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ogt_double:
|
||||
|
||||
; M2: c.ule.d $f12, $f14
|
||||
; M3: c.ule.d $f12, $f13
|
||||
; M2: bc1f [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ule.d $f12, $f14
|
||||
; CMOV-32: movf.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.lt.d $f0, $f14, $f12
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ule.d $f12, $f13
|
||||
; CMOV-64: movf.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.lt.d $f0, $f13, $f12
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.ule.d $f12, $f14
|
||||
; MM32R3: movf.d $f14, $f12, $fcc0
|
||||
; MM32R3: mov.d $f0, $f14
|
||||
|
||||
%s = fcmp ogt double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_oge_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oge_double:
|
||||
|
||||
; M2: c.ult.d $f12, $f14
|
||||
; M3: c.ult.d $f12, $f13
|
||||
; M2: bc1f [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ult.d $f12, $f14
|
||||
; CMOV-32: movf.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.le.d $f0, $f14, $f12
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ult.d $f12, $f13
|
||||
; CMOV-64: movf.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.le.d $f0, $f13, $f12
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.ult.d $f12, $f14
|
||||
; MM32R3: movf.d $f14, $f12, $fcc0
|
||||
; MM32R3: mov.d $f0, $f14
|
||||
|
||||
%s = fcmp oge double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_oeq_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oeq_double:
|
||||
|
||||
; M2: c.eq.d $f12, $f14
|
||||
; M3: c.eq.d $f12, $f13
|
||||
; M2: bc1t [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.eq.d $f12, $f14
|
||||
; CMOV-32: movt.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.eq.d $f0, $f12, $f14
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.eq.d $f12, $f13
|
||||
; CMOV-64: movt.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.eq.d $f0, $f12, $f13
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.eq.d $f12, $f14
|
||||
; MM32R3: movt.d $f14, $f12, $fcc0
|
||||
; MM32R3: mov.d $f0, $f14
|
||||
|
||||
%s = fcmp oeq double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_one_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_one_double:
|
||||
|
||||
; M2: c.ueq.d $f12, $f14
|
||||
; M3: c.ueq.d $f12, $f13
|
||||
; M2: bc1f [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ueq.d $f12, $f14
|
||||
; CMOV-32: movf.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.ueq.d $f0, $f12, $f14
|
||||
; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-32: not $[[T0]], $[[T0]]
|
||||
; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ueq.d $f12, $f13
|
||||
; CMOV-64: movf.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.ueq.d $f0, $f12, $f13
|
||||
; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-64: not $[[T0]], $[[T0]]
|
||||
; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.ueq.d $f12, $f14
|
||||
; MM32R3: movf.d $f14, $f12, $fcc0
|
||||
; MM32R3: mov.d $f0, $f14
|
||||
|
||||
%s = fcmp one double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
@ -1,343 +0,0 @@
|
||||
; RUN: llc < %s -march=mips -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,M2,M2-M3
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,SEL-32,32R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,M3,M2-M3
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,SEL-64,64R6
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MM32R3
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MM32R6,SEL-32
|
||||
|
||||
define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_float:
|
||||
|
||||
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: jr $ra
|
||||
; M2: mtc1 $6, $f0
|
||||
; M3: mov.s $f13, $f14
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2: mtc1 $5, $f0
|
||||
; M3: mov.s $f0, $f13
|
||||
|
||||
; CMOV-32: mtc1 $6, $f0
|
||||
; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV-32: mtc1 $5, $f1
|
||||
; CMOV-32: movn.s $f0, $f1, $[[T0]]
|
||||
|
||||
; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
|
||||
; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
|
||||
; SEL-32: mtc1 $4, $f0
|
||||
; SEL-32: sel.s $f0, $[[F1]], $[[F0]]
|
||||
|
||||
; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV-64: movn.s $f14, $f13, $[[T0]]
|
||||
; CMOV-64: mov.s $f0, $f14
|
||||
|
||||
; SEL-64: mtc1 $4, $f0
|
||||
; SEL-64: sel.s $f0, $f14, $f13
|
||||
|
||||
; MM32R3: mtc1 $6, $[[F0:f[0-9]+]]
|
||||
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
|
||||
; MM32R3: movn.s $f0, $[[F1]], $[[T0]]
|
||||
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_i1_float_reordered(float %x, float %y,
|
||||
i1 signext %s) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_float_reordered:
|
||||
|
||||
; M2-M3: andi $[[T0:[0-9]+]], $6, 1
|
||||
; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M3: mov.s $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
|
||||
; CMOV-32: movn.s $f14, $f12, $[[T0]]
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: mtc1 $6, $f0
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
|
||||
; CMOV-64: movn.s $f13, $f12, $[[T0]]
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: mtc1 $6, $f0
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
|
||||
; MM32R3: andi16 $[[T0:[0-9]+]], $6, 1
|
||||
; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]]
|
||||
; MM32R3: mov.s $f0, $[[F0]]
|
||||
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_olt_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_olt_float:
|
||||
|
||||
; M2: c.olt.s $f12, $f14
|
||||
; M3: c.olt.s $f12, $f13
|
||||
; M2: bc1t [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M3: mov.s $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.olt.s $f12, $f14
|
||||
; CMOV-32: movt.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.lt.s $f0, $f12, $f14
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.olt.s $f12, $f13
|
||||
; CMOV-64: movt.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.lt.s $f0, $f12, $f13
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.olt.s $f12, $f14
|
||||
; MM32R3: movt.s $f14, $f12, $fcc0
|
||||
; MM32R3: mov.s $f0, $f14
|
||||
|
||||
%s = fcmp olt float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_ole_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ole_float:
|
||||
|
||||
; M2: c.ole.s $f12, $f14
|
||||
; M3: c.ole.s $f12, $f13
|
||||
; M2: bc1t [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M3: mov.s $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.ole.s $f12, $f14
|
||||
; CMOV-32: movt.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.le.s $f0, $f12, $f14
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ole.s $f12, $f13
|
||||
; CMOV-64: movt.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.le.s $f0, $f12, $f13
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.ole.s $f12, $f14
|
||||
; MM32R3: movt.s $f14, $f12, $fcc0
|
||||
; MM32R3: mov.s $f0, $f14
|
||||
|
||||
%s = fcmp ole float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_ogt_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ogt_float:
|
||||
|
||||
; M2: c.ule.s $f12, $f14
|
||||
; M3: c.ule.s $f12, $f13
|
||||
; M2: bc1f [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M3: mov.s $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.ule.s $f12, $f14
|
||||
; CMOV-32: movf.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.lt.s $f0, $f14, $f12
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ule.s $f12, $f13
|
||||
; CMOV-64: movf.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.lt.s $f0, $f13, $f12
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.ule.s $f12, $f14
|
||||
; MM32R3: movf.s $f14, $f12, $fcc0
|
||||
; MM32R3: mov.s $f0, $f14
|
||||
|
||||
%s = fcmp ogt float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_oge_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oge_float:
|
||||
|
||||
; M2: c.ult.s $f12, $f14
|
||||
; M3: c.ult.s $f12, $f13
|
||||
; M2: bc1f [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M3: mov.s $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.ult.s $f12, $f14
|
||||
; CMOV-32: movf.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.le.s $f0, $f14, $f12
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ult.s $f12, $f13
|
||||
; CMOV-64: movf.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.le.s $f0, $f13, $f12
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.ult.s $f12, $f14
|
||||
; MM32R3: movf.s $f14, $f12, $fcc0
|
||||
; MM32R3: mov.s $f0, $f14
|
||||
|
||||
%s = fcmp oge float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_oeq_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oeq_float:
|
||||
|
||||
; M2: c.eq.s $f12, $f14
|
||||
; M3: c.eq.s $f12, $f13
|
||||
; M2: bc1t [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M3: mov.s $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.eq.s $f12, $f14
|
||||
; CMOV-32: movt.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.eq.s $f0, $f12, $f14
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.eq.s $f12, $f13
|
||||
; CMOV-64: movt.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.eq.s $f0, $f12, $f13
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.eq.s $f12, $f14
|
||||
; MM32R3: movt.s $f14, $f12, $fcc0
|
||||
; MM32R3: mov.s $f0, $f14
|
||||
|
||||
%s = fcmp oeq float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_one_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_one_float:
|
||||
|
||||
; M2: c.ueq.s $f12, $f14
|
||||
; M3: c.ueq.s $f12, $f13
|
||||
; M2: bc1f [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M3: mov.s $f12, $f13
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.ueq.s $f12, $f14
|
||||
; CMOV-32: movf.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.ueq.s $f0, $f12, $f14
|
||||
; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-32: not $[[T0]], $[[T0]]
|
||||
; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ueq.s $f12, $f13
|
||||
; CMOV-64: movf.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.ueq.s $f0, $f12, $f13
|
||||
; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-64: not $[[T0]], $[[T0]]
|
||||
; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
|
||||
; MM32R3: c.ueq.s $f12, $f14
|
||||
; MM32R3: movf.s $f14, $f12, $fcc0
|
||||
; MM32R3: mov.s $f0, $f14
|
||||
|
||||
%s = fcmp one float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
@ -1,273 +0,0 @@
|
||||
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,M2,M2-M3
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,SEL,SEL-32
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,M3,M2-M3
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,SEL,SEL-64
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MM32R3
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MMR6,MM32R6
|
||||
|
||||
define signext i1 @tst_select_i1_i1(i1 signext %s,
|
||||
i1 signext %x, i1 signext %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_i1:
|
||||
|
||||
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2-M3: move $5, $6
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: move $2, $5
|
||||
|
||||
; CMOV: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV: movn $6, $5, $[[T0]]
|
||||
; CMOV: move $2, $6
|
||||
|
||||
; SEL: andi $[[T0:[0-9]+]], $4, 1
|
||||
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
|
||||
; SEL: or $2, $[[T2]], $[[T1]]
|
||||
|
||||
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; MM32R3: move $2, $[[T1]]
|
||||
|
||||
; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
|
||||
; MMR6: or $2, $[[T2]], $[[T1]]
|
||||
|
||||
%r = select i1 %s, i1 %x, i1 %y
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define signext i8 @tst_select_i1_i8(i1 signext %s,
|
||||
i8 signext %x, i8 signext %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_i8:
|
||||
|
||||
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2-M3: move $5, $6
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: move $2, $5
|
||||
|
||||
; CMOV: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV: movn $6, $5, $[[T0]]
|
||||
; CMOV: move $2, $6
|
||||
|
||||
; SEL: andi $[[T0:[0-9]+]], $4, 1
|
||||
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
|
||||
; SEL: or $2, $[[T2]], $[[T1]]
|
||||
|
||||
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; MM32R3: move $2, $[[T1]]
|
||||
|
||||
; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
|
||||
; MMR6: or $2, $[[T2]], $[[T1]]
|
||||
|
||||
%r = select i1 %s, i8 %x, i8 %y
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
define signext i32 @tst_select_i1_i32(i1 signext %s,
|
||||
i32 signext %x, i32 signext %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_i32:
|
||||
|
||||
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
|
||||
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2-M3: move $5, $6
|
||||
; M2-M3: [[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: move $2, $5
|
||||
|
||||
; CMOV: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV: movn $6, $5, $[[T0]]
|
||||
; CMOV: move $2, $6
|
||||
|
||||
; SEL: andi $[[T0:[0-9]+]], $4, 1
|
||||
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
|
||||
; SEL: or $2, $[[T2]], $[[T1]]
|
||||
|
||||
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; MM32R3: move $2, $[[T1]]
|
||||
|
||||
; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
|
||||
; MMR6: or $2, $[[T2]], $[[T1]]
|
||||
|
||||
%r = select i1 %s, i32 %x, i32 %y
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define signext i64 @tst_select_i1_i64(i1 signext %s,
|
||||
i64 signext %x, i64 signext %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_i64:
|
||||
|
||||
; M2: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: lw $[[T1:[0-9]+]], 16($sp)
|
||||
; M2: $[[BB0]]:
|
||||
; FIXME: This branch is redundant
|
||||
; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: lw $[[T2:[0-9]+]], 20($sp)
|
||||
; M2: $[[BB1]]:
|
||||
; M2: move $2, $[[T1]]
|
||||
; M2: jr $ra
|
||||
; M2: move $3, $[[T2]]
|
||||
|
||||
; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV-32: lw $2, 16($sp)
|
||||
; CMOV-32: movn $2, $6, $[[T0]]
|
||||
; CMOV-32: lw $3, 20($sp)
|
||||
; CMOV-32: movn $3, $7, $[[T0]]
|
||||
|
||||
; SEL-32: andi $[[T0:[0-9]+]], $4, 1
|
||||
; SEL-32: lw $[[T1:[0-9]+]], 16($sp)
|
||||
; SEL-32: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]]
|
||||
; SEL-32: selnez $[[T3:[0-9]+]], $6, $[[T0]]
|
||||
; SEL-32: or $2, $[[T3]], $[[T2]]
|
||||
; SEL-32: lw $[[T4:[0-9]+]], 20($sp)
|
||||
; SEL-32: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
|
||||
; SEL-32: selnez $[[T6:[0-9]+]], $7, $[[T0]]
|
||||
; SEL-32: or $3, $[[T6]], $[[T5]]
|
||||
|
||||
; M3: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
|
||||
; M3: nop
|
||||
; M3: move $5, $6
|
||||
; M3: [[BB0]]:
|
||||
; M3: jr $ra
|
||||
; M3: move $2, $5
|
||||
|
||||
; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV-64: movn $6, $5, $[[T0]]
|
||||
; CMOV-64: move $2, $6
|
||||
|
||||
; SEL-64: andi $[[T0:[0-9]+]], $4, 1
|
||||
; FIXME: This shift is redundant
|
||||
; SEL-64: sll $[[T0]], $[[T0]], 0
|
||||
; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; SEL-64: selnez $[[T0]], $5, $[[T0]]
|
||||
; SEL-64: or $2, $[[T0]], $[[T1]]
|
||||
|
||||
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R3: lw $2, 16($sp)
|
||||
; MM32R3: movn $2, $6, $[[T0]]
|
||||
; MM32R3: lw $3, 20($sp)
|
||||
; MM32R3: movn $3, $7, $[[T0]]
|
||||
|
||||
; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R6: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; MM32R6: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
|
||||
; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; MM32R6: or $2, $[[T1]], $[[T3]]
|
||||
; MM32R6: lw $[[T4:[0-9]+]], 20($sp)
|
||||
; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
|
||||
; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
|
||||
; MM32R6: or $3, $[[T6]], $[[T5]]
|
||||
|
||||
%r = select i1 %s, i64 %x, i64 %y
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i8* @tst_select_word_cst(i8* %a, i8* %b) {
|
||||
; ALL-LABEL: tst_select_word_cst:
|
||||
|
||||
; M2: addiu $[[T0:[0-9]+]], $zero, -1
|
||||
; M2: xor $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
|
||||
; M2: bnez $[[T2]], [[BB0:\$BB[0-9_]+]]
|
||||
; M2: addiu $2, $zero, 0
|
||||
; M2: move $2, $4
|
||||
; M2: [[BB0]]:
|
||||
; M2: jr $ra
|
||||
|
||||
; M3: daddiu $[[T0:[0-9]+]], $zero, -1
|
||||
; M3: xor $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
|
||||
; M3: bnez $[[T2]], [[BB0:\.LBB[0-9_]+]]
|
||||
; M3: daddiu $2, $zero, 0
|
||||
; M3: move $2, $4
|
||||
; M3: [[BB0]]:
|
||||
; M3: jr $ra
|
||||
|
||||
; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1
|
||||
; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]]
|
||||
; CMOV-32: jr $ra
|
||||
; CMOV-32: move $2, $[[T2]]
|
||||
|
||||
; SEL-32: addiu $[[T0:[0-9]+]], $zero, -1
|
||||
; SEL-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; SEL-32: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
|
||||
; SEL-32: jr $ra
|
||||
; SEL-32: seleqz $2, $4, $[[T2]]
|
||||
|
||||
; CMOV-64: daddiu $[[T0:[0-9]+]], $zero, -1
|
||||
; CMOV-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; CMOV-64: movn $[[T2:[0-9]+]], $zero, $[[T1]]
|
||||
; CMOV-64: move $2, $[[T2]]
|
||||
|
||||
; SEL-64: daddiu $[[T0:[0-9]+]], $zero, -1
|
||||
; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
|
||||
; FIXME: This shift is redundant.
|
||||
; SEL-64: sll $[[T2]], $[[T2]], 0
|
||||
; SEL-64: seleqz $2, $4, $[[T2]]
|
||||
|
||||
; MM32R3: li16 $[[T0:[0-9]+]], -1
|
||||
; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; MM32R3: li16 $[[T2:[0-9]+]], 0
|
||||
; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; MM32R3: move $2, $[[T3]]
|
||||
|
||||
; MM32R6: li16 $[[T0:[0-9]+]], -1
|
||||
; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]]
|
||||
; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
|
||||
; MM32R6: seleqz $2, $4, $[[T2]]
|
||||
|
||||
%cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
|
||||
%r = select i1 %cmp, i8* %a, i8* null
|
||||
ret i8* %r
|
||||
}
|
||||
1040
external/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
vendored
1040
external/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
vendored
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Reference in New Issue
Block a user