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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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24
external/llvm/test/CodeGen/Hexagon/bit-validate-reg.ll vendored
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@ -1,24 +0,0 @@
; RUN: llc -march=hexagon -hexbit-extract=0 < %s | FileCheck %s
; Make sure we don't generate zxtb to transfer a predicate register into
; a general purpose register.
; CHECK: r0 = p0
; CHECK-NOT: zxtb(p
; CHECK-NOT: and(p
; CHECK-NOT: extract(p
; CHECK-NOT: extractu(p
target triple = "hexagon"
; Function Attrs: nounwind
define i32 @fred() local_unnamed_addr #0 {
entry:
%0 = tail call i32 @llvm.hexagon.C4.and.and(i32 undef, i32 undef, i32 undef)
ret i32 %0
}
declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) #1
attributes #0 = { nounwind "target-cpu"="hexagonv5" }
attributes #1 = { nounwind readnone }