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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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55
external/llvm/test/CodeGen/ARM/msr-it-block.ll vendored
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@ -1,55 +0,0 @@
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=V6M --check-prefix=CHECK
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=V7M --check-prefix=CHECK
; RUN: llc < %s -mtriple=thumbv7a-none-eabi | FileCheck %s --check-prefix=V7A --check-prefix=CHECK
; RUN: llc < %s -mtriple=armv7a-none-eabi | FileCheck %s --check-prefix=V7A --check-prefix=CHECK
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7a-arm-none-eabi"
define void @test_const(i32 %val) {
; CHECK-LABEL: test_const:
entry:
%cmp = icmp eq i32 %val, 0
br i1 %cmp, label %write_reg, label %exit
write_reg:
tail call void @llvm.write_register.i32(metadata !0, i32 0)
tail call void @llvm.write_register.i32(metadata !0, i32 0)
; V6M: msr apsr, {{r[0-9]+}}
; V6M: msr apsr, {{r[0-9]+}}
; V7M: msr apsr_nzcvq, {{r[0-9]+}}
; V7M: msr apsr_nzcvq, {{r[0-9]+}}
; V7A: msr APSR_nzcvq, {{r[0-9]+}}
; V7A: msr APSR_nzcvq, {{r[0-9]+}}
br label %exit
exit:
ret void
}
define void @test_var(i32 %val, i32 %apsr) {
; CHECK-LABEL: test_var:
entry:
%cmp = icmp eq i32 %val, 0
br i1 %cmp, label %write_reg, label %exit
write_reg:
tail call void @llvm.write_register.i32(metadata !0, i32 %apsr)
tail call void @llvm.write_register.i32(metadata !0, i32 %apsr)
; V6M: msr apsr, {{r[0-9]+}}
; V6M: msr apsr, {{r[0-9]+}}
; V7M: msr apsr_nzcvq, {{r[0-9]+}}
; V7M: msr apsr_nzcvq, {{r[0-9]+}}
; V7A: msr APSR_nzcvq, {{r[0-9]+}}
; V7A: msr APSR_nzcvq, {{r[0-9]+}}
br label %exit
exit:
ret void
}
declare void @llvm.write_register.i32(metadata, i32)
!0 = !{!"apsr"}