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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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30
external/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll vendored
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@ -1,30 +0,0 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
; We need second, post-ra scheduling to have VLDM instruction combined from single-loads
; CHECK: ********** MI Scheduling **********
; CHECK: VLDMDIA
; CHECK: rdefs left
; CHECK-NEXT: Latency : 6
; CHECK: Successors:
; CHECK: Data
; CHECK-SAME: Latency=5
; CHECK-NEXT: Data
; CHECK-SAME: Latency=5
; CHECK-NEXT: Data
; CHECK-SAME: Latency=6
define double @foo(double* %a) nounwind optsize {
entry:
%b = getelementptr double, double* %a, i32 1
%c = getelementptr double, double* %a, i32 2
%0 = load double, double* %a, align 4
%1 = load double, double* %b, align 4
%2 = load double, double* %c, align 4
%mul1 = fmul double %0, %1
%mul2 = fmul double %mul1, %2
ret double %mul2
}