Imported Upstream version 5.18.0.167

Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a

external/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll

@@ -1,30 +0,0 @@
-; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NOV4T
-; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V4T
-; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V5T
-
-define arm_aapcscc void @test_indirect_call(void() *%fptr) {
-; CHECK-LABEL: name: test_indirect_call
-; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0
-; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
-; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-entry:
-  notail call arm_aapcscc void %fptr()
-  ret void
-}
-
-declare arm_aapcscc void @call_target()
-
-define arm_aapcscc void @test_direct_call() {
-; CHECK-LABEL: name: test_direct_call
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-entry:
-  notail call arm_aapcscc void @call_target()
-  ret void
-}

external/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll

@@ -1,112 +0,0 @@
-; RUN: llc -mtriple arm-gnueabi -mattr=+v6t2,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
-; RUN: llc -mtriple arm-gnueabi -mattr=+v6t2,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-AEABI
-; RUN: llc -mtriple arm-gnu -mattr=+v6t2,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
-; RUN: llc -mtriple arm-gnu -mattr=+v6t2,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-DEFAULT
-
-define arm_aapcscc i32 @test_sdiv_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: test_sdiv_i32:
-; HWDIV: sdiv
-; SOFT-AEABI: bl __aeabi_idiv
-; SOFT-DEFAULT: bl __divsi3
-  %r = sdiv i32 %a, %b
-  ret i32 %r
-}
-
-define arm_aapcscc i32 @test_udiv_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: test_udiv_i32:
-; HWDIV: udiv
-; SOFT-AEABI: bl __aeabi_uidiv
-; SOFT-DEFAULT: bl __udivsi3
-  %r = udiv i32 %a, %b
-  ret i32 %r
-}
-
-define arm_aapcscc i16 @test_sdiv_i16(i16 %a, i16 %b) {
-; CHECK-LABEL: test_sdiv_i16:
-; HWDIV: sdiv
-; SOFT-AEABI: bl __aeabi_idiv
-; SOFT-DEFAULT: bl __divsi3
-  %r = sdiv i16 %a, %b
-  ret i16 %r
-}
-
-define arm_aapcscc i16 @test_udiv_i16(i16 %a, i16 %b) {
-; CHECK-LABEL: test_udiv_i16:
-; HWDIV: udiv
-; SOFT-AEABI: bl __aeabi_uidiv
-; SOFT-DEFAULT: bl __udivsi3
-  %r = udiv i16 %a, %b
-  ret i16 %r
-}
-
-define arm_aapcscc i8 @test_sdiv_i8(i8 %a, i8 %b) {
-; CHECK-LABEL: test_sdiv_i8:
-; HWDIV: sdiv
-; SOFT-AEABI: bl __aeabi_idiv
-; SOFT-DEFAULT: bl __divsi3
-  %r = sdiv i8 %a, %b
-  ret i8 %r
-}
-
-define arm_aapcscc i8 @test_udiv_i8(i8 %a, i8 %b) {
-; CHECK-LABEL: test_udiv_i8:
-; HWDIV: udiv
-; SOFT-AEABI: bl __aeabi_uidiv
-; SOFT-DEFAULT: bl __udivsi3
-  %r = udiv i8 %a, %b
-  ret i8 %r
-}
-
-define arm_aapcscc i32 @test_srem_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: test_srem_i32:
-; HWDIV: sdiv
-; SOFT-AEABI: bl __aeabi_idivmod
-; SOFT-DEFAULT: bl __modsi3
-  %r = srem i32 %x, %y
-  ret i32 %r
-}
-
-define arm_aapcscc i32 @test_urem_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: test_urem_i32:
-; HWDIV: udiv
-; SOFT-AEABI: bl __aeabi_uidivmod
-; SOFT-DEFAULT: bl __umodsi3
-  %r = urem i32 %x, %y
-  ret i32 %r
-}
-
-define arm_aapcscc i16 @test_srem_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: test_srem_i16:
-; HWDIV: sdiv
-; SOFT-AEABI: bl __aeabi_idivmod
-; SOFT-DEFAULT: bl __modsi3
-  %r = srem i16 %x, %y
-  ret i16 %r
-}
-
-define arm_aapcscc i16 @test_urem_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: test_urem_i16:
-; HWDIV: udiv
-; SOFT-AEABI: bl __aeabi_uidivmod
-; SOFT-DEFAULT: bl __umodsi3
-  %r = urem i16 %x, %y
-  ret i16 %r
-}
-
-define arm_aapcscc i8 @test_srem_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: test_srem_i8:
-; HWDIV: sdiv
-; SOFT-AEABI: bl __aeabi_idivmod
-; SOFT-DEFAULT: bl __modsi3
-  %r = srem i8 %x, %y
-  ret i8 %r
-}
-
-define arm_aapcscc i8 @test_urem_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: test_urem_i8:
-; HWDIV: udiv
-; SOFT-AEABI: bl __aeabi_uidivmod
-; SOFT-DEFAULT: bl __umodsi3
-  %r = urem i8 %x, %y
-  ret i8 %r
-}

external/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll

@@ -1,98 +0,0 @@
-; RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD
-; RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-AEABI
-; RUN: llc -mtriple arm-linux-gnu- -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-DEFAULT
-
-define arm_aapcscc float @test_frem_float(float %x, float %y) {
-; CHECK-LABEL: test_frem_float:
-; CHECK: bl fmodf
-  %r = frem float %x, %y
-  ret float %r
-}
-
-define arm_aapcscc double @test_frem_double(double %x, double %y) {
-; CHECK-LABEL: test_frem_double:
-; CHECK: bl fmod
-  %r = frem double %x, %y
-  ret double %r
-}
-
-declare float @llvm.pow.f32(float %x, float %y)
-define arm_aapcscc float @test_fpow_float(float %x, float %y) {
-; CHECK-LABEL: test_fpow_float:
-; CHECK: bl powf
-  %r = call float @llvm.pow.f32(float %x, float %y)
-  ret float %r
-}
-
-declare double @llvm.pow.f64(double %x, double %y)
-define arm_aapcscc double @test_fpow_double(double %x, double %y) {
-; CHECK-LABEL: test_fpow_double:
-; CHECK: bl pow
-  %r = call double @llvm.pow.f64(double %x, double %y)
-  ret double %r
-}
-
-define arm_aapcscc float @test_add_float(float %x, float %y) {
-; CHECK-LABEL: test_add_float:
-; HARD: vadd.f32
-; SOFT-AEABI: bl __aeabi_fadd
-; SOFT-DEFAULT: bl __addsf3
-  %r = fadd float %x, %y
-  ret float %r
-}
-
-define arm_aapcscc double @test_add_double(double %x, double %y) {
-; CHECK-LABEL: test_add_double:
-; HARD: vadd.f64
-; SOFT-AEABI: bl __aeabi_dadd
-; SOFT-DEFAULT: bl __adddf3
-  %r = fadd double %x, %y
-  ret double %r
-}
-
-define arm_aapcscc float @test_sub_float(float %x, float %y) {
-; CHECK-LABEL: test_sub_float:
-; HARD: vsub.f32
-; SOFT-AEABI: bl __aeabi_fsub
-; SOFT-DEFAULT: bl __subsf3
-  %r = fsub float %x, %y
-  ret float %r
-}
-
-define arm_aapcscc double @test_sub_double(double %x, double %y) {
-; CHECK-LABEL: test_sub_double:
-; HARD: vsub.f64
-; SOFT-AEABI: bl __aeabi_dsub
-; SOFT-DEFAULT: bl __subdf3
-  %r = fsub double %x, %y
-  ret double %r
-}
-define arm_aapcs_vfpcc i32 @test_cmp_float_ogt(float %x, float %y) {
-; CHECK-LABEL: test_cmp_float_ogt
-; HARD: vcmp.f32
-; HARD: vmrs APSR_nzcv, fpscr
-; HARD-NEXT: movgt
-; SOFT-AEABI: bl __aeabi_fcmpgt
-; SOFT-DEFAULT: bl __gtsf2
-entry:
-  %v = fcmp ogt float %x, %y
-  %r = zext i1 %v to i32
-  ret i32 %r
-}
-
-define arm_aapcs_vfpcc i32 @test_cmp_float_one(float %x, float %y) {
-; CHECK-LABEL: test_cmp_float_one
-; HARD: vcmp.f32
-; HARD: vmrs APSR_nzcv, fpscr
-; HARD: movgt
-; HARD-NOT: vcmp
-; HARD: movmi
-; SOFT-AEABI-DAG: bl __aeabi_fcmpgt
-; SOFT-AEABI-DAG: bl __aeabi_fcmplt
-; SOFT-DEFAULT-DAG: bl __gtsf2
-; SOFT-DEFAULT-DAG: bl __ltsf2
-entry:
-  %v = fcmp one float %x, %y
-  %r = zext i1 %v to i32
-  ret i32 %r
-}

external/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-pic.ll

@@ -1,114 +0,0 @@
-; RUN: llc -mtriple armv7-linux -relocation-model=pic -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,ELF
-; RUN: llc -mtriple armv7-linux -relocation-model=pic -mattr=+no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,ELF
-; RUN: llc -mtriple armv7-darwin -relocation-model=pic -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,DARWIN,DARWIN-MOVT
-; RUN: llc -mtriple armv7-darwin -relocation-model=pic -mattr=+no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,DARWIN,DARWIN-NOMOVT
-
-@internal_global = internal global i32 42
-define i32 @test_internal_global() {
-; CHECK-LABEL: test_internal_global:
-; ELF: ldr [[OFFSET:r[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; ELF: [[ANCHOR:.L[[:alnum:]_]+]]:
-; DARWIN-NOMOVT: ldr [[OFFSET:r[0-9]+]], [[LABEL:L[[:alnum:]_]+]]
-; DARWIN-MOVT: movw [[OFFSET:r[0-9]+]], :lower16:(_internal_global-([[ANCHOR:L[[:alnum:]_]+]]+8))
-; DARWIN-MOVT-NEXT: movt [[OFFSET]], :upper16:(_internal_global-([[ANCHOR]]+8))
-; DARWIN: [[ANCHOR:L[[:alnum:]_]+]]:
-; CHECK-NEXT: add r[[ADDR:[0-9]+]], pc, [[OFFSET]]
-; CHECK-NEXT: ldr r0, [r[[ADDR]]]
-; CHECK-NEXT: bx lr
-; ELF: [[LABEL]]:
-; ELF-NEXT: .long internal_global-([[ANCHOR]]+8)
-; DARWIN-NOMOVT: [[LABEL]]:
-; DARWIN-NOMOVT-NEXT: .long _internal_global-([[ANCHOR]]+8)
-; DARWIN-MOVT-NOT: .long _internal_global
-
-entry:
-  %v = load i32, i32* @internal_global
-  ret i32 %v
-}
-
-@external_global = external global i32
-define i32 @test_external_global() {
-; CHECK-LABEL: test_external_global:
-; ELF: ldr [[OFFSET:r[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; ELF: [[ANCHOR:.L[[:alnum:]_]+]]:
-; ELF-NEXT: ldr r[[ADDR:[0-9]+]], [pc, [[OFFSET]]]
-; DARWIN-NOMOVT: ldr [[OFFSET:r[0-9]+]], [[LABEL:L[[:alnum:]_]+]]
-; DARWIN-MOVT: movw [[OFFSET:r[0-9]+]], :lower16:(L_external_global$non_lazy_ptr-([[ANCHOR:L[[:alnum:]_]+]]+8))
-; DARWIN-MOVT: movt [[OFFSET]], :upper16:(L_external_global$non_lazy_ptr-([[ANCHOR]]+8))
-; DARWIN: [[ANCHOR:L[[:alnum:]_]+]]:
-; DARWIN: ldr r[[ADDR:[0-9]+]], [pc, [[OFFSET]]]
-; CHECK-NEXT: ldr r0, [r[[ADDR]]]
-; CHECK-NEXT: bx lr
-; ELF: [[LABEL]]:
-; ELF: [[TMPLABEL:.L[[:alnum:]_]+]]:
-; ELF: .long external_global(GOT_PREL)-(([[ANCHOR]]+8)-[[TMPLABEL]])
-; DARWIN-NOMOVT: [[LABEL]]:
-; DARWIN-NOMOVT: .long L_external_global$non_lazy_ptr-([[ANCHOR]]+8)
-; DARWIN-NOMOVT-NOT: .long L_external_global
-entry:
-  %v = load i32, i32* @external_global
-  ret i32 %v
-}
-
-@internal_constant = internal constant i32 42
-define i32 @test_internal_constant() {
-; CHECK-LABEL: test_internal_constant:
-; ELF: ldr [[OFFSET:r[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; ELF: [[ANCHOR:.L[[:alnum:]_]+]]:
-; DARWIN-NOMOVT: ldr [[OFFSET:r[0-9]+]], [[LABEL:L[[:alnum:]_]+]]
-; DARWIN-MOVT: movw [[OFFSET:r[0-9]+]], :lower16:(_internal_constant-([[ANCHOR:L[[:alnum:]_]+]]+8))
-; DARWIN-MOVT-NEXT: movt [[OFFSET]], :upper16:(_internal_constant-([[ANCHOR]]+8))
-; DARWIN: [[ANCHOR:L[[:alnum:]_]+]]:
-; CHECK-NEXT: add r[[ADDR:[0-9]+]], pc, [[OFFSET]]
-; CHECK-NEXT: ldr r0, [r[[ADDR]]]
-; CHECK-NEXT: bx lr
-; ELF: [[LABEL]]:
-; ELF-NEXT: .long internal_constant-([[ANCHOR]]+8)
-; DARWIN-NOMOVT: [[LABEL]]:
-; DARWIN-NOMOVT-NEXT: .long _internal_constant-([[ANCHOR]]+8)
-; DARWIN-MOVT-NOT: .long _internal_constant
-
-entry:
-  %v = load i32, i32* @internal_constant
-  ret i32 %v
-}
-
-@external_constant = external constant i32
-define i32 @test_external_constant() {
-; CHECK-LABEL: test_external_constant:
-; ELF: ldr [[OFFSET:r[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; ELF: [[ANCHOR:.L[[:alnum:]_]+]]:
-; ELF-NEXT: ldr r[[ADDR:[0-9]+]], [pc, [[OFFSET]]]
-; DARWIN-NOMOVT: ldr [[OFFSET:r[0-9]+]], [[LABEL:L[[:alnum:]_]+]]
-; DARWIN-MOVT: movw [[OFFSET:r[0-9]+]], :lower16:(L_external_constant$non_lazy_ptr-([[ANCHOR:L[[:alnum:]_]+]]+8))
-; DARWIN-MOVT: movt [[OFFSET]], :upper16:(L_external_constant$non_lazy_ptr-([[ANCHOR]]+8))
-; DARWIN: [[ANCHOR:L[[:alnum:]_]+]]:
-; DARWIN: ldr r[[ADDR:[0-9]+]], [pc, [[OFFSET]]]
-; CHECK-NEXT: ldr r0, [r[[ADDR]]]
-; CHECK-NEXT: bx lr
-; ELF: [[LABEL]]:
-; ELF: [[TMPLABEL:.L[[:alnum:]_]+]]:
-; ELF: .long external_constant(GOT_PREL)-(([[ANCHOR]]+8)-[[TMPLABEL]])
-; DARWIN-NOMOVT: [[LABEL]]:
-; DARWIN-NOMOVT: .long L_external_constant$non_lazy_ptr-([[ANCHOR]]+8)
-; DARWIN-NOMOVT-NOT: .long L_external_constant
-entry:
-  %v = load i32, i32* @external_constant
-  ret i32 %v
-}
-
-; ELF: internal_global:
-; DARWIN: _internal_global:
-; CHECK: .long 42
-; ELF: .size internal_global, 4
-
-; ELF: internal_constant:
-; DARWIN: _internal_constant:
-; CHECK: .long 42
-; ELF: .size internal_constant, 4
-
-; DARWIN-DAG: L_external_global$non_lazy_ptr:
-; DARWIN-DAG: .indirect_symbol _external_global
-
-; DARWIN-DAG: L_external_constant$non_lazy_ptr:
-; DARWIN-DAG: .indirect_symbol _external_constant

external/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-ropi-rwpi.ll

@@ -1,122 +0,0 @@
-; RUN: llc -mtriple armv7-linux -relocation-model=ropi -mattr=-no-movt,+v8m -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,RW-DEFAULT-MOVT,RW-DEFAULT,ROPI-MOVT,ROPI
-; RUN: llc -mtriple armv7-linux -relocation-model=ropi -mattr=+no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,RW-DEFAULT-NOMOVT,RW-DEFAULT,ROPI-NOMOVT,ROPI
-; RUN: llc -mtriple armv7-linux -relocation-model=rwpi -mattr=-no-movt,+v8m -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,RO-DEFAULT-MOVT,RO-DEFAULT,RWPI-MOVT,RWPI
-; RUN: llc -mtriple armv7-linux -relocation-model=rwpi -mattr=+no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,RO-DEFAULT-NOMOVT,RO-DEFAULT,RWPI-NOMOVT,RWPI
-; RUN: llc -mtriple armv7-linux -relocation-model=ropi-rwpi -mattr=-no-movt,+v8m -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,ROPI-MOVT,ROPI,RWPI-MOVT,RWPI
-; RUN: llc -mtriple armv7-linux -relocation-model=ropi-rwpi -mattr=+no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,ROPI-NOMOVT,ROPI,RWPI-NOMOVT,RWPI
-
-@internal_global = internal global i32 42
-define i32 @test_internal_global() {
-; CHECK-LABEL: test_internal_global:
-; RW-DEFAULT-MOVT: movw r[[ADDR:[0-9]+]], :lower16:internal_global
-; RW-DEFAULT-MOVT-NEXT: movt r[[ADDR]], :upper16:internal_global
-; RW-DEFAULT-NOMOVT: ldr r[[ADDR:[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; RW-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
-; RW-DEFAULT-NEXT: bx lr
-; RW-DEFAULT-NOMOVT: [[LABEL]]:
-; RW-DEFAULT-NOMOVT-NEXT: .long internal_global
-
-; RWPI-MOVT: movw [[OFFSET:r[0-9]+]], :lower16:internal_global(sbrel)
-; RWPI-MOVT-NEXT: movt [[OFFSET]], :upper16:internal_global(sbrel)
-; RWPI-NOMOVT: ldr [[OFFSET:r[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; RWPI-NEXT: add r[[ADDR:[0-9]+]], r9, [[OFFSET]]
-; RWPI-NEXT: ldr r0, [r[[ADDR]]]
-; RWPI-NEXT: bx lr
-; RWPI-NOMOVT: [[LABEL]]:
-; RWPI-NOMOVT-NEXT: .long internal_global(sbrel)
-entry:
-  %v = load i32, i32* @internal_global
-  ret i32 %v
-}
-
-@external_global = external global i32
-define i32 @test_external_global() {
-; CHECK-LABEL: test_external_global:
-; RW-DEFAULT-MOVT: movw r[[ADDR:[0-9]+]], :lower16:external_global
-; RW-DEFAULT-MOVT-NEXT: movt r[[ADDR]], :upper16:external_global
-; RW-DEFAULT-NOMOVT: ldr r[[ADDR:[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; RW-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
-; RW-DEFAULT-NEXT: bx lr
-; RW-DEFAULT-NOMOVT: [[LABEL]]:
-; RW-DEFAULT-NOMOVT: .long external_global
-
-; RWPI-MOVT: movw [[OFFSET:r[0-9]+]], :lower16:external_global(sbrel)
-; RWPI-MOVT-NEXT: movt [[OFFSET]], :upper16:external_global(sbrel)
-; RWPI-NOMOVT: ldr [[OFFSET:r[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; RWPI-NEXT: add r[[ADDR:[0-9]+]], r9, [[OFFSET]]
-; RWPI-NEXT: ldr r0, [r[[ADDR]]]
-; RWPI-NEXT: bx lr
-; RWPI-NOMOVT: [[LABEL]]:
-; RWPI-NOMOVT-NEXT: .long external_global(sbrel)
-entry:
-  %v = load i32, i32* @external_global
-  ret i32 %v
-}
-
-@internal_constant = internal constant i32 42
-define i32 @test_internal_constant() {
-; CHECK-LABEL: test_internal_constant:
-; ROPI-MOVT: movw [[OFFSET:r[0-9]+]], :lower16:(internal_constant-([[ANCHOR:.L[[:alnum:]_]+]]+8)
-; ROPI-MOVT-NEXT: movt [[OFFSET]], :upper16:(internal_constant-([[ANCHOR]]+8)
-; ROPI-MOVT-NEXT: [[ANCHOR]]:
-; ROPI-NOMOVT: ldr [[OFFSET:r[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; ROPI-NOMOVT-NEXT: [[ANCHOR:.L[[:alnum:]_]+]]:
-; ROPI-NEXT: add r[[ADDR:[0-9]+]], pc, [[OFFSET]]
-; ROPI-NEXT: ldr r0, [r[[ADDR]]]
-; ROPI-NEXT: bx lr
-; ROPI-NOMOVT: [[LABEL]]:
-; ROPI-NOMOVT-NEXT: .long internal_constant-([[ANCHOR]]+8)
-
-; RO-DEFAULT-MOVT: movw r[[ADDR:[0-9]+]], :lower16:internal_constant
-; RO-DEFAULT-MOVT-NEXT: movt r[[ADDR]], :upper16:internal_constant
-; RO-DEFAULT-NOMOVT: ldr r[[ADDR:[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; RO-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
-; RO-DEFAULT-NEXT: bx lr
-; RO-DEFAULT-NOMOVT: [[LABEL]]:
-; RO-DEFAULT-NOMOVT-NEXT: .long internal_constant
-entry:
-  %v = load i32, i32* @internal_constant
-  ret i32 %v
-}
-
-@external_constant = external constant i32
-define i32 @test_external_constant() {
-; CHECK-LABEL: test_external_constant:
-; ROPI-MOVT: movw [[OFFSET:r[0-9]+]], :lower16:(external_constant-([[ANCHOR:.L[[:alnum:]_]+]]+8)
-; ROPI-MOVT-NEXT: movt [[OFFSET]], :upper16:(external_constant-([[ANCHOR]]+8)
-; ROPI-MOVT-NEXT: [[ANCHOR]]:
-; ROPI-NOMOVT: ldr [[OFFSET:r[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; ROPI-NOMOVT-NEXT: [[ANCHOR:.L[[:alnum:]_]+]]:
-; ROPI-NEXT: add r[[ADDR:[0-9]+]], pc, [[OFFSET]]
-; ROPI-NEXT: ldr r0, [r[[ADDR]]]
-; ROPI-NEXT: bx lr
-; ROPI-NOMOVT: [[LABEL]]:
-; ROPI-NOMOVT-NEXT: .long external_constant-([[ANCHOR]]+8)
-
-; RO-DEFAULT-MOVT: movw r[[ADDR:[0-9]+]], :lower16:external_constant
-; RO-DEFAULT-MOVT-NEXT: movt r[[ADDR]], :upper16:external_constant
-; RO-DEFAULT-NOMOVT: ldr r[[ADDR:[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; RO-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
-; RO-DEFAULT-NEXT: bx lr
-; RO-DEFAULT-NOMOVT: [[LABEL]]:
-; RO-DEFAULT-NOMOVT: .long external_constant
-entry:
-  %v = load i32, i32* @external_constant
-  ret i32 %v
-}
-
-; RW-DEFAULT-NOMOVT: internal_global:
-; RW-DEFAULT-NOMOVT: .long 42
-; RW-DEFAULT-NOMOVT: .size internal_global, 4
-
-; RWPI-NOMOVT: internal_global:
-; RWPI-NOMOVT: .long 42
-; RWPI-NOMOVT: .size internal_global, 4
-
-; ROPI-NOMOVT: internal_constant:
-; ROPI-NOMOVT: .long 42
-; ROPI-NOMOVT: .size internal_constant, 4
-
-; RO-DEFAULT-NOMOVT: internal_constant:
-; RO-DEFAULT-NOMOVT: .long 42
-; RO-DEFAULT-NOMOVT: .size internal_constant, 4

external/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-static.ll

@@ -1,50 +0,0 @@
-; RUN: llc -mtriple armv7-linux -relocation-model=static -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,ELF,ELF-MOVT
-; RUN: llc -mtriple armv7-linux -relocation-model=static -mattr=+no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,ELF,ELF-NOMOVT
-; RUN: llc -mtriple armv7-darwin -relocation-model=static -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,DARWIN,DARWIN-MOVT
-; RUN: llc -mtriple armv7-darwin -relocation-model=static -mattr=+no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,DARWIN,DARWIN-NOMOVT
-
-@internal_global = internal global i32 42
-define i32 @test_internal_global() {
-; CHECK-LABEL: test_internal_global:
-; ELF-MOVT: movw r[[ADDR:[0-9]+]], :lower16:internal_global
-; ELF-MOVT-NEXT: movt r[[ADDR]], :upper16:internal_global
-; ELF-NOMOVT: ldr r[[ADDR:[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
-; DARWIN-MOVT: movw r[[ADDR:[0-9]+]], :lower16:_internal_global
-; DARWIN-MOVT-NEXT: movt r[[ADDR]], :upper16:_internal_global
-; DARWIN-NOMOVT: ldr r[[ADDR:[0-9]+]], [[LABEL:L[[:alnum:]_]+]]
-; CHECK-NEXT: ldr r0, [r[[ADDR]]]
-; CHECK-NEXT: bx lr
-; ELF-NOMOVT: [[LABEL]]:
-; ELF-NOMOVT-NEXT: .long internal_global
-; DARWIN-NOMOVT: [[LABEL]]:
-; DARWIN-NOMOVT-NEXT: .long _internal_global
-
-entry:
-  %v = load i32, i32* @internal_global
-  ret i32 %v
-}
-
-@external_global = external global i32
-define i32 @test_external_global() {
-; CHECK-LABEL: test_external_global:
-; ELF-MOVT: movw r[[ADDR:[0-9]+]], :lower16:external_global
-; ELF-MOVT-NEXT: movt r[[ADDR]], :upper16:external_global
-; ELF-NOMOVT: ldr r[[ADDR:[0-9]+]], [[CONST_POOL:.L[[:alnum:]_]+]]
-; DARWIN-MOVT: movw r[[ADDR:[0-9]+]], :lower16:_external_global
-; DARWIN-MOVT: movt r[[ADDR]], :upper16:_external_global
-; DARWIN-NOMOVT: ldr r[[ADDR:[0-9]+]], [[LABEL:L[[:alnum:]_]+]]
-; CHECK-NEXT: ldr r0, [r[[ADDR]]]
-; CHECK-NEXT: bx lr
-; ELF-NOMOVT: [[CONST_POOL]]:
-; ELF-NOMOVT: .long external_global
-; DARWIN-NOMOVT: [[LABEL]]:
-; DARWIN-NOMOVT: .long _external_global
-entry:
-  %v = load i32, i32* @external_global
-  ret i32 %v
-}
-
-; ELF: internal_global:
-; DARWIN: _internal_global:
-; CHECK: .long 42
-; ELF: .size internal_global, 4

external/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll

@@ -1,463 +0,0 @@
-; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6 -global-isel %s -o - | FileCheck %s
-
-define void @test_void_return() {
-; CHECK-LABEL: test_void_return:
-; CHECK: bx lr
-entry:
-  ret void
-}
-
-define i32 @test_constant_return_i32() {
-; CHECK-LABEL: test_constant_return_i32:
-; CHECK: mov r0, #42
-; CHECK: bx lr
-entry:
-  ret i32 42
-}
-
-define zeroext i1 @test_zext_i1(i1 %x) {
-; CHECK-LABEL: test_zext_i1
-; CHECK: and r0, r0, #1
-; CHECK: bx lr
-entry:
-  ret i1 %x
-}
-
-define signext i1 @test_sext_i1(i1 %x) {
-; CHECK-LABEL: test_sext_i1
-; CHECK: mov	r1, #31
-; CHECK: lsl	r0, r0, r1
-; CHECK: asr	r0, r0, r1
-; CHECK: bx lr
-entry:
-  ret i1 %x
-}
-
-define zeroext i8 @test_ext_i8(i8 %x) {
-; CHECK-LABEL: test_ext_i8:
-; CHECK: uxtb r0, r0
-; CHECK: bx lr
-
-entry:
-  ret i8 %x
-}
-
-define signext i16 @test_ext_i16(i16 %x) {
-; CHECK-LABEL: test_ext_i16:
-; CHECK: mov	r1, #16
-; CHECK: lsl	r0, r0, r1
-; CHECK: asr	r0, r0, r1
-; CHECK: bx lr
-entry:
-  ret i16 %x
-}
-
-define void @test_trunc_i32_i16(i32 %v, i16 *%p) {
-; CHECK-LABEL: test_trunc_i32_i16:
-; The trunc doesn't result in any instructions, but we
-; expect the store to be explicitly 16-bit.
-; CHECK: strh r0, [r1]
-; CHECK: bx lr
-entry:
-  %v16 = trunc i32 %v to i16
-  store i16 %v16, i16 *%p
-  ret void
-}
-
-define void @test_trunc_i32_i8(i32 %v, i8 *%p) {
-; CHECK-LABEL: test_trunc_i32_i8:
-; The trunc doesn't result in any instructions, but we
-; expect the store to be explicitly 8-bit.
-; CHECK: strb r0, [r1]
-; CHECK: bx lr
-entry:
-  %v8 = trunc i32 %v to i8
-  store i8 %v8, i8 *%p
-  ret void
-}
-
-define i8 @test_add_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: test_add_i8:
-; CHECK: add r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = add i8 %x, %y
-  ret i8 %sum
-}
-
-define i16 @test_add_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: test_add_i16:
-; CHECK: add r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = add i16 %x, %y
-  ret i16 %sum
-}
-
-define i32 @test_add_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: test_add_i32:
-; CHECK: add r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = add i32 %x, %y
-  ret i32 %sum
-}
-
-define i8 @test_sub_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: test_sub_i8:
-; CHECK: sub r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = sub i8 %x, %y
-  ret i8 %sum
-}
-
-define i16 @test_sub_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: test_sub_i16:
-; CHECK: sub r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = sub i16 %x, %y
-  ret i16 %sum
-}
-
-define i32 @test_sub_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: test_sub_i32:
-; CHECK: sub r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = sub i32 %x, %y
-  ret i32 %sum
-}
-
-define i8 @test_mul_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: test_mul_i8:
-; CHECK: mul r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = mul i8 %x, %y
-  ret i8 %sum
-}
-
-define i16 @test_mul_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: test_mul_i16:
-; CHECK: mul r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = mul i16 %x, %y
-  ret i16 %sum
-}
-
-define i32 @test_mul_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: test_mul_i32:
-; CHECK: mul r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = mul i32 %x, %y
-  ret i32 %sum
-}
-
-define i8 @test_and_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: test_and_i8:
-; CHECK: and r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = and i8 %x, %y
-  ret i8 %sum
-}
-
-define i16 @test_and_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: test_and_i16:
-; CHECK: and r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = and i16 %x, %y
-  ret i16 %sum
-}
-
-define i32 @test_and_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: test_and_i32:
-; CHECK: and r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = and i32 %x, %y
-  ret i32 %sum
-}
-
-define i8 @test_or_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: test_or_i8:
-; CHECK: orr r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = or i8 %x, %y
-  ret i8 %sum
-}
-
-define i16 @test_or_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: test_or_i16:
-; CHECK: orr r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = or i16 %x, %y
-  ret i16 %sum
-}
-
-define i32 @test_or_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: test_or_i32:
-; CHECK: orr r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = or i32 %x, %y
-  ret i32 %sum
-}
-
-define i8 @test_xor_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: test_xor_i8:
-; CHECK: eor r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = xor i8 %x, %y
-  ret i8 %sum
-}
-
-define i16 @test_xor_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: test_xor_i16:
-; CHECK: eor r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = xor i16 %x, %y
-  ret i16 %sum
-}
-
-define i32 @test_xor_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: test_xor_i32:
-; CHECK: eor r0, r0, r1
-; CHECK: bx lr
-entry:
-  %sum = xor i32 %x, %y
-  ret i32 %sum
-}
-
-define i32 @test_stack_args_i32(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
-; CHECK-LABEL: test_stack_args_i32:
-; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
-; CHECK: ldr [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
-; CHECK: add r0, r2, [[P5]]
-; CHECK: bx lr
-entry:
-  %sum = add i32 %p2, %p5
-  ret i32 %sum
-}
-
-define i16 @test_stack_args_mixed(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 %p4, i16 %p5) {
-; CHECK-LABEL: test_stack_args_mixed:
-; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
-; CHECK: ldrh [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
-; CHECK: add r0, r1, [[P5]]
-; CHECK: bx lr
-entry:
-  %sum = add i16 %p1, %p5
-  ret i16 %sum
-}
-
-define i16 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i16 zeroext %p4) {
-; CHECK-LABEL: test_stack_args_zeroext:
-; CHECK: mov [[P4ADDR:r[0-9]+]], sp
-; CHECK: ldr [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
-; CHECK: add r0, r1, [[P4]]
-; CHECK: bx lr
-entry:
-  %sum = add i16 %p1, %p4
-  ret i16 %sum
-}
-
-define i8 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 signext %p4) {
-; CHECK-LABEL: test_stack_args_signext:
-; CHECK: mov [[P4ADDR:r[0-9]+]], sp
-; CHECK: ldr [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
-; CHECK: add r0, r2, [[P4]]
-; CHECK: bx lr
-entry:
-  %sum = add i8 %p2, %p4
-  ret i8 %sum
-}
-
-define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 %p4) {
-; CHECK-LABEL: test_stack_args_noext:
-; CHECK: mov [[P4ADDR:r[0-9]+]], sp
-; CHECK: ldrb [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
-; CHECK: add r0, r2, [[P4]]
-; CHECK: bx lr
-entry:
-  %sum = add i8 %p2, %p4
-  ret i8 %sum
-}
-
-define i32 @test_ptr_arg_in_reg(i32* %p) {
-; CHECK-LABEL: test_ptr_arg_in_reg:
-; CHECK: ldr r0, [r0]
-; CHECK: bx lr
-entry:
-  %v = load i32, i32* %p
-  ret i32 %v
-}
-
-define i32 @test_ptr_arg_on_stack(i32 %f0, i32 %f1, i32 %f2, i32 %f3, i32* %p) {
-; CHECK-LABEL: test_ptr_arg_on_stack:
-; CHECK: mov r0, sp
-; CHECK: ldr r0, [r0]
-; CHECK: ldr r0, [r0]
-; CHECK: bx lr
-entry:
-  %v = load i32, i32* %p
-  ret i32 %v
-}
-
-define i8* @test_ptr_ret(i8** %p) {
-; CHECK-LABEL: test_ptr_ret:
-; CHECK: ldr r0, [r0]
-; CHECK: bx lr
-entry:
-  %v = load i8*, i8** %p
-  ret i8* %v
-}
-
-define arm_aapcs_vfpcc float @test_float_hard(float %f0, float %f1) {
-; CHECK-LABEL: test_float_hard:
-; CHECK: vadd.f32 s0, s0, s1
-; CHECK: bx lr
-entry:
-  %v = fadd float %f0, %f1
-  ret float %v
-}
-
-define arm_aapcscc float @test_float_softfp(float %f0, float %f1) {
-; CHECK-LABEL: test_float_softfp:
-; CHECK-DAG: vmov [[F0:s[0-9]+]], r0
-; CHECK-DAG: vmov [[F1:s[0-9]+]], r1
-; CHECK: vadd.f32 [[FV:s[0-9]+]], [[F0]], [[F1]]
-; CHECK: vmov r0, [[FV]]
-; CHECK: bx lr
-entry:
-  %v = fadd float %f0, %f1
-  ret float %v
-}
-
-define arm_aapcs_vfpcc double @test_double_hard(double %f0, double %f1) {
-; CHECK-LABEL: test_double_hard:
-; CHECK: vadd.f64 d0, d0, d1
-; CHECK: bx lr
-entry:
-  %v = fadd double %f0, %f1
-  ret double %v
-}
-
-define arm_aapcscc double @test_double_softfp(double %f0, double %f1) {
-; CHECK-LABEL: test_double_softfp:
-; CHECK-DAG: vmov [[F0:d[0-9]+]], r0, r1
-; CHECK-DAG: vmov [[F1:d[0-9]+]], r2, r3
-; CHECK: vadd.f64 [[FV:d[0-9]+]], [[F0]], [[F1]]
-; CHECK: vmov r0, r1, [[FV]]
-; CHECK: bx lr
-entry:
-  %v = fadd double %f0, %f1
-  ret double %v
-}
-
-define arm_aapcscc i32 @test_cmp_i32_eq(i32 %a, i32 %b) {
-; CHECK-LABEL: test_cmp_i32_eq:
-; CHECK: mov [[V:r[0-9]+]], #0
-; CHECK: cmp r0, r1
-; CHECK: moveq [[V]], #1
-; CHECK: and r0, [[V]], #1
-; CHECK: bx lr
-entry:
-  %v = icmp eq i32 %a, %b
-  %r = zext i1 %v to i32
-  ret i32 %r
-}
-
-define arm_aapcscc i32 @test_cmp_ptr_neq(double *%a, double *%b) {
-; CHECK-LABEL: test_cmp_ptr_neq:
-; CHECK: mov [[V:r[0-9]+]], #0
-; CHECK: cmp r0, r1
-; CHECK: movne [[V]], #1
-; CHECK: and r0, [[V]], #1
-; CHECK: bx lr
-entry:
-  %v = icmp ne double * %a, %b
-  %r = zext i1 %v to i32
-  ret i32 %r
-}
-
-define arm_aapcscc i32 @test_cmp_i16_slt(i16 %a, i16 %b) {
-; CHECK-LABEL: test_cmp_i16_slt:
-; CHECK-DAG: mov [[V:r[0-9]+]], #0
-; CHECK: cmp r0, r1
-; CHECK: movlt [[V]], #1
-; CHECK: and r0, [[V]], #1
-; CHECK: bx lr
-entry:
-  %v = icmp slt i16 %a, %b
-  %r = zext i1 %v to i32
-  ret i32 %r
-}
-
-define arm_aapcscc i32 @test_select_i32(i32 %a, i32 %b, i1 %cond) {
-; CHECK-LABEL: test_select_i32
-; CHECK: cmp r2, #0
-; CHECK: moveq r0, r1
-; CHECK: bx lr
-entry:
-  %r = select i1 %cond, i32 %a, i32 %b
-  ret i32 %r
-}
-
-define arm_aapcscc i32* @test_select_ptr(i32* %a, i32* %b, i1 %cond) {
-; CHECK-LABEL: test_select_ptr
-; CHECK: cmp r2, #0
-; CHECK: moveq r0, r1
-; CHECK: bx lr
-entry:
-  %r = select i1 %cond, i32* %a, i32* %b
-  ret i32* %r
-}
-
-define arm_aapcscc void @test_br() {
-; CHECK-LABEL: test_br
-; CHECK: [[LABEL:.L[[:alnum:]_]+]]:
-; CHECK: b [[LABEL]]
-entry:
-  br label %infinite
-
-infinite:
-  br label %infinite
-}
-
-declare arm_aapcscc void @brcond1()
-declare arm_aapcscc void @brcond2()
-
-define arm_aapcscc void @test_brcond(i32 %n) {
-; CHECK-LABEL: test_brcond
-; CHECK: cmp r0
-; CHECK-NEXT: movgt [[RCMP:r[0-9]+]], #1
-; CHECK: tst [[RCMP]], #1
-; CHECK-NEXT: beq [[FALSE:.L[[:alnum:]_]+]]
-; CHECK: bl brcond1
-; CHECK: [[FALSE]]:
-; CHECK: bl brcond2
-entry:
-  %cmp = icmp sgt i32 %n, 0
-  br i1 %cmp, label %if.true, label %if.false
-
-if.true:
-  call arm_aapcscc void @brcond1()
-  br label %if.end
-
-if.false:
-  call arm_aapcscc void @brcond2()
-  br label %if.end
-
-if.end:
-  ret void
-}

external/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll

@@ -1,477 +0,0 @@
-; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE
-; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG
-; XFAIL: armeb
-
-declare arm_aapcscc i32* @simple_reg_params_target(i32, i32*)
-
-define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
-; CHECK-LABEL: name: test_call_simple_reg_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %r0 = COPY [[BVREG]]
-; CHECK-DAG: %r1 = COPY [[AVREG]]
-; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0
-; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %r0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
-entry:
-  %r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a)
-  ret i32 *%r
-}
-
-declare arm_aapcscc i32* @simple_stack_params_target(i32, i32*, i32, i32*, i32, i32*)
-
-define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
-; CHECK-LABEL: name: test_call_simple_stack_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %r0 = COPY [[BVREG]]
-; CHECK-DAG: %r1 = COPY [[AVREG]]
-; CHECK-DAG: %r2 = COPY [[BVREG]]
-; CHECK-DAG: %r3 = COPY [[AVREG]]
-; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
-; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
-; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4
-; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %r0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
-entry:
-  %r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
-  ret i32 *%r
-}
-
-declare arm_aapcscc signext i16 @ext_target(i8 signext, i8 zeroext, i16 signext, i16 zeroext, i8 signext, i8 zeroext, i16 signext, i16 zeroext, i1 zeroext)
-
-define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
-; CHECK-LABEL: name: test_call_ext_params
-; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s8) = G_TRUNC [[R0VREG]]
-; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]]
-; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]]
-; CHECK: ADJCALLSTACKDOWN 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8)
-; CHECK: %r0 = COPY [[SEXTA]]
-; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8)
-; CHECK: %r1 = COPY [[ZEXTA]]
-; CHECK: [[SEXTB:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]](s16)
-; CHECK: %r2 = COPY [[SEXTB]]
-; CHECK: [[ZEXTB:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]](s16)
-; CHECK: %r3 = COPY [[ZEXTB]]
-; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
-; CHECK: [[SEXTA2:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]]
-; CHECK: G_STORE [[SEXTA2]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
-; CHECK: [[ZEXTA2:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]]
-; CHECK: G_STORE [[ZEXTA2]](s32), [[FI2]](p0){{.*}}store 4
-; CHECK: [[SP3:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-; CHECK: [[FI3:%[0-9]+]]:_(p0) = G_GEP [[SP3]], [[OFF3]](s32)
-; CHECK: [[SEXTB2:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]]
-; CHECK: G_STORE [[SEXTB2]](s32), [[FI3]](p0){{.*}}store 4
-; CHECK: [[SP4:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
-; CHECK: [[FI4:%[0-9]+]]:_(p0) = G_GEP [[SP4]], [[OFF4]](s32)
-; CHECK: [[ZEXTB2:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]]
-; CHECK: G_STORE [[ZEXTB2]](s32), [[FI4]](p0){{.*}}store 4
-; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_GEP [[SP5]], [[OFF5]](s32)
-; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]]
-; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4
-; CHECK: BL @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]]
-; CHECK: ADJCALLSTACKUP 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]]
-; CHECK: %r0 = COPY [[RExtVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
-entry:
-  %r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c)
-  ret i16 %r
-}
-
-declare arm_aapcs_vfpcc double @vfpcc_fp_target(float, double)
-
-define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
-; CHECK-LABEL: name: test_call_vfpcc_fp_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %s2
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %s0 = COPY [[BVREG]]
-; CHECK-DAG: %d1 = COPY [[AVREG]]
-; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0
-; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %d0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %d0
-entry:
-  %r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a)
-  ret double %r
-}
-
-declare arm_aapcscc double @aapcscc_fp_target(float, double, float, double)
-
-define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
-; CHECK-LABEL: name: test_call_aapcs_fp_params
-; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY %r1
-; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
-; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: ADJCALLSTACKDOWN 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %r0 = COPY [[BVREG]]
-; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64)
-; LITTLE-DAG: %r2 = COPY [[A1]]
-; LITTLE-DAG: %r3 = COPY [[A2]]
-; BIG-DAG: %r2 = COPY [[A2]]
-; BIG-DAG: %r3 = COPY [[A1]]
-; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
-; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
-; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8
-; CHECK: BL @aapcscc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r1
-; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
-; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64)
-; LITTLE-DAG: %r0 = COPY [[R1]]
-; LITTLE-DAG: %r1 = COPY [[R2]]
-; BIG-DAG: %r0 = COPY [[R2]]
-; BIG-DAG: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
-entry:
-  %r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a)
-  ret double %r
-}
-
-declare arm_aapcscc float @different_call_conv_target(float)
-
-define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
-; CHECK-LABEL: name: test_call_different_call_conv
-; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %r0 = COPY [[X]]
-; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0
-; CHECK: [[R:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %s0 = COPY [[R]]
-; CHECK: BX_RET 14, %noreg, implicit %s0
-entry:
-  %r = notail call arm_aapcscc float @different_call_conv_target(float %x)
-  ret float %r
-}
-
-declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32])
-
-define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
-; CHECK-LABEL: name: test_tiny_int_arrays
-; CHECK: liveins: %r0, %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[ARG_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: BL @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: [[RES_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32)
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s96)
-; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
-; that composite types larger than 4 bytes should be passed through memory),
-; but it's what DAGISel does. We should fix it in the common code for both.
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1, implicit %r2
-entry:
-  %r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr)
-  ret [3 x i32] %r
-}
-
-declare arm_aapcscc void @multiple_int_arrays_target([2 x i32], [2 x i32])
-
-define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) {
-; CHECK-LABEL: name: test_multiple_int_arrays
-; CHECK: liveins: %r0, %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %r3
-; CHECK: [[ARG_ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: [[ARG_ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64)
-; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: %r3 = COPY [[R3]]
-; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: BX_RET 14, %noreg
-entry:
-  notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1)
-  ret void
-}
-
-declare arm_aapcscc void @large_int_arrays_target([20 x i32])
-
-define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
-; CHECK-LABEL: name: test_large_int_arrays
-; CHECK: fixedStack:
-; The parameters live in separate stack locations, one for each element that
-; doesn't fit in the registers.
-; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
-; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
-; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[ARG_ARR:%[0-9]+]]:_(s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
-; CHECK: ADJCALLSTACKDOWN 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: %r3 = COPY [[R3]]
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
-; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
-; Match the second-to-last offset, so we can get the correct SP for the last element
-; CHECK: G_CONSTANT i32 56
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60
-; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
-; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
-; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
-; CHECK: ADJCALLSTACKUP 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: BX_RET 14, %noreg
-entry:
-  notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr)
-  ret void
-}
-
-declare arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double])
-
-define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
-; CHECK-LABEL: name: test_fp_arrays_aapcs
-; CHECK: fixedStack:
-; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8,
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY %r1
-; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
-; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
-; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY %r3
-; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
-; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
-; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
-; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
-; CHECK: [[ARR_MERGED:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64)
-; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192)
-; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
-; LITTLE: %r0 = COPY [[ARR0_0]](s32)
-; LITTLE: %r1 = COPY [[ARR0_1]](s32)
-; BIG: %r0 = COPY [[ARR0_1]](s32)
-; BIG: %r1 = COPY [[ARR0_0]](s32)
-; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64)
-; LITTLE: %r2 = COPY [[ARR1_0]](s32)
-; LITTLE: %r3 = COPY [[ARR1_1]](s32)
-; BIG: %r2 = COPY [[ARR1_1]](s32)
-; BIG: %r3 = COPY [[ARR1_0]](s32)
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32)
-; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8
-; CHECK: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[R_MERGED:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
-entry:
-  %r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr)
-  ret [2 x float] %r
-}
-
-declare arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double], [3 x float], [4 x double])
-
-define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) {
-; CHECK-LABEL: name: test_fp_arrays_aapcs_vfp
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[Z0_ID:[0-9]+]], type: default, offset: 0, size: 8,
-; CHECK-DAG: id: [[Z1_ID:[0-9]+]], type: default, offset: 8, size: 8,
-; CHECK-DAG: id: [[Z2_ID:[0-9]+]], type: default, offset: 16, size: 8,
-; CHECK-DAG: id: [[Z3_ID:[0-9]+]], type: default, offset: 24, size: 8,
-; CHECK: liveins: %d0, %d1, %d2, %s6, %s7, %s8
-; CHECK: [[X0:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK: [[X1:%[0-9]+]]:_(s64) = COPY %d1
-; CHECK: [[X2:%[0-9]+]]:_(s64) = COPY %d2
-; CHECK: [[Y0:%[0-9]+]]:_(s32) = COPY %s6
-; CHECK: [[Y1:%[0-9]+]]:_(s32) = COPY %s7
-; CHECK: [[Y2:%[0-9]+]]:_(s32) = COPY %s8
-; CHECK: [[Z0_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]
-; CHECK: [[Z0:%[0-9]+]]:_(s64) = G_LOAD [[Z0_FI]]{{.*}}load 8
-; CHECK: [[Z1_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]]
-; CHECK: [[Z1:%[0-9]+]]:_(s64) = G_LOAD [[Z1_FI]]{{.*}}load 8
-; CHECK: [[Z2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]]
-; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8
-; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]
-; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8
-; CHECK: [[X_ARR:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64)
-; CHECK: [[Y_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32)
-; CHECK: [[Z_ARR:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64)
-; CHECK: ADJCALLSTACKDOWN 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[X_ARR]](s192)
-; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[Y_ARR]](s96)
-; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[Z_ARR]](s256)
-; CHECK: %d0 = COPY [[X0]](s64)
-; CHECK: %d1 = COPY [[X1]](s64)
-; CHECK: %d2 = COPY [[X2]](s64)
-; CHECK: %s6 = COPY [[Y0]](s32)
-; CHECK: %s7 = COPY [[Y1]](s32)
-; CHECK: %s8 = COPY [[Y2]](s32)
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[Z0_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[Z0_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z0_OFFSET]](s32)
-; CHECK: G_STORE [[Z0]](s64), [[Z0_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[Z1_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-; CHECK: [[Z1_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z1_OFFSET]](s32)
-; CHECK: G_STORE [[Z1]](s64), [[Z1_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[Z2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-; CHECK: [[Z2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z2_OFFSET]](s32)
-; CHECK: G_STORE [[Z2]](s64), [[Z2_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[Z3_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
-; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32)
-; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8
-; CHECK: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %s0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %s1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %s2
-; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %s3
-; CHECK: [[R_MERGED:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32)
-; CHECK: ADJCALLSTACKUP 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s128)
-; CHECK: %s0 = COPY [[R0]]
-; CHECK: %s1 = COPY [[R1]]
-; CHECK: %s2 = COPY [[R2]]
-; CHECK: %s3 = COPY [[R3]]
-; CHECK: BX_RET 14, %noreg, implicit %s0, implicit %s1, implicit %s2, implicit %s3
-entry:
-  %r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z)
-  ret [4 x float] %r
-}
-
-declare arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
-
-define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
-; CHECK-LABEL: name: test_tough_arrays
-; CHECK: fixedStack:
-; The parameters live in separate stack locations, one for each element that
-; doesn't fit in the registers.
-; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
-; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
-; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[ARG_ARR:%[0-9]+]]:_(s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
-; CHECK: ADJCALLSTACKDOWN 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: %r3 = COPY [[R3]]
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
-; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
-; Match the second-to-last offset, so we can get the correct SP for the last element
-; CHECK: G_CONSTANT i32 72
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
-; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76
-; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
-; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
-; CHECK: BL @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[RES_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
-entry:
-  %r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
-  ret [2 x i32*] %r
-}
-
-declare arm_aapcscc {i32, i32} @structs_target({i32, i32})
-
-define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
-; CHECK-LABEL: test_structs
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
-; CHECK-DAG: %r0 = COPY [[X0]](s32)
-; CHECK-DAG: %r1 = COPY [[X1]](s32)
-; CHECK: BL @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[R:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
-; CHECK: %r0 = COPY [[R0]](s32)
-; CHECK: %r1 = COPY [[R1]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
-  %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x)
-  ret {i32, i32} %r
-}

external/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir

@@ -1,121 +0,0 @@
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=pic -mattr=+no-movt -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,ELF
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=pic -mattr=-no-movt,+v8m -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,ELF
-# RUN: llc -O0 -mtriple arm-darwin -relocation-model=pic -mattr=+no-movt -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,DARWIN-NOMOVT
-# RUN: llc -O0 -mtriple arm-darwin -relocation-model=pic -mattr=-no-movt,+v8m -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,DARWIN-MOVT
---- |
-  @internal_global = internal global i32 42
-  define void @test_internal_global() { ret void }
-
-  @external_global = external global i32
-  define void @test_external_global() { ret void }
-
-  @internal_constant = internal constant i32 42
-  define void @test_internal_constant() { ret void }
-
-  @external_constant = external constant i32
-  define void @test_external_constant() { ret void }
-...
----
-name:            test_internal_global
-# CHECK-LABEL: name: test_internal_global
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @internal_global
-    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel {{.*}}@internal_global
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global
-    ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...
----
-name:            test_external_global
-# CHECK-LABEL: name: test_external_global
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @external_global
-    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr {{.*}} @external_global :: (load 4 from got)
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr {{.*}}@external_global :: (load 4 from got)
-    ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(<unknown>) @external_global :: (load 4 from got)
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...
----
-name:            test_internal_constant
-# CHECK-LABEL: name: test_internal_constant
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @internal_constant
-    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel {{.*}}@internal_constant
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant
-    ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...
----
-name:            test_external_constant
-# CHECK-LABEL: name: test_external_constant
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @external_constant
-    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr {{.*}} @external_constant :: (load 4 from got)
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr {{.*}}@external_constant :: (load 4 from got)
-    ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(<unknown>) @external_constant :: (load 4 from got)
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...

external/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir

@@ -1,147 +0,0 @@
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=ropi -mattr=-no-movt,+v8m -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RW-DEFAULT-MOVT,RW-DEFAULT,ROPI-MOVT,ROPI
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=ropi -mattr=+no-movt -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RW-DEFAULT-NOMOVT,RW-DEFAULT,ROPI-NOMOVT,ROPI
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=rwpi -mattr=-no-movt,+v8m -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-MOVT,RWPI,RO-DEFAULT-MOVT,RO-DEFAULT
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=rwpi -mattr=+no-movt -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-NOMOVT,RWPI,RO-DEFAULT-NOMOVT,RO-DEFAULT
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=ropi-rwpi -mattr=-no-movt,+v8m -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-MOVT,RWPI,ROPI-MOVT,ROPI
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=ropi-rwpi -mattr=+no-movt -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-NOMOVT,RWPI,ROPI-NOMOVT,ROPI
---- |
-  @internal_global = internal global i32 42
-  define void @test_internal_global() { ret void }
-
-  @external_global = external global i32
-  define void @test_external_global() { ret void }
-
-  @internal_constant = internal constant i32 42
-  define void @test_internal_constant() { ret void }
-
-  @external_constant = external constant i32
-  define void @test_external_constant() { ret void }
-...
----
-name:            test_internal_global
-# CHECK-LABEL: name: test_internal_global
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-# RW-DEFAULT-NOMOVT: constants:
-# RW-DEFAULT-NOMOVT: id: 0
-# RW-DEFAULT-NOMOVT: value: 'i32* @internal_global'
-# RWPI-NOMOVT: constants:
-# RWPI-NOMOVT: id: 0
-# RWPI-NOMOVT: value: 'internal_global(SBREL)'
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @internal_global
-    ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
-    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
-    ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @internal_global
-    ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
-    ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...
----
-name:            test_external_global
-# CHECK-LABEL: name: test_external_global
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-# RW-DEFAULT-NOMOVT: constants:
-# RW-DEFAULT-NOMOVT: id: 0
-# RW-DEFAULT-NOMOVT: value: 'i32* @external_global'
-# RWPI-NOMOVT: constants:
-# RWPI-NOMOVT: id: 0
-# RWPI-NOMOVT: value: 'external_global(SBREL)'
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @external_global
-    ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
-    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
-    ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @external_global
-    ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
-    ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...
----
-name:            test_internal_constant
-# CHECK-LABEL: name: test_internal_constant
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-# RO-DEFAULT-NOMOVT: constants:
-# RO-DEFAULT-NOMOVT: id: 0
-# RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant'
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @internal_constant
-    ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant
-    ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant
-    ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
-    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...
----
-name:            test_external_constant
-# CHECK-LABEL: name: test_external_constant
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-# RO-DEFAULT-NOMOVT: constants:
-# RO-DEFAULT-NOMOVT: id: 0
-# RO-DEFAULT-NOMOVT: value: 'i32* @external_constant'
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @external_constant
-    ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant
-    ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant
-    ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant
-    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...

external/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir

@@ -1,71 +0,0 @@
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=static -mattr=+no-movt -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,ELF-NOMOVT
-# RUN: llc -O0 -mtriple arm-linux -relocation-model=static -mattr=-no-movt,+v8m -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,ELF-MOVT
-# RUN: llc -O0 -mtriple arm-darwin -relocation-model=static -mattr=+no-movt -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,DARWIN-NOMOVT
-# RUN: llc -O0 -mtriple arm-darwin -relocation-model=static -mattr=-no-movt,+v8m -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,DARWIN-MOVT
---- |
-  @internal_global = internal global i32 42
-  define void @test_internal_global() { ret void }
-
-  @external_global = external global i32
-  define void @test_external_global() { ret void }
-...
----
-name:            test_internal_global
-# CHECK-LABEL: name: test_internal_global
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-# ELF-NOMOVT: constants:
-# ELF-NOMOVT: id: 0
-# ELF-NOMOVT: value: 'i32* @internal_global'
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @internal_global
-    ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
-    ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
-    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...
----
-name:            test_external_global
-# CHECK-LABEL: name: test_external_global
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-# ELF-NOMOVT: constants:
-# ELF-NOMOVT: id: 0
-# ELF-NOMOVT: value: 'i32* @external_global'
-body:             |
-  bb.0:
-    %0(p0) = G_GLOBAL_VALUE @external_global
-    ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
-    ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
-    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global
-
-    %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
-
-    %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[V]]
-
-    BX_RET 14, %noreg, implicit %r0
-    ; CHECK: BX_RET 14, %noreg, implicit %r0
-...

external/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll

@@ -1,131 +0,0 @@
-; RUN: llc -mtriple arm-unknown -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o - 2>&1 | FileCheck %s -check-prefixes=CHECK
-; RUN: llc -mtriple arm-unknown -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -relocation-model=pic %s -o - 2>&1 | FileCheck %s -check-prefixes=PIC
-; RUN: llc -mtriple arm-unknown -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -relocation-model=ropi %s -o - 2>&1 | FileCheck %s -check-prefixes=ROPI
-; RUN: llc -mtriple arm-unknown -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -relocation-model=rwpi %s -o - 2>&1 | FileCheck %s -check-prefixes=RWPI
-; RUN: llc -mtriple arm-unknown -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -relocation-model=ropi-rwpi %s -o - 2>&1 | FileCheck %s -check-prefixes=ROPI-RWPI
-
-; This file checks that we use the fallback path for things that are known to
-; be unsupported on the ARM target. It should progressively shrink in size.
-
-define <4 x i32> @test_int_vectors(<4 x i32> %a, <4 x i32> %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: <4 x i32> (<4 x i32>, <4 x i32>)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_int_vectors
-  %res = add <4 x i32> %a, %b
-  ret <4 x i32> %res
-}
-
-define <4 x float> @test_float_vectors(<4 x float> %a, <4 x float> %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: <4 x float> (<4 x float>, <4 x float>)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_float_vectors
-  %res = fadd <4 x float> %a, %b
-  ret <4 x float> %res
-}
-
-define i64 @test_i64(i64 %a, i64 %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: i64 (i64, i64)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_i64
-  %res = add i64 %a, %b
-  ret i64 %res
-}
-
-define i128 @test_i128(i128 %a, i128 %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: i128 (i128, i128)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_i128
-  %res = add i128 %a, %b
-  ret i128 %res
-}
-
-define i17 @test_funny_ints(i17 %a, i17 %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: i17 (i17, i17)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_funny_ints
-  %res = add i17 %a, %b
-  ret i17 %res
-}
-
-define half @test_half(half %a, half %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: half (half, half)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_half
-  %res = fadd half %a, %b
-  ret half %res
-}
-
-declare [16 x i32] @ret_demotion_target()
-
-define [16 x i32] @test_ret_demotion() {
-; CHECK: remark: {{.*}} unable to translate instruction: call{{.*}} @ret_demotion_target
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_ret_demotion
-  %res = call [16 x i32] @ret_demotion_target()
-  ret [16 x i32] %res
-}
-
-%large.struct = type { i32, i32, i32, i32, i32} ; Doesn't fit in R0-R3
-
-declare %large.struct @large_struct_return_target()
-
-define %large.struct @test_large_struct_return() {
-; CHECK: remark: {{.*}} unable to translate instruction: call{{.*}} @large_struct_return_target
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_large_struct_return
-  %r = call %large.struct @large_struct_return_target()
-  ret %large.struct %r
-}
-
-%mixed.struct = type {i32*, float, i32}
-
-define %mixed.struct @test_mixed_struct(%mixed.struct %x) {
-; CHECK: remark: {{.*}} unable to lower arguments: %mixed.struct (%mixed.struct)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_mixed_struct
-  ret %mixed.struct %x
-}
-
-define void @test_vararg_definition(i32 %a, ...) {
-; CHECK: remark: {{.*}} unable to lower arguments: void (i32, ...)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_vararg_definition
-  ret void
-}
-
-define void @test_vararg_call(i32 %a) {
-; CHECK: remark: {{.*}} unable to translate instruction: call
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_vararg_call
-  call void(i32, ...) @test_vararg_definition(i32 %a, i32 %a, i32 %a)
-  ret void
-}
-
-define i32 @test_thumb(i32 %a) #0 {
-; CHECK: remark: {{.*}} unable to lower arguments: i32 (i32)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_thumb
-  ret i32 %a
-}
-
-@thread_local_global = thread_local global i32 42
-
-define i32 @test_thread_local_global() {
-; CHECK: remark: {{.*}} cannot select: {{.*}} G_GLOBAL_VALUE
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_thread_local_global
-; PIC: remark: {{.*}} cannot select: {{.*}} G_GLOBAL_VALUE
-; PIC-LABEL: warning: Instruction selection used fallback path for test_thread_local_global
-; ROPI: remark: {{.*}} cannot select: {{.*}} G_GLOBAL_VALUE
-; ROPI-LABEL: warning: Instruction selection used fallback path for test_thread_local_global
-; RWPI: remark: {{.*}} cannot select: {{.*}} G_GLOBAL_VALUE
-; RWPI-LABEL: warning: Instruction selection used fallback path for test_thread_local_global
-; ROPI-RWPI: remark: {{.*}} cannot select: {{.*}} G_GLOBAL_VALUE
-; ROPI-RWPI-LABEL: warning: Instruction selection used fallback path for test_thread_local_global
-  %v = load i32, i32* @thread_local_global
-  ret i32 %v
-}
-
-%byval.class = type { i32 }
-
-define void @test_byval_arg(%byval.class* byval %x) {
-; CHECK: remark: {{.*}} unable to lower arguments: void (%byval.class*)*
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval
-  ret void
-}
-
-define void @test_byval_param(%byval.class* %x) {
-; CHECK: remark: {{.*}} unable to translate instruction: call
-; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval_param
-  call void @test_byval_arg(%byval.class* byval %x)
-  ret void
-}
-
-attributes #0 = { "target-features"="+thumb-mode" }